/**
  ******************************************************************************
  * @file    py32f420_hal_rcc_ex.h
  * @author  MCU Application Team
  * @brief   Header file of RCC HAL Extended module.
  ******************************************************************************
  * @attention
  *
  * <h2><center>&copy; Copyright (c) 2023 Puya Semiconductor Co.
  * All rights reserved.</center></h2>
  *
  * This software component is licensed by Puya under BSD 3-Clause license,
  * the "License"; You may not use this file except in compliance with the
  * License. You may obtain a copy of the License at:
  *                        opensource.org/licenses/BSD-3-Clause
  *
  ******************************************************************************
  * @attention
  *
  * <h2><center>&copy; Copyright (c) 2016 STMicroelectronics.
  * All rights reserved.</center></h2>
  *
  * This software component is licensed by ST under BSD 3-Clause license,
  * the "License"; You may not use this file except in compliance with the
  * License. You may obtain a copy of the License at:
  *                        opensource.org/licenses/BSD-3-Clause
  *
  ******************************************************************************
  */

/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __PY32F420_HAL_RCC_EX_H
#define __PY32F420_HAL_RCC_EX_H

#ifdef __cplusplus
extern "C" {
#endif

/* Includes ------------------------------------------------------------------*/
#include "py32f420_hal_def.h"

/** @addtogroup PY32F420_HAL_Driver
  * @{
  */

/** @addtogroup RCCEx
  * @{
  */

/* Private Constants ---------------------------------------------------------*/
/** @addtogroup RCCEx_Private_Constants
 * @{
 */

/**
  * @}
  */

/* Private Macros ------------------------------------------------------------*/
/** @addtogroup RCCEx_Private_Macros
 * @{
 */

#define IS_RCC_PLL_MUL(__MUL__)      (((__MUL__) == RCC_PLL_MUL2)  || ((__MUL__) == RCC_PLL_MUL3) || \
                                      ((__MUL__) == RCC_PLL_MUL4)  || ((__MUL__) == RCC_PLL_MUL5) || \
                                      ((__MUL__) == RCC_PLL_MUL6)  || ((__MUL__) == RCC_PLL_MUL7) || \
                                      ((__MUL__) == RCC_PLL_MUL8)  || ((__MUL__) == RCC_PLL_MUL9) || \
                                      ((__MUL__) == RCC_PLL_MUL10)  || ((__MUL__) == RCC_PLL_MUL11) || \
                                      ((__MUL__) == RCC_PLL_MUL12)  || ((__MUL__) == RCC_PLL_MUL13) || \
                                      ((__MUL__) == RCC_PLL_MUL14)  || ((__MUL__) == RCC_PLL_MUL15) || \
                                      ((__MUL__) == RCC_PLL_MUL16))

#define IS_RCC_MCOSOURCE(__SOURCE__) (((__SOURCE__) == RCC_MCOSOURCE_NOCLOCK)  || ((__SOURCE__) == RCC_MCOSOURCE_SYSCLK) || \
                                      ((__SOURCE__) == RCC_MCOSOURCE_HSI)      || ((__SOURCE__) == RCC_MCOSOURCE_HSE)    || \
                                      ((__SOURCE__) == RCC_MCOSOURCE_PLLCLK)   || ((__SOURCE__) == RCC_MCOSOURCE_LSI)    || \
                                      ((__SOURCE__) == RCC_MCOSOURCE_LSE)      || ((__SOURCE__) == RCC_MCOSOURCE_HSI10M) || \
                                      ((__SOURCE__) == RCC_MCOSOURCE_HCLK)     || ((__SOURCE__) == RCC_MCOSOURCE_PCLK1)  || \
                                      ((__SOURCE__) == RCC_MCOSOURCE_PCLK2))

#define IS_RCC_ADCCLKSOURCE(__ADCCLK__) (((__ADCCLK__) == RCC_ADCCLKSOURCE_SYSCLK)  || ((__ADCCLK__) == RCC_ADCCLKSOURCE_PLL)   || \
                                         ((__ADCCLK__) == RCC_ADCCLKSOURCE_HSI)     || ((__ADCCLK__) == RCC_ADCCLKSOURCE_HSE))

#define IS_RCC_FDCANCLKSOURCE(__FDCANCLK__)  (((__FDCANCLK__) == RCC_FDCANCLKSOURCE_PLL)      || ((__FDCANCLK__) == RCC_FDCANCLKSOURCE_PCLK1)   || \
                                              ((__FDCANCLK__) == RCC_FDCANCLKSOURCE_HSE))

#define IS_RCC_PVDFILTERCLK(__PVDFILTERCLK__) (((__PVDFILTERCLK__) == RCC_PVDFILTERCLK_LSI)  || ((__PVDFILTERCLK__) == RCC_PVDFILTERCLK_LSE)  || \
                                               ((__PVDFILTERCLK__) == RCC_PVDFILTERCLK_PCLK1))

#define IS_RCC_USARTCLKSOURCE(__SOURCE__) (((__SOURCE__) == RCC_USARTCLKSOURCE_PCLK2)  || ((__SOURCE__) == RCC_USARTCLKSOURCE_SYSCLK) || \
                                            ((__SOURCE__) == RCC_USARTCLKSOURCE_LSE)    || ((__SOURCE__) == RCC_USARTCLKSOURCE_HSI))

#define IS_RCC_LPUARTCLKSOURCE(__SOURCE__) (((__SOURCE__) == RCC_LPUARTCLKSOURCE_PCLK1)  || ((__SOURCE__) == RCC_LPUARTCLKSOURCE_SYSCLK) || \
                                             ((__SOURCE__) == RCC_LPUARTCLKSOURCE_LSE)    || ((__SOURCE__) == RCC_LPUARTCLKSOURCE_HSI))

#define IS_RCC_LPTIMCLKSOURCE(__SOURCE__) (((__SOURCE__) == RCC_LPTIMCLKSOURCE_PCLK1) || ((__SOURCE__) == RCC_LPTIMCLKSOURCE_LSI)   || \
                                            ((__SOURCE__) == RCC_LPTIMCLKSOURCE_HSI)   || ((__SOURCE__) == RCC_LPTIMCLKSOURCE_LSE))

#define IS_RCC_COMP1CLKSOURCE(__SOURCE__) (((__SOURCE__) == RCC_COMP1CLKSOURCE_PCLK2) || ((__SOURCE__) == RCC_COMP1CLKSOURCE_LSI)   || \
                                           ((__SOURCE__) == RCC_COMP1CLKSOURCE_LSE))

#define IS_RCC_COMP2CLKSOURCE(__SOURCE__) (((__SOURCE__) == RCC_COMP2CLKSOURCE_PCLK2) || ((__SOURCE__) == RCC_COMP2CLKSOURCE_LSI)   || \
                                           ((__SOURCE__) == RCC_COMP2CLKSOURCE_LSE))

#define IS_RCC_COMP3CLKSOURCE(__SOURCE__) (((__SOURCE__) == RCC_COMP3CLKSOURCE_PCLK2) || ((__SOURCE__) == RCC_COMP3CLKSOURCE_LSI)   || \
                                           ((__SOURCE__) == RCC_COMP3CLKSOURCE_LSE))

#define IS_RCC_COMP4CLKSOURCE(__SOURCE__) (((__SOURCE__) == RCC_COMP4CLKSOURCE_PCLK2) || ((__SOURCE__) == RCC_COMP4CLKSOURCE_LSI)   || \
                                           ((__SOURCE__) == RCC_COMP4CLKSOURCE_LSE))

#define IS_RCC_PERIPHCLOCK(PERIPHCLOCK)  ((PERIPHCLOCK) <= RCC_PERIPHCLK_MASK)

/**
  * @}
  */

/* Exported types ------------------------------------------------------------*/

/** @defgroup RCCEx_Exported_Types RCCEx Exported Types
  * @{
  */

/**
  * @brief  RCC extended clocks structure definition
  */
typedef struct
{
  uint32_t PeriphClockSelection;            /*!< The Extended Clock to be configured.
                                            This parameter can be a value of @ref RCCEx_Periph_Clock_Selection */

  uint32_t RtcClockSelection;              /*!< specifies the RTC clock source.
                                             This parameter can be a value of @ref RCC_RTC_Clock_Source */
  
  uint32_t UsartClockSelection;           /*!< Specifies USART1 clock source.
                                            This parameter can be a value of @ref RCCEx_USART_Clock_Source */
  
  uint32_t LpuartClockSelection;          /*!< Specifies LPUART1 clock source.
                                            This parameter can be a value of @ref RCCEx_LPUART1_Clock_Source */
  
  uint32_t Comp1ClockSelection;            /*!< Specifies COMP1 clock source.
                                            This parameter can be a value of @ref RCCEx_COMP1_Clock_Source */
  
  uint32_t Comp2ClockSelection;            /*!< Specifies COMP2 clock source.
                                            This parameter can be a value of @ref RCCEx_COMP2_Clock_Source */
  
  uint32_t Comp3ClockSelection;            /*!< Specifies COMP3 clock source.
                                            This parameter can be a value of @ref RCCEx_COMP3_Clock_Source */
  
  uint32_t Comp4ClockSelection;            /*!< Specifies COMP4 clock source.
                                            This parameter can be a value of @ref RCCEx_COMP4_Clock_Source */
  
  uint32_t PvdFilterClockSelection;        /*!< PVD filter clock source
                                            This parameter can be a value of @ref RCCEx_PVD_Filter_Clock_Source */
  
  uint32_t FdcanClockSelection;              /*!< CAN clock source
                                            This parameter can be a value of @ref RCCEx_FDCAN_Clock_Source */

  uint32_t FdcanPLLDiv;                     /*!< CAN PLL clock division factor
                                            This parameter must be a number between 1 and 16. */

  uint32_t AdcClockSelection;              /*!< ADC clock source
                                            This parameter can be a value of @ref RCCEx_ADC_Clock_Source */
  
  uint32_t AdcPLLDiv;                     /*!< ADC PLL clock division factor
                                            This parameter must be a number between 1 and 3. */
  
  uint32_t LptimClockSelection;           /*!< Specifies LPTIM1 clock source.
                                            This parameter can be a value of @ref RCCEx_LPTIM1_Clock_Source */
} RCC_PeriphCLKInitTypeDef;

/**
  * @}
  */

/* Exported constants --------------------------------------------------------*/
/** @defgroup RCCEx_Exported_Constants RCCEx Exported Constants
  * @{
  */

/** @defgroup RCCEx_Periph_Clock_Selection Periph Clock Selection
  * @{
  */
#define RCC_PERIPHCLK_RTC           0x00000001U
#define RCC_PERIPHCLK_USART         0x00000002U
#define RCC_PERIPHCLK_LPUART        0x00000004U
#define RCC_PERIPHCLK_COMP1         0x00000008U
#define RCC_PERIPHCLK_COMP2         0x00000010U
#define RCC_PERIPHCLK_COMP3         0x00000020U
#define RCC_PERIPHCLK_COMP4         0x00000040U
#define RCC_PERIPHCLK_PVD           0x00000080U
#define RCC_PERIPHCLK_FDCAN         0x00000100U
#define RCC_PERIPHCLK_ADC           0x00000200U
#define RCC_PERIPHCLK_LPTIM         0x00000400U

#define RCC_PERIPHCLK_MASK          0x000007FFU
/**
  * @}
  */

/** @defgroup RCCEx_ADC_Clock_Source ADC Clock Source
  * @{
  */
#define RCC_ADCCLKSOURCE_SYSCLK        0x00000000U
#define RCC_ADCCLKSOURCE_PLL           RCC_CCIPR2_ADC12SEL_0
#define RCC_ADCCLKSOURCE_HSI           RCC_CCIPR2_ADC12SEL_1
#define RCC_ADCCLKSOURCE_HSE           (RCC_CCIPR2_ADC12SEL_1 | RCC_CCIPR2_ADC12SEL_0)
/**
  * @}
  */

/** @defgroup RCCEx_FDCAN_Clock_Source CAN Clock Source
  * @{
  */
#define RCC_FDCANCLKSOURCE_PLL           0x00000000U
#define RCC_FDCANCLKSOURCE_PCLK1         RCC_CCIPR2_FDCANCKSEL_0
#define RCC_FDCANCLKSOURCE_HSE           RCC_CCIPR2_FDCANCKSEL_1
/**
  * @}
  */

/** @defgroup RCCEx_PVD_Filter_Clock_Source PVD Filter Clock Source
  * @{
  */
#define RCC_PVDFILTERCLK_LSI            0x00000000
#define RCC_PVDFILTERCLK_LSE            RCC_CCIPR1_PVDSEL_0
#define RCC_PVDFILTERCLK_PCLK1          RCC_CCIPR1_PVDSEL_1
/**
  * @}
  */

/** @defgroup RCCEx_USART_Clock_Source USART1 Clock Source
  * @{
  */
#define RCC_USARTCLKSOURCE_PCLK2      0x00000000U
#define RCC_USARTCLKSOURCE_SYSCLK     RCC_CCIPR1_USARTSEL_0
#define RCC_USARTCLKSOURCE_HSI        RCC_CCIPR1_USARTSEL_1
#define RCC_USARTCLKSOURCE_LSE        (RCC_CCIPR1_USARTSEL_0 | RCC_CCIPR1_USARTSEL_1)
/**
  * @}
  */

/** @defgroup RCCEx_LPUART1_Clock_Source LPUART1 Clock Source
  * @{
  */
#define RCC_LPUARTCLKSOURCE_PCLK1     0x00000000U
#define RCC_LPUARTCLKSOURCE_SYSCLK    RCC_CCIPR1_LPUARTSEL_0
#define RCC_LPUARTCLKSOURCE_HSI       RCC_CCIPR1_LPUARTSEL_1
#define RCC_LPUARTCLKSOURCE_LSE       (RCC_CCIPR1_LPUARTSEL_0 | RCC_CCIPR1_LPUARTSEL_1)
/**
  * @}
  */

/** @defgroup RCCEx_LPTIM1_Clock_Source LPTIM1 Clock Source
  * @{
  */
#define RCC_LPTIMCLKSOURCE_PCLK1      0x00000000U
#define RCC_LPTIMCLKSOURCE_LSI        RCC_CCIPR2_LPTIMSEL_0
#define RCC_LPTIMCLKSOURCE_HSI        RCC_CCIPR2_LPTIMSEL_1
#define RCC_LPTIMCLKSOURCE_LSE        (RCC_CCIPR2_LPTIMSEL_1 | RCC_CCIPR2_LPTIMSEL_0)
/**
  * @}
  */

/** @defgroup RCCEx_COMP1_Clock_Source COMP1 Clock Source
  * @{
  */
#define RCC_COMP1CLKSOURCE_PCLK2      0x00000000U
#define RCC_COMP1CLKSOURCE_LSI        RCC_CCIPR1_COMP1SEL_0
#define RCC_COMP1CLKSOURCE_LSE        RCC_CCIPR1_COMP1SEL_1
/**
  * @}
  */

/** @defgroup RCCEx_COMP2_Clock_Source COMP2 Clock Source
  * @{
  */
#define RCC_COMP2CLKSOURCE_PCLK2      0x00000000U
#define RCC_COMP2CLKSOURCE_LSI        RCC_CCIPR1_COMP2SEL_0
#define RCC_COMP2CLKSOURCE_LSE        RCC_CCIPR1_COMP2SEL_1
/**
  * @}
  */

/** @defgroup RCCEx_COMP3_Clock_Source COMP3 Clock Source
  * @{
  */
#define RCC_COMP3CLKSOURCE_PCLK2      0x00000000U
#define RCC_COMP3CLKSOURCE_LSI        RCC_CCIPR1_COMP3SEL_0
#define RCC_COMP3CLKSOURCE_LSE        RCC_CCIPR1_COMP3SEL_1
/**
  * @}
  */

/** @defgroup RCCEx_COMP4_Clock_Source COMP4 Clock Source
  * @{
  */
#define RCC_COMP4CLKSOURCE_PCLK2      0x00000000U
#define RCC_COMP4CLKSOURCE_LSI        RCC_CCIPR1_COMP4SEL_0
#define RCC_COMP4CLKSOURCE_LSE        RCC_CCIPR1_COMP4SEL_1
/**
  * @}
  */
  
/** @defgroup RCCEx_TIM_PCLK_Frequency_Control TIM PCLK Frequency Control
  * @{
  */
  
#define RCC_TIMPCLK_MUL2       0x00000000U               /*!< TIMER PCLK is twice the system PCLK, but the frequency will not exceed HCLK */
#define RCC_TIMPCLK_MUL1       RCC_CCIPR1_TIMCLKCTRL     /*!< TIMER PCLK is the system PCLK */
/**
  * @}
  */

/**
  * @}
  */

/** @defgroup RCCEx_Peripheral_Configuration Peripheral Configuration
  * @brief  Macros to configure clock source of different peripherals.
  * @{
  */

/** @brief  Macro to configure the ADCx clock (x=1 to 2 depending on devices).
  * @param  __ADCCLKSOURCE__ specifies the ADC clock source.
  *          This parameter can be one of the following values:
  *            @arg @ref RCC_ADCCLKSOURCE_SYSCLK  System Clock selected as ADC clock
  *            @arg @ref RCC_ADCCLKSOURCE_PLL     PLL selected as ADC clock
  *            @arg @ref RCC_ADCCLKSOURCE_HSI     HSI selected as ADC clock
  *            @arg @ref RCC_ADCCLKSOURCE_HSE     HSE selected as ADC clock
  */
#define __HAL_RCC_ADC_CONFIG(__ADCCLKSOURCE__) \
                  MODIFY_REG(RCC->CCIPR2, RCC_CCIPR2_ADC12SEL, (uint32_t)(__ADCCLKSOURCE__))

/** @brief  Macro to get the ADC clock (ADCxCLK, x=1 to 2 depending on devices).
  * @retval The clock source can be one of the following values:
  *            @arg @ref RCC_ADCCLKSOURCE_SYSCLK  System Clock selected as ADC clock
  *            @arg @ref RCC_ADCCLKSOURCE_PLL     PLL selected as ADC clock
  *            @arg @ref RCC_ADCCLKSOURCE_HSI     HSI selected as ADC clock
  *            @arg @ref RCC_ADCCLKSOURCE_HSE     HSE selected as ADC clock
  */
#define __HAL_RCC_GET_ADC_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR2, RCC_CCIPR2_ADC12SEL)))

/** @brief  Macro to configure the ADC PLL clock division factor.
  * @param  __ADC_PLLDIV__ specifies the ADC PLL clock division factor.
  *         This parameter must be a number between 1 and 3.
  * @retval None
  */
#define __HAL_RCC_ADC_PLLDIV_CONFIG(__ADC_PLLDIV__) \
                  MODIFY_REG(RCC->CCIPR3, RCC_CCIPR3_PLL_ADC_DIV, ((__ADC_PLLDIV__) - 1U) << RCC_CCIPR3_PLL_ADC_DIV_Pos)

/** @brief  Macro to get the ADC PLL clock division factor.
  * @retval The ADC PLL clock division factor can be a number between 1 and 3.
  */
#define __HAL_RCC_GET_ADC_PLLDIV() ((READ_BIT(RCC->CCIPR3, RCC_CCIPR3_PLL_ADC_DIV) >> RCC_CCIPR3_PLL_ADC_DIV_Pos) + 1U)

/** @brief  Macro to enable the ADC1 kernal clock.
  * @retval None
  */
#define __HAL_RCC_ADC1_KERNALCLK_ENABLE() SET_BIT(RCC->CCIPR2, RCC_CCIPR2_ADC1KEN)

/** @brief  Macro to disable the ADC1 kernal clock.
  * @retval None
  */
#define __HAL_RCC_ADC1_KERNALCLK_DISABLE() CLEAR_BIT(RCC->CCIPR2, RCC_CCIPR2_ADC1KEN)

/** @brief  Macro to enable the ADC2 kernal clock.
  * @retval None
  */
#define __HAL_RCC_ADC2_KERNALCLK_ENABLE() SET_BIT(RCC->CCIPR2, RCC_CCIPR2_ADC2KEN)

/** @brief  Macro to disable the ADC2 kernal clock.
  * @retval None
  */
#define __HAL_RCC_ADC2_KERNALCLK_DISABLE() CLEAR_BIT(RCC->CCIPR2, RCC_CCIPR2_ADC2KEN)

/** @brief  Macro to configure the CAN clock.
  * @param  __FDCANCLKSOURCE__ specifies the CAN clock source.
  *          This parameter can be one of the following values:
  *            @arg @ref RCC_FDCANCLKSOURCE_PLL   PLL selected as CAN clock
  *            @arg @ref RCC_FDCANCLKSOURCE_PCLK1 PCLK1 selected as CAN clock
  *            @arg @ref RCC_FDCANCLKSOURCE_HSE   HSE selected as CAN clock
*/
#define __HAL_RCC_FDCAN_CONFIG(__FDCANCLKSOURCE__) \
                  MODIFY_REG(RCC->CCIPR2, RCC_CCIPR2_FDCANCKSEL, (uint32_t)(__FDCANCLKSOURCE__))

/** @brief  Macro to get the CAN clock.
  * @retval The clock source can be one of the following values:
  *            @arg @ref RCC_FDCANCLKSOURCE_PLL   PLL selected as CAN clock
  *            @arg @ref RCC_FDCANCLKSOURCE_PCLK1 PCLK1 selected as CAN clock
  *            @arg @ref RCC_FDCANCLKSOURCE_HSE   HSE selected as CAN clock
  */
#define __HAL_RCC_GET_FDCAN_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR2, RCC_CCIPR2_FDCANCKSEL)))

/** @brief  Macro to configure the CAN PLL clock division factor.
  * @param  __FDCAN_PLLDIV__ specifies the CAN PLL clock division factor.
  *         This parameter must be a number between 1 and 16.
  * @retval None
  */
#define __HAL_RCC_FDCAN_PLLDIV_CONFIG(__FDCAN_PLLDIV__) \
                  MODIFY_REG(RCC->CCIPR3, RCC_CCIPR3_PLL_FDCAN_DIV, ((__FDCAN_PLLDIV__) - 1U) << RCC_CCIPR3_PLL_FDCAN_DIV_Pos)

/** @brief  Macro to get the CAN PLL clock division factor.
  * @retval The CAN PLL clock division factor can be a number between 1 and 16.
  */
#define __HAL_RCC_GET_FDCAN_PLLDIV() ((READ_BIT(RCC->CCIPR3, RCC_CCIPR3_PLL_FDCAN_DIV) >> RCC_CCIPR3_PLL_FDCAN_DIV_Pos) + 1U)

/** @brief  Macro to configure the PVD filter clock.
  * @param  __PVDFILTERCLK__ specifies the SRAM2 clock source.
  *          This parameter can be one of the following values:
  *            @arg @ref RCC_PVDFILTERCLK_LSI   LSI oscillator clock used as PVD filter clock
  *            @arg @ref RCC_PVDFILTERCLK_LSE   LSE oscillator clock used as PVD filter clock
  *            @arg @ref RCC_PVDFILTERCLK_PCLK1 PCLK used as PVD filter clock
  */
#define __HAL_RCC_PVD_CONFIG(__PVDFILTERCLK__) \
                  MODIFY_REG(RCC->CCIPR1, RCC_CCIPR1_PVDSEL, (uint32_t)(__PVDFILTERCLK__))

/** @brief  Macro to get the PVD filter clock.
  * @retval The clock source can be one of the following values:
  *            @arg @ref RCC_PVDFILTERCLK_LSI   LSI oscillator clock used as PVD filter clock
  *            @arg @ref RCC_PVDFILTERCLK_LSE   LSE oscillator clock used as PVD filter clock
  *            @arg @ref RCC_PVDFILTERCLK_PCLK1 PCLK used as PVD filter clock
  */
#define __HAL_RCC_GET_PVD_FILTER_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR1, RCC_CCIPR1_PVDSEL)))

/** @brief  Macro to configure the USART1 clock (USART1CLK).
  *
  * @param  __USART_CLKSOURCE__ specifies the USART1 clock source.
  *          This parameter can be one of the following values:
  *            @arg @ref RCC_USARTCLKSOURCE_PCLK2   PCLK2 selected as USART1 clock
  *            @arg @ref RCC_USARTCLKSOURCE_HSI     HSI selected as USART1 clock
  *            @arg @ref RCC_USARTCLKSOURCE_SYSCLK  System Clock selected as USART1 clock
  *            @arg @ref RCC_USARTCLKSOURCE_LSE     LSE selected as USART1 clock
  * @retval None
  */
#define __HAL_RCC_USART_CONFIG(__USART_CLKSOURCE__) \
                  MODIFY_REG(RCC->CCIPR1, RCC_CCIPR1_USARTSEL, (__USART_CLKSOURCE__))

/** @brief  Macro to get the USART1 clock source.
  * @retval The clock source can be one of the following values:
  *            @arg @ref RCC_USARTCLKSOURCE_PCLK2   PCLK2 selected as USART1 clock
  *            @arg @ref RCC_USARTCLKSOURCE_HSI     HSI selected as USART1 clock
  *            @arg @ref RCC_USARTCLKSOURCE_SYSCLK  System Clock selected as USART1 clock
  *            @arg @ref RCC_USARTCLKSOURCE_LSE     LSE selected as USART1 clock
  */
#define __HAL_RCC_GET_USART_SOURCE() (READ_BIT(RCC->CCIPR1, RCC_CCIPR1_USARTSEL))

/** @brief  Macro to configure the LPUART1 clock (LPUART1CLK).
  *
  * @param  __LPUART1_CLKSOURCE__ specifies the LPUART1 clock source.
  *          This parameter can be one of the following values:
  *            @arg @ref RCC_LPUARTCLKSOURCE_PCLK1   PCLK1 selected as LPUART1 clock
  *            @arg @ref RCC_LPUARTCLKSOURCE_HSI     HSI selected as LPUART1 clock
  *            @arg @ref RCC_LPUARTCLKSOURCE_SYSCLK  System Clock selected as LPUART1 clock
  *            @arg @ref RCC_LPUARTCLKSOURCE_LSE     LSE selected as LPUART1 clock
  * @retval None
  */
#define __HAL_RCC_LPUART_CONFIG(__LPUART1_CLKSOURCE__) \
                  MODIFY_REG(RCC->CCIPR1, RCC_CCIPR1_LPUARTSEL, (__LPUART1_CLKSOURCE__))

/** @brief  Macro to get the LPUART1 clock source.
  * @retval The clock source can be one of the following values:
  *            @arg @ref RCC_LPUARTCLKSOURCE_PCLK1   PCLK1 selected as LPUART1 clock
  *            @arg @ref RCC_LPUARTCLKSOURCE_HSI     HSI selected as LPUART1 clock
  *            @arg @ref RCC_LPUARTCLKSOURCE_SYSCLK  System Clock selected as LPUART1 clock
  *            @arg @ref RCC_LPUARTCLKSOURCE_LSE     LSE selected as LPUART1 clock
  */
#define __HAL_RCC_GET_LPUART_SOURCE() (READ_BIT(RCC->CCIPR1, RCC_CCIPR1_LPUARTSEL))

/** @brief  Macro to configure the LPTIM1 clock (LPTIM1CLK).
  *
  * @param  __LPTIM1_CLKSOURCE__ specifies the LPTIM1 clock source.
  *          This parameter can be one of the following values:
  *            @arg @ref RCC_LPTIMCLKSOURCE_PCLK1  PCLK1 selected as LPTIM1 clock
  *            @arg @ref RCC_LPTIMCLKSOURCE_LSI    LSI selected as LPTIM1 clock
  *            @arg @ref RCC_LPTIMCLKSOURCE_HSI    HSI selected as LPTIM1 clock
  *            @arg @ref RCC_LPTIMCLKSOURCE_LSE    LSE selected as LPTIM1 clock
  * @retval None
  */
#define __HAL_RCC_LPTIM_CONFIG(__LPTIM1_CLKSOURCE__) \
                  MODIFY_REG(RCC->CCIPR2, RCC_CCIPR2_LPTIMSEL, (__LPTIM1_CLKSOURCE__))

/** @brief  Macro to get the LPTIM1 clock source.
  * @retval The clock source can be one of the following values:
  *            @arg @ref RCC_LPTIMCLKSOURCE_PCLK1  PCLK1 selected as LPTIM1 clock
  *            @arg @ref RCC_LPTIMCLKSOURCE_LSI    LSI selected as LPTIM1 clock
  *            @arg @ref RCC_LPTIMCLKSOURCE_HSI    HSI selected as LPTIM1 clock
  *            @arg @ref RCC_LPTIMCLKSOURCE_LSE    LSE selected as LPTIM1 clock
  */
#define __HAL_RCC_GET_LPTIM_SOURCE() (READ_BIT(RCC->CCIPR2, RCC_CCIPR2_LPTIMSEL))

/** @brief  Macro to configure the COMP1 clock (COMP1CLK).
  *
  * @param  __COMP1_CLKSOURCE__ specifies the COMP1 clock source.
  *          This parameter can be one of the following values:
  *            @arg @ref RCC_COMP1CLKSOURCE_PCLK2  PCLK selected as COMP1 clock
  *            @arg @ref RCC_COMP1CLKSOURCE_LSI    HSI selected as COMP1 clock
  *            @arg @ref RCC_COMP1CLKSOURCE_LSE    LSE selected as COMP1 clock
  * @retval None
  */
#define __HAL_RCC_COMP1_CONFIG(__COMP1_CLKSOURCE__) \
                  MODIFY_REG(RCC->CCIPR1, RCC_CCIPR1_COMP1SEL, (__COMP1_CLKSOURCE__))

/** @brief  Macro to get the COMP1 clock source.
  * @retval The clock source can be one of the following values:
  *            @arg @ref RCC_COMP1CLKSOURCE_PCLK2  PCLK selected as COMP1 clock
  *            @arg @ref RCC_COMP1CLKSOURCE_LSI    HSI selected as COMP1 clock
  *            @arg @ref RCC_COMP1CLKSOURCE_LSE    LSE selected as COMP1 clock
  */
#define __HAL_RCC_GET_COMP1_SOURCE() (READ_BIT(RCC->CCIPR1, RCC_CCIPR1_COMP1SEL))

/** @brief  Macro to configure the COMP1 clock (COMP1CLK).
  *
  * @param  __COMP2_CLKSOURCE__ specifies the COMP2 clock source.
  *          This parameter can be one of the following values:
  *            @arg @ref RCC_COMP2CLKSOURCE_PCLK2  PCLK selected as COMP2 clock
  *            @arg @ref RCC_COMP2CLKSOURCE_LSI    HSI selected as COMP2 clock
  *            @arg @ref RCC_COMP2CLKSOURCE_LSE    LSE selected as COMP2 clock
  * @retval None
  */
#define __HAL_RCC_COMP2_CONFIG(__COMP2_CLKSOURCE__) \
                  MODIFY_REG(RCC->CCIPR1, RCC_CCIPR1_COMP2SEL, (__COMP2_CLKSOURCE__))

/** @brief  Macro to get the COMP2 clock source.
  * @retval The clock source can be one of the following values:
  *            @arg @ref RCC_COMP2CLKSOURCE_PCLK2  PCLK selected as COMP2 clock
  *            @arg @ref RCC_COMP2CLKSOURCE_LSI    HSI selected as COMP2 clock
  *            @arg @ref RCC_COMP2CLKSOURCE_LSE    LSE selected as COMP2 clock
  */
#define __HAL_RCC_GET_COMP2_SOURCE() (READ_BIT(RCC->CCIPR1, RCC_CCIPR1_COMP2SEL))

/** @brief  Macro to configure the COMP3 clock (COMP3CLK).
  *
  * @param  __COMP3_CLKSOURCE__ specifies the COMP3 clock source.
  *          This parameter can be one of the following values:
  *            @arg @ref RCC_COMP3CLKSOURCE_PCLK2  PCLK selected as COMP3 clock
  *            @arg @ref RCC_COMP3CLKSOURCE_LSI    HSI selected as COMP3 clock
  *            @arg @ref RCC_COMP3CLKSOURCE_LSE    LSE selected as COMP3 clock
  * @retval None
  */
#define __HAL_RCC_COMP3_CONFIG(__COMP3_CLKSOURCE__) \
                  MODIFY_REG(RCC->CCIPR1, RCC_CCIPR1_COMP3SEL, (__COMP3_CLKSOURCE__))

/** @brief  Macro to get the COMP3 clock source.
  * @retval The clock source can be one of the following values:
  *            @arg @ref RCC_COMP3CLKSOURCE_PCLK2  PCLK selected as COMP3 clock
  *            @arg @ref RCC_COMP3CLKSOURCE_LSI    HSI selected as COMP3 clock
  *            @arg @ref RCC_COMP3CLKSOURCE_LSE    LSE selected as COMP3 clock
  */
#define __HAL_RCC_GET_COMP3_SOURCE() (READ_BIT(RCC->CCIPR1, RCC_CCIPR1_COMP3SEL))

/** @brief  Macro to configure the COMP4 clock (COMP4CLK).
  *
  * @param  __COMP4_CLKSOURCE__ specifies the COMP4 clock source.
  *          This parameter can be one of the following values:
  *            @arg @ref RCC_COMP4CLKSOURCE_PCLK2  PCLK selected as COMP4 clock
  *            @arg @ref RCC_COMP4CLKSOURCE_LSI    HSI selected as COMP4 clock
  *            @arg @ref RCC_COMP4CLKSOURCE_LSE    LSE selected as COMP4 clock
  * @retval None
  */
#define __HAL_RCC_COMP4_CONFIG(__COMP4_CLKSOURCE__) \
                  MODIFY_REG(RCC->CCIPR1, RCC_CCIPR1_COMP4SEL, (__COMP4_CLKSOURCE__))

/** @brief  Macro to get the COMP4 clock source.
  * @retval The clock source can be one of the following values:
  *            @arg @ref RCC_COMP4CLKSOURCE_PCLK2  PCLK selected as COMP4 clock
  *            @arg @ref RCC_COMP4CLKSOURCE_LSI    HSI selected as COMP4 clock
  *            @arg @ref RCC_COMP4CLKSOURCE_LSE    LSE selected as COMP4 clock
  */
#define __HAL_RCC_GET_COMP4_SOURCE() (READ_BIT(RCC->CCIPR1, RCC_CCIPR1_COMP4SEL))

/** @brief  Macro to configure the TIMER PCLK frequency control.
  * @param  __TIMPCLK_MUL__ TIMPCLK multiple frequency factor.
  *          This parameter can be one of the following values:
  *            @arg @ref RCC_TIMPCLK_MUL2 TIMER PCLK is twice the system PCLK, but the frequency will not exceed HCLK
  *            @arg @ref RCC_TIMPCLK_MUL1 TIMER PCLK is the system PCLK
  */
#define __HAL_RCC_TIMPCLK_CONFIG(__TIMPCLK_MUL__) \
                  MODIFY_REG(RCC->CCIPR1, RCC_CCIPR1_TIMCLKCTRL, (uint32_t)(__TIMPCLK_MUL__))

/** @brief  Macro to get the TIMPCLK multiple frequency factor.
  * @retval The multiple frequency factor can be one of the following values:
  *            @arg @ref RCC_TIMPCLK_MUL2 TIMER PCLK is twice the system PCLK, but the frequency will not exceed HCLK
  *            @arg @ref RCC_TIMPCLK_MUL1 TIMER PCLK is the system PCLK
  */
#define __HAL_RCC_GET_TIMPCLK_MUL() ((uint32_t)(READ_BIT(RCC->CCIPR1, RCC_CCIPR1_TIMCLKCTRL)))

/**
  * @brief    Macros to enable the time base synchronization of EPWM.
  * @retval None
  */
#define __HAL_RCC_EPWM_TIME_BASE_SYNC_ENABLE()     SET_BIT(RCC->CCIPR2, RCC_CCIPR2_EPWM_TBCLKSYNC)

/**
  * @brief    Macros to disable the time base synchronization of EPWM.
  * @retval None
  */
#define __HAL_RCC_EPWM_TIME_BASE_SYNC_DISABLE()    CLEAR_BIT(RCC->CCIPR2, RCC_CCIPR2_EPWM_TBCLKSYNC)
/**
  * @}
  */

/**
  * @}
  */

/* Exported functions --------------------------------------------------------*/
/** @addtogroup RCCEx_Exported_Functions
  * @{
  */

/** @addtogroup RCCEx_Exported_Functions_Group1
  * @{
  */

HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef  *PeriphClkInit);
void              HAL_RCCEx_GetPeriphCLKConfig(RCC_PeriphCLKInitTypeDef  *PeriphClkInit);
uint32_t          HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk);

/**
  * @}
  */

/**
  * @}
  */

/**
  * @}
  */

#ifdef __cplusplus
}
#endif

#endif /* __PY32F420_HAL_RCC_EX_H */


/************************ (C) COPYRIGHT Puya *****END OF FILE******************/

