/**
  ******************************************************************************
  * @file    py32f420_hal_rcc_ex.c
  * @author  MCU Application Team
  * @brief   Extended RCC HAL module driver.
  *          This file provides firmware functions to manage the following
  *          functionalities RCC extended peripheral:
  *           + Extended Peripheral Control functions
  *           + Extended Clock management functions
  *
  ******************************************************************************
  * @attention
  *
  * <h2><center>&copy; Copyright (c) 2023 Puya Semiconductor Co.
  * All rights reserved.</center></h2>
  *
  * This software component is licensed by Puya under BSD 3-Clause license,
  * the "License"; You may not use this file except in compliance with the
  * License. You may obtain a copy of the License at:
  *                        opensource.org/licenses/BSD-3-Clause
  *
  ******************************************************************************
  * @attention
  *
  * <h2><center>&copy; Copyright (c) 2016 STMicroelectronics.
  * All rights reserved.</center></h2>
  *
  * This software component is licensed by ST under BSD 3-Clause license,
  * the "License"; You may not use this file except in compliance with the
  * License. You may obtain a copy of the License at:
  *                        opensource.org/licenses/BSD-3-Clause
  *
  ******************************************************************************
  */

/* Includes ------------------------------------------------------------------*/
#include "py32f4xx_hal.h"

/** @addtogroup PY32F420_HAL_Driver
  * @{
  */

#ifdef HAL_RCC_MODULE_ENABLED

/** @defgroup RCCEx RCCEx
  * @brief RCC Extension HAL module driver.
  * @{
  */

/* Private typedef -----------------------------------------------------------*/
/* Private define ------------------------------------------------------------*/
/** @defgroup RCCEx_Private_Constants RCCEx Private Constants
  * @{
  */
/**
  * @}
  */

/* Private macro -------------------------------------------------------------*/
/** @defgroup RCCEx_Private_Macros RCCEx Private Macros
  * @{
  */
/**
  * @}
  */

/* Private variables ---------------------------------------------------------*/
/* Private function prototypes -----------------------------------------------*/
/** @defgroup RCC_Private_Functions RCC Private Functions
  * @{
  */
static uint32_t          RCCEx_GetPLLClockFreq(void);
/**
  * @}
  */
/* Private functions ---------------------------------------------------------*/

/** @defgroup RCCEx_Exported_Functions RCCEx Exported Functions
  * @{
  */

/** @defgroup RCCEx_Exported_Functions_Group1 Peripheral Control functions
  *  @brief  Extended Peripheral Control functions
  *
@verbatim
 ===============================================================================
                ##### Extended Peripheral Control functions  #####
 ===============================================================================
    [..]
    This subsection provides a set of functions allowing to control the RCC Clocks
    frequencies.
    [..]
    (@) Important note: Care must be taken when HAL_RCCEx_PeriphCLKConfig() is used to
        select the RTC clock source; in this case the Backup domain will be reset in
        order to modify the RTC Clock source, as consequence RTC registers (including
        the backup registers) are set to their reset values.

@endverbatim
  * @{
  */

/**
  * @brief  Initializes the RCC extended peripherals clocks according to the specified parameters in the
  *         RCC_PeriphCLKInitTypeDef.
  * @param  PeriphClkInit pointer to an RCC_PeriphCLKInitTypeDef structure that
  *         contains the configuration information for the Extended Peripherals clocks.
  *
  * @note   Care must be taken when HAL_RCCEx_PeriphCLKConfig() is used to select
  *         the RTC clock source; in this case the Backup domain will be reset in
  *         order to modify the RTC Clock source, as consequence RTC registers (including
  *         the backup registers) are set to their reset values.
  *
  * @retval HAL status
  */
HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef  *PeriphClkInit)
{
  uint32_t tickstart = 0U, temp_reg = 0U;

  /* Check the parameters */
  assert_param(IS_RCC_PERIPHCLOCK(PeriphClkInit->PeriphClockSelection));

  /*------------------------------- RTC Configuration ------------------------*/
  if ((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_RTC) == RCC_PERIPHCLK_RTC))
  {
    /* check for RTC Parameters used to output RTCCLK */
    assert_param(IS_RCC_RTCCLKSOURCE(PeriphClkInit->RtcClockSelection));

    FlagStatus       pwrclkchanged = RESET;

    /* As soon as function is called to change RTC clock source, activation of the
       power domain is done. */
    /* Requires to enable write access to Backup Domain of necessary */
    if (__HAL_RCC_PWR_IS_CLK_DISABLED())
    {
      __HAL_RCC_PWR_CLK_ENABLE();
      pwrclkchanged = SET;
    }

    if (HAL_IS_BIT_CLR(PWR->CR1, PWR_CR1_DBP))
    {
      /* Enable write access to Backup domain */
      SET_BIT(PWR->CR1, PWR_CR1_DBP);

      /* Wait for Backup domain Write protection disable */
      tickstart = HAL_GetTick();

      while (HAL_IS_BIT_CLR(PWR->CR1, PWR_CR1_DBP))
      {
        if ((HAL_GetTick() - tickstart) > RCC_DBP_TIMEOUT_VALUE)
        {
          return HAL_TIMEOUT;
        }
      }
    }

    /* Reset the Backup domain only if the RTC Clock source selection is modified from reset value */
    temp_reg = (RCC->BDCR & RCC_BDCR_RTCSEL);
    if ((temp_reg != 0x00000000U) && (temp_reg != (PeriphClkInit->RtcClockSelection & RCC_BDCR_RTCSEL)))
    {
      /* Store the content of BDCR register before the reset of Backup Domain */
      temp_reg = (RCC->BDCR & ~(RCC_BDCR_RTCSEL));
      /* RTC Clock selection can be changed only if the Backup Domain is reset */
      __HAL_RCC_BACKUPRESET_FORCE();
      __HAL_RCC_BACKUPRESET_RELEASE();
      /* Restore the Content of BDCR register */
      RCC->BDCR = temp_reg;

      /* Wait for LSERDY if LSE was enabled */
      if (HAL_IS_BIT_SET(temp_reg, RCC_BDCR_LSEON))
      {
        /* Get Start Tick */
        tickstart = HAL_GetTick();

        /* Wait till LSE is ready */
        while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET)
        {
          if ((HAL_GetTick() - tickstart) > RCC_LSE_TIMEOUT_VALUE)
          {
            return HAL_TIMEOUT;
          }
        }
      }
      /* Wait for LSIRDY if LSI was enabled */
      if (HAL_IS_BIT_SET(temp_reg, RCC_BDCR_LSION))
      {
        /* Get Start Tick */
        tickstart = HAL_GetTick();

        /* Wait till LSI is ready */
        while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) == RESET)
        {
          if ((HAL_GetTick() - tickstart) > LSI_TIMEOUT_VALUE)
          {
            return HAL_TIMEOUT;
          }
        }
      }
    }
    __HAL_RCC_RTC_CONFIG(PeriphClkInit->RtcClockSelection);

    /* Require to disable power clock if necessary */
    if (pwrclkchanged == SET)
    {
      __HAL_RCC_PWR_CLK_DISABLE();
    }
  }
  
  /*-------------------------- USART1 clock source configuration -------------------*/
  if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USART) == RCC_PERIPHCLK_USART)
  {
    /* Check the parameters */
    assert_param(IS_RCC_USARTCLKSOURCE(PeriphClkInit->UsartClockSelection));

    /* Configure the USART1 clock source */
    __HAL_RCC_USART_CONFIG(PeriphClkInit->UsartClockSelection);
  }

  /*-------------------------- LPUART1 clock source configuration ------------------*/
  if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_LPUART) == RCC_PERIPHCLK_LPUART)
  {
    /* Check the parameters */
    assert_param(IS_RCC_LPUARTCLKSOURCE(PeriphClkInit->LpuartClockSelection));

    /* Configure the LPUAR1 clock source */
    __HAL_RCC_LPUART_CONFIG(PeriphClkInit->LpuartClockSelection);
  }
  
  /*-------------------------- COMP1 clock source configuration ---------------------*/
  if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_COMP1) == RCC_PERIPHCLK_COMP1)
  {
    /* Check the parameters */
    assert_param(IS_RCC_COMP1CLKSOURCE(PeriphClkInit->Comp1ClockSelection));

    /* Configure the COMP1 clock source */
    __HAL_RCC_COMP1_CONFIG(PeriphClkInit->Comp1ClockSelection);
  }
  
  /*-------------------------- COMP2 clock source configuration ---------------------*/
  if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_COMP2) == RCC_PERIPHCLK_COMP2)
  {
    /* Check the parameters */
    assert_param(IS_RCC_COMP2CLKSOURCE(PeriphClkInit->Comp2ClockSelection));

    /* Configure the COMP2 clock source */
    __HAL_RCC_COMP2_CONFIG(PeriphClkInit->Comp2ClockSelection);
  }
  
  /*-------------------------- COMP3 clock source configuration ---------------------*/
  if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_COMP3) == RCC_PERIPHCLK_COMP3)
  {
    /* Check the parameters */
    assert_param(IS_RCC_COMP3CLKSOURCE(PeriphClkInit->Comp3ClockSelection));

    /* Configure the COMP3 clock source */
    __HAL_RCC_COMP3_CONFIG(PeriphClkInit->Comp3ClockSelection);
  }
  
  /*-------------------------- COMP4 clock source configuration ---------------------*/
  if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_COMP4) == RCC_PERIPHCLK_COMP4)
  {
    /* Check the parameters */
    assert_param(IS_RCC_COMP4CLKSOURCE(PeriphClkInit->Comp4ClockSelection));

    /* Configure the COMP4 clock source */
    __HAL_RCC_COMP4_CONFIG(PeriphClkInit->Comp4ClockSelection);
  }
  
  /*------------------------------ PVD filter  clock Configuration ----------*/
  if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_PVD) == RCC_PERIPHCLK_PVD)
  {
    /* Check the parameters */
    assert_param(IS_RCC_PVDFILTERCLK(PeriphClkInit->PvdFilterClockSelection));

    /* Configure the PVD filter clock */
    __HAL_RCC_PVD_CONFIG(PeriphClkInit->PvdFilterClockSelection);
  }
  
  /*------------------------------ CAN clock Configuration ------------------*/
  if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_FDCAN) == RCC_PERIPHCLK_FDCAN)
  {
    /* Check the parameters */
    assert_param(IS_RCC_FDCANCLKSOURCE(PeriphClkInit->FdcanClockSelection));

    /* Configure the CAN clock source */
    __HAL_RCC_FDCAN_CONFIG(PeriphClkInit->FdcanClockSelection);
    
    if (PeriphClkInit->FdcanClockSelection == RCC_FDCANCLKSOURCE_PLL)
    {
      __HAL_RCC_FDCAN_PLLDIV_CONFIG(PeriphClkInit->FdcanPLLDiv);
    }
  }
  
  /*------------------------------ ADC clock Configuration ------------------*/
  if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_ADC) == RCC_PERIPHCLK_ADC)
  {
    /* Check the parameters */
    assert_param(IS_RCC_ADCCLKSOURCE(PeriphClkInit->AdcClockSelection));

    /* Configure the ADC clock source */
    __HAL_RCC_ADC_CONFIG(PeriphClkInit->AdcClockSelection);
    
    if (PeriphClkInit->AdcClockSelection == RCC_ADCCLKSOURCE_PLL)
    {
      __HAL_RCC_ADC_PLLDIV_CONFIG(PeriphClkInit->AdcPLLDiv);
    }
  }
  
  /*-------------------------- LPTIM1 clock source configuration ---------------------*/
  if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_LPTIM) == RCC_PERIPHCLK_LPTIM)
  {
    /* Check the parameters */
    assert_param(IS_RCC_LPTIMCLKSOURCE(PeriphClkInit->LptimClockSelection));

    /* Configure the LPTIM1 clock source */
    __HAL_RCC_LPTIM_CONFIG(PeriphClkInit->LptimClockSelection);
  }
  
  return HAL_OK;
}

/**
  * @brief  Get the PeriphClkInit according to the internal
  * RCC configuration registers.
  * @param  PeriphClkInit pointer to an RCC_PeriphCLKInitTypeDef structure that
  *         returns the configuration information for the Extended Peripherals clocks(RTC, ADC... clocks).
  * @retval None
  */
void HAL_RCCEx_GetPeriphCLKConfig(RCC_PeriphCLKInitTypeDef  *PeriphClkInit)
{
  /* Get the RTC configuration -----------------------------------------------*/
  PeriphClkInit->PeriphClockSelection = RCC_PERIPHCLK_RTC;
  PeriphClkInit->RtcClockSelection = __HAL_RCC_GET_RTC_SOURCE();

  /* Get the USART1 clock configuration -----------------------------------------*/
  PeriphClkInit->PeriphClockSelection |= RCC_PERIPHCLK_USART;
  PeriphClkInit->UsartClockSelection = __HAL_RCC_GET_USART_SOURCE();
  
  /* Get the LPUART1 clock configuration -----------------------------------------*/
  PeriphClkInit->PeriphClockSelection |= RCC_PERIPHCLK_LPUART;
  PeriphClkInit->LpuartClockSelection = __HAL_RCC_GET_LPUART_SOURCE();

  /* Get the COMP1 clock configuration -----------------------------------------*/
  PeriphClkInit->PeriphClockSelection |= RCC_PERIPHCLK_COMP1;
  PeriphClkInit->Comp1ClockSelection = __HAL_RCC_GET_COMP1_SOURCE();
  
  /* Get the COMP2 clock configuration -----------------------------------------*/
  PeriphClkInit->PeriphClockSelection |= RCC_PERIPHCLK_COMP2;
  PeriphClkInit->Comp2ClockSelection = __HAL_RCC_GET_COMP2_SOURCE();
  
  /* Get the COMP3 clock configuration -----------------------------------------*/
  PeriphClkInit->PeriphClockSelection |= RCC_PERIPHCLK_COMP3;
  PeriphClkInit->Comp3ClockSelection = __HAL_RCC_GET_COMP3_SOURCE();
  
  /* Get the COMP4 clock configuration -----------------------------------------*/
  PeriphClkInit->PeriphClockSelection |= RCC_PERIPHCLK_COMP4;
  PeriphClkInit->Comp4ClockSelection = __HAL_RCC_GET_COMP4_SOURCE();
  
  /* Get the PVD filter clock configuration -----------------------------------------*/
  PeriphClkInit->PeriphClockSelection |= RCC_PERIPHCLK_PVD;
  PeriphClkInit->PvdFilterClockSelection = __HAL_RCC_GET_PVD_FILTER_SOURCE();
  
  /* Get the CAN clock configuration -----------------------------------------*/
  PeriphClkInit->PeriphClockSelection |= RCC_PERIPHCLK_FDCAN;
  PeriphClkInit->FdcanClockSelection = __HAL_RCC_GET_FDCAN_SOURCE();
  PeriphClkInit->FdcanPLLDiv = __HAL_RCC_GET_FDCAN_PLLDIV();

  /* Get the ADC clock configuration -----------------------------------------*/
  PeriphClkInit->PeriphClockSelection |= RCC_PERIPHCLK_ADC;
  PeriphClkInit->AdcClockSelection = __HAL_RCC_GET_ADC_SOURCE();
  PeriphClkInit->AdcPLLDiv = __HAL_RCC_GET_ADC_PLLDIV();
  
  /* Get the LPTIM1 clock configuration -----------------------------------------*/
  PeriphClkInit->PeriphClockSelection |= RCC_PERIPHCLK_LPTIM;
  PeriphClkInit->LptimClockSelection = __HAL_RCC_GET_LPTIM_SOURCE();
}

/**
  * @brief  Returns the peripheral clock frequency
  * @note   Returns 0 if peripheral clock is unknown
  * @param  PeriphClk Peripheral clock identifier
  *         This parameter can be one of the following values:
  *            @arg @ref RCC_PERIPHCLK_RTC      RTC peripheral clock
  *            @arg @ref RCC_PERIPHCLK_USART    USART1 peripheral clock
  *            @arg @ref RCC_PERIPHCLK_LPUART   LPUART1 peripheral clock
  *            @arg @ref RCC_PERIPHCLK_COMP1    COMP1 peripheral clock
  *            @arg @ref RCC_PERIPHCLK_COMP2    COMP2 peripheral clock
  *            @arg @ref RCC_PERIPHCLK_COMP3    COMP3 peripheral clock
  *            @arg @ref RCC_PERIPHCLK_COMP4    COMP4 peripheral clock
  *            @arg @ref RCC_PERIPHCLK_PVD      PVD peripheral clock
  *            @arg @ref RCC_PERIPHCLK_FDCAN    CAN peripheral clock
  *            @arg @ref RCC_PERIPHCLK_ADC      ADC peripheral clock
  *            @arg @ref RCC_PERIPHCLK_LPTIM    LPTIM peripheral clock
  * @retval Frequency in Hz (0: means that no available frequency for the peripheral)
  */
uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk)
{
  uint32_t temp_reg = 0U, srcclk = 0U, hsiIndex = 0U, frequency = 0U;
  
  const uint32_t hsiValue[4] = {8000000,16000000,24000000,48000000};
  
  /* Check the parameters */
  assert_param(IS_RCC_PERIPHCLOCK(PeriphClk));

  switch (PeriphClk)
  {
    case RCC_PERIPHCLK_RTC:
    {
      /* Get RCC BDCR configuration ------------------------------------------------------*/
      temp_reg = RCC->BDCR;

      /* Check if LSE is ready if RTC clock selection is LSE */
      if (((temp_reg & RCC_BDCR_RTCSEL) == RCC_RTCCLKSOURCE_LSE) && (HAL_IS_BIT_SET(temp_reg, RCC_BDCR_LSERDY)))
      {
        frequency = LSE_VALUE;
      }
      /* Check if LSI is ready if RTC clock selection is LSI */
      else if (((temp_reg & RCC_BDCR_RTCSEL) == RCC_RTCCLKSOURCE_LSI) && (HAL_IS_BIT_SET(temp_reg, RCC_BDCR_LSIRDY)))
      {
        frequency = LSI_VALUE;
      }
      else if ((((RCC->CCIPR2 & RCC_CCIPR2_RTC_HSEDIV_SEL) | (temp_reg & RCC_BDCR_RTCSEL)) == RCC_RTCCLKSOURCE_HSE_DIV32) && (HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSERDY)))
      {
        frequency = HSE_VALUE / 32U;
      }
      else if ((((RCC->CCIPR2 & RCC_CCIPR2_RTC_HSEDIV_SEL) | (temp_reg & RCC_BDCR_RTCSEL)) == RCC_RTCCLKSOURCE_HSE_DIV128) && (HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSERDY)))
      {
        frequency = HSE_VALUE / 128U;
      }
      else if ((((RCC->CCIPR2 & RCC_CCIPR2_RTC_HSEDIV_SEL) | (temp_reg & RCC_BDCR_RTCSEL)) == RCC_RTCCLKSOURCE_HSE_DIV8) && (HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSERDY)))
      {
        frequency = HSE_VALUE / 8U;
      }
      /* Clock not enabled for RTC*/
      else
      {
        /* nothing to do: frequency already initialized to 0U */
      }
      break;
    }
    
    case RCC_PERIPHCLK_USART:
    {
      /* Get the current USART1 source */
      srcclk = __HAL_RCC_GET_USART_SOURCE();

      if(srcclk == RCC_USARTCLKSOURCE_PCLK2)
      {
        frequency = HAL_RCC_GetPCLK2Freq();
      }
      else if(srcclk == RCC_USARTCLKSOURCE_SYSCLK)
      {
        frequency = HAL_RCC_GetSysClockFreq();
      }
      else if((HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY)) && (srcclk == RCC_USARTCLKSOURCE_HSI) )
      {
        hsiIndex = (RCC->ICSCR & RCC_ICSCR_HSI_FS_Msk) >> RCC_ICSCR_HSI_FS_Pos;
        frequency = hsiValue[hsiIndex];
      }
      else if((HAL_IS_BIT_SET(RCC->BDCR, RCC_BDCR_LSERDY)) && (srcclk == RCC_USARTCLKSOURCE_LSE))
      {
        frequency = LSE_VALUE;
      }
      /* Clock not enabled for USART1 */
      else
      {
        /* nothing to do: frequency already initialized to 0 */
      }
      break;
    }
    
    case RCC_PERIPHCLK_LPUART:
    {
      /* Get the current LPUART1 source */
      srcclk = __HAL_RCC_GET_LPUART_SOURCE();

      if(srcclk == RCC_LPUARTCLKSOURCE_PCLK1)
      {
        frequency = HAL_RCC_GetPCLK1Freq();
      }
      else if(srcclk == RCC_LPUARTCLKSOURCE_SYSCLK)
      {
        frequency = HAL_RCC_GetSysClockFreq();
      }
      else if((HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY)) && (srcclk == RCC_LPUARTCLKSOURCE_HSI))
      {
        hsiIndex = (RCC->ICSCR & RCC_ICSCR_HSI_FS_Msk) >> RCC_ICSCR_HSI_FS_Pos;
        frequency = hsiValue[hsiIndex];
      }
      else if((HAL_IS_BIT_SET(RCC->BDCR, RCC_BDCR_LSERDY)) && (srcclk == RCC_LPUARTCLKSOURCE_LSE))
      {
        frequency = LSE_VALUE;
      }
      /* Clock not enabled for LPUART1 */
      else
      {
        /* nothing to do: frequency already initialized to 0 */
      }
      break;
    }
    
    case RCC_PERIPHCLK_COMP1:
    {
      /* Get the current COMP1 source */
      srcclk = __HAL_RCC_GET_COMP1_SOURCE();

      if(srcclk == RCC_COMP1CLKSOURCE_PCLK2)
      {
        frequency = HAL_RCC_GetPCLK2Freq();
      }
      else if((HAL_IS_BIT_SET(RCC->BDCR, RCC_BDCR_LSIRDY)) && (srcclk == RCC_COMP1CLKSOURCE_LSI))
      {
        frequency = LSI_VALUE;
      }
      else if((HAL_IS_BIT_SET(RCC->BDCR, RCC_BDCR_LSERDY)) && (srcclk == RCC_COMP1CLKSOURCE_LSE))
      {
        frequency = LSE_VALUE;
      }
      /* Clock not enabled for COMP1 */
      else
      {
        /* nothing to do: frequency already initialized to 0 */
      }
      break;
    }
    
    case RCC_PERIPHCLK_COMP2:
    {
      /* Get the current COMP2 source */
      srcclk = __HAL_RCC_GET_COMP2_SOURCE();

      if(srcclk == RCC_COMP2CLKSOURCE_PCLK2)
      {
        frequency = HAL_RCC_GetPCLK2Freq();
      }
      else if((HAL_IS_BIT_SET(RCC->BDCR, RCC_BDCR_LSIRDY)) && (srcclk == RCC_COMP2CLKSOURCE_LSI))
      {
        frequency = LSI_VALUE;
      }
      else if((HAL_IS_BIT_SET(RCC->BDCR, RCC_BDCR_LSERDY)) && (srcclk == RCC_COMP2CLKSOURCE_LSE))
      {
        frequency = LSE_VALUE;
      }
      /* Clock not enabled for COMP2 */
      else
      {
        /* nothing to do: frequency already initialized to 0 */
      }
      break;
    }
    
    case RCC_PERIPHCLK_COMP3:
    {
      /* Get the current COMP3 source */
      srcclk = __HAL_RCC_GET_COMP3_SOURCE();

      if(srcclk == RCC_COMP3CLKSOURCE_PCLK2)
      {
        frequency = HAL_RCC_GetPCLK2Freq();
      }
      else if((HAL_IS_BIT_SET(RCC->BDCR, RCC_BDCR_LSIRDY)) && (srcclk == RCC_COMP3CLKSOURCE_LSI))
      {
        frequency = LSI_VALUE;
      }
      else if((HAL_IS_BIT_SET(RCC->BDCR, RCC_BDCR_LSERDY)) && (srcclk == RCC_COMP3CLKSOURCE_LSE))
      {
        frequency = LSE_VALUE;
      }
      /* Clock not enabled for COMP3 */
      else
      {
        /* nothing to do: frequency already initialized to 0 */
      }
      break;
    }
    
    case RCC_PERIPHCLK_COMP4:
    {
      /* Get the current COMP4 source */
      srcclk = __HAL_RCC_GET_COMP4_SOURCE();

      if(srcclk == RCC_COMP4CLKSOURCE_PCLK2)
      {
        frequency = HAL_RCC_GetPCLK2Freq();
      }
      else if((HAL_IS_BIT_SET(RCC->BDCR, RCC_BDCR_LSIRDY)) && (srcclk == RCC_COMP4CLKSOURCE_LSI))
      {
        frequency = LSI_VALUE;
      }
      else if((HAL_IS_BIT_SET(RCC->BDCR, RCC_BDCR_LSERDY)) && (srcclk == RCC_COMP4CLKSOURCE_LSE))
      {
        frequency = LSE_VALUE;
      }
      /* Clock not enabled for COMP4 */
      else
      {
        /* nothing to do: frequency already initialized to 0 */
      }
      break;
    }
    
    case RCC_PERIPHCLK_PVD:
    {
      /* Get the current PVD filter source */
      srcclk = __HAL_RCC_GET_PVD_FILTER_SOURCE();

      if((HAL_IS_BIT_SET(RCC->BDCR, RCC_BDCR_LSIRDY)) && (srcclk == RCC_PVDFILTERCLK_LSI))
      {
        frequency = LSI_VALUE;
      }
      else if((HAL_IS_BIT_SET(RCC->BDCR, RCC_BDCR_LSERDY)) && (srcclk == RCC_PVDFILTERCLK_LSE))
      {
        frequency = LSE_VALUE;
      }
      else if(srcclk == RCC_PVDFILTERCLK_PCLK1)
      {
        frequency = HAL_RCC_GetPCLK1Freq();
      }
      /* Clock not enabled for PVD */
      else
      {
        /* nothing to do: frequency already initialized to 0 */
      }
      break;
    }
    
    case RCC_PERIPHCLK_FDCAN:
    {
      /* Get RCC CCIPR2 configuration ------------------------------------------------------*/
      temp_reg = RCC->CCIPR2;
      
      if((temp_reg & RCC_CCIPR2_FDCANCKSEL) == RCC_FDCANCLKSOURCE_PCLK1)
      {
        frequency = HAL_RCC_GetPCLK1Freq();
      }
      else if(((temp_reg & RCC_CCIPR2_FDCANCKSEL_1) == RCC_FDCANCLKSOURCE_HSE) && (HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSERDY)))
      {
        frequency = HSE_VALUE;
      }
      else if (((temp_reg & RCC_CCIPR2_FDCANCKSEL) == RCC_FDCANCLKSOURCE_PLL) && (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLLRDY)))
      {
        frequency = RCCEx_GetPLLClockFreq() / __HAL_RCC_GET_FDCAN_PLLDIV();
      }
      else
      {
        /* nothing to do: frequency already initialized to 0 */
      }
      break;
    }
    
    case RCC_PERIPHCLK_ADC:
    {
      /* Get the current ADC source */
      srcclk = __HAL_RCC_GET_ADC_SOURCE();
      
      if (srcclk == RCC_ADCCLKSOURCE_SYSCLK)
      {
        frequency = HAL_RCC_GetSysClockFreq();
      }
      else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLLRDY)) && (srcclk == RCC_ADCCLKSOURCE_PLL))
      {
        frequency = RCCEx_GetPLLClockFreq() / __HAL_RCC_GET_ADC_PLLDIV();
      }
      else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY)) && (srcclk == RCC_ADCCLKSOURCE_HSI))
      {
        hsiIndex = (RCC->ICSCR & RCC_ICSCR_HSI_FS_Msk) >> RCC_ICSCR_HSI_FS_Pos;
        frequency = hsiValue[hsiIndex];
      }
      /* Clock not enabled for ADC */
      else
      {
        /* nothing to do: frequency already initialized to 0 */
      }
      break;
    }
    
    case RCC_PERIPHCLK_LPTIM:
    {
      /* Get the current LPTIM1 source */
      srcclk = __HAL_RCC_GET_LPTIM_SOURCE();

      if(srcclk == RCC_LPTIMCLKSOURCE_PCLK1)
      {
        frequency = HAL_RCC_GetPCLK1Freq();
      }
      else if((HAL_IS_BIT_SET(RCC->BDCR, RCC_BDCR_LSIRDY)) && (srcclk == RCC_LPTIMCLKSOURCE_LSI))
      {
        frequency = LSI_VALUE;
      }
      else if((HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY)) && (srcclk == RCC_LPTIMCLKSOURCE_HSI))
      {
        hsiIndex = (RCC->ICSCR & RCC_ICSCR_HSI_FS_Msk) >> RCC_ICSCR_HSI_FS_Pos;
        frequency = hsiValue[hsiIndex];
      }
      else if((HAL_IS_BIT_SET(RCC->BDCR, RCC_BDCR_LSERDY)) && (srcclk == RCC_LPTIMCLKSOURCE_LSE))
      {
        frequency = LSE_VALUE;
      }
      /* Clock not enabled for LPTIM1 */
      else
      {
        /* nothing to do: frequency already initialized to 0 */
      }
      break;
    }
    
    default:
    {
      break;
    }
  }
  
  return (frequency);
}
/**
  * @brief  Returns the PLL clock frequencies.
  * @note   The function returns values based on HSE_VALUE or HSI_VALUE multiplied by the PLL
  *         factors.
  * @note   This function can be used by the user application to compute the
  *         baud-rate for the communication peripherals or configure other parameters.
  * @retval Frequency in Hz
  */
static uint32_t RCCEx_GetPLLClockFreq(void)
{
  uint32_t freq = 0, pllsource = 0, pllmul = 0, hsiIndex = 0;
  const uint32_t hsiValue[4] = {8000000U, 16000000U, 24000000U, 48000000U};

  pllsource = READ_BIT(RCC->PLLCFGR1, RCC_PLLCFGR1_PLLSRC);
  pllmul = (READ_BIT(RCC->PLLCFGR1, RCC_PLLCFGR1_PLLMUL) >> RCC_PLLCFGR1_PLLMUL_Pos) + 2U ;

  switch (pllsource)
  {
#if defined(RCC_HSE_SUPPORT)
  case RCC_PLLSOURCE_HSE:  /* HSE used as PLL clock source */
    freq = (HSE_VALUE * pllmul);
    break;
#endif
  case RCC_PLLSOURCE_HSI:  /* HSI used as PLL clock source */
  default:
    hsiIndex = (RCC->ICSCR & RCC_ICSCR_HSI_FS_Msk) >> RCC_ICSCR_HSI_FS_Pos;
    
    /* HSI used as PLL clock source : PLLCLK = HSI * PLLMUL */
    freq = (uint32_t)(hsiValue[hsiIndex] * pllmul);
    break;
  }

  return freq;
}
/**
  * @}
  */

/**
  * @}
  */

/**
  * @}
  */

#endif /* HAL_RCC_MODULE_ENABLED */

/**
  * @}
  */

/************************ (C) COPYRIGHT Puya *****END OF FILE******************/

