/**
******************************************************************************
* @file    py32f420xC.h
* @brief   CMSIS Cortex-M4 Device Peripheral Access Layer Header File.
*          This file contains all the peripheral register's definitions, bits
*          definitions and memory mapping for PY32F4xx devices.
* @version v1.0.0
*
  ******************************************************************************
  * @attention
  *
  * <h2><center>&copy; Copyright (c) 2023 Puya Semiconductor Co.
  * All rights reserved.</center></h2>
  *
  * This software component is licensed by Puya under BSD 3-Clause license,
  * the "License"; You may not use this file except in compliance with the
  * License. You may obtain a copy of the License at:
  *                        opensource.org/licenses/BSD-3-Clause
  *
  ******************************************************************************
  * @attention
  *
  * <h2><center>&copy; Copyright (c) 2016 STMicroelectronics.
  * All rights reserved.</center></h2>
  *
  * This software component is licensed by ST under BSD 3-Clause license,
  * the "License"; You may not use this file except in compliance with the
  * License. You may obtain a copy of the License at:
  *                        opensource.org/licenses/BSD-3-Clause
  *
  ******************************************************************************
  */

#ifndef __PY32F420xC_H
#define __PY32F420xC_H

#ifdef __cplusplus
extern "C" {
#endif /* __cplusplus */

/**
* @brief Configuration of the Cortex-M4 Processor and Core Peripherals
*/
#define __CM4_REV                 0x0001U  /*!< Core revision r0p1                            */
#define __MPU_PRESENT             0U       /*!< PY32F4xx provides an MPU                      */
#define __NVIC_PRIO_BITS          3U       /*!< PY32F4xx uses 3 Bits for the Priority Levels  */
#define __Vendor_SysTickConfig    0U       /*!< Set to 1 if different SysTick Config is used  */
#define __FPU_PRESENT             1U       /*!< FPU present                                   */

/**
 * @brief PY32F4xx Interrupt Number Definition, according to the selected device
 *        in @ref Library_configuration_section
 */
typedef enum
{
  /******  Cortex-M4 Processor Exceptions Numbers **************************************************************/
  NonMaskableInt_IRQn         = -14,    /*!< 2 Non Maskable Interrupt                                          */
  HardFault_IRQn              = -13,    /*!< 3 Cortex-M4 Hard Fault Interrupt                                  */
  MemoryManagement_IRQn       = -12,    /*!< 4 Cortex-M4 Memory Management Interrupt                           */
  BusFault_IRQn               = -11,    /*!< 5 Cortex-M4 Bus Fault Interrupt                                   */
  UsageFault_IRQn             = -10,    /*!< 6 Cortex-M4 Usage Fault Interrupt                                 */
  SVCall_IRQn                 = -5,     /*!< 11 Cortex-M4 SV Call Interrupt                                    */
  DebugMonitor_IRQn           = -4,     /*!< 12 Cortex-M4 Debug Monitor Interrupt                              */
  PendSV_IRQn                 = -2,     /*!< 14 Cortex-M4 Pend SV Interrupt                                    */
  SysTick_IRQn                = -1,     /*!< 15 Cortex-M4 System Tick Interrupt                                */
  WWDG_IRQn                   = 0,      /*!< Window WatchDog Interrupt                                         */
  PVD_IRQn                    = 1,      /*!< PVD through EXTI Line detection Interrupt                         */
  TAMPER_IRQn                 = 2,      /*!< TAMPER global Interrupt                                           */
  RTC_IRQn                    = 3,      /*!< RTC global Interrupt                                              */
  FLASH_IRQn                  = 4,      /*!< FLASH global Interrupt                                            */
  RCC_IRQn                    = 5,      /*!< RCC global Interrupt                                              */
  EXTI0_IRQn                  = 6,      /*!< EXTI Line0 Interrupt                                              */
  EXTI1_IRQn                  = 7,      /*!< EXTI Line1 Interrupt                                              */
  EXTI2_IRQn                  = 8,      /*!< EXTI Line2 Interrupt                                              */
  EXTI3_IRQn                  = 9,      /*!< EXTI Line3 Interrupt                                              */
  EXTI4_IRQn                  = 10,     /*!< EXTI Line4 Interrupt                                              */
  EXTI9_5_IRQn                = 11,     /*!< External Line[5:9] Interrupt                                      */
  EXTI15_10_IRQn              = 12,     /*!< External Line[15:10] Interrupt                                    */
  DMA_Channel1_IRQn           = 13,     /*!< DMA Channel 1 global Interrupt                                    */
  DMA_Channel2_IRQn           = 14,     /*!< DMA Channel 2 global Interrupt                                    */
  DMA_Channel3_IRQn           = 15,     /*!< DMA Channel 3 global Interrupt                                    */
  DMA_Channel4_IRQn           = 16,     /*!< DMA Channel 4 global Interrupt                                    */
  DMA_Channel5_IRQn           = 17,     /*!< DMA Channel 5 global Interrupt                                    */
  ADC1_IRQn                   = 18,     /*!< ADC1 global Interrupt                                             */
  ADC2_IRQn                   = 19,     /*!< ADC2 global Interrupt                                             */
  DAC_IRQn                    = 20,     /*!< DAC global Interrupt                                              */
  TIM1_BRK_IRQn               = 21,     /*!< TIM1 global Interrupt                                             */
  TIM1_UP_IRQn                = 22,     /*!< TIM1 Update Interrupt global Interrupt                            */
  TIM1_TRG_COM_IRQn           = 23,     /*!< TIM1 Trigger and Commutation Interrupt global interrupt           */
  TIM1_CC_IRQn                = 24,     /*!< TIM1 Capture Compare Interrupt                                    */
  TIM2_IRQn                   = 25,     /*!< TIM2 global Interrupt                                             */
  TIM3_IRQn                   = 26,     /*!< TIM3 global Interrupt                                             */
  TIM6_IRQn                   = 27,     /*!< TIM6 global Interrupt                                             */
  TIM7_IRQn                   = 28,     /*!< TIM7 global Interrupt                                             */
  TIM8_BRK_IRQn               = 29,     /*!< TIM8 global Interrupt                                             */
  TIM8_UP_IRQn                = 30,     /*!< TIM8 Update Interrupt global Interrupt                            */
  TIM8_TRG_COM_IRQn           = 31,     /*!< TIM8 Trigger and Commutation Interrupt global interrupt           */
  TIM8_CC_IRQn                = 32,     /*!< TIM8 Capture Compare Interrupt                                    */
  LPTIM_IRQn                  = 33,     /*!< LPTIM global Interrupt                                            */
  SPI1_IRQn                   = 34,     /*!< SPI1 global Interrupt                                             */
  SPI2_IRQn                   = 35,     /*!< SPI2 global Interrupt                                             */
  USART1_IRQn                 = 36,     /*!< USART1 global Interrupt                                           */
  UART1_IRQn                  = 37,     /*!< UART1 global Interrupt                                            */
  UART2_IRQn                  = 38,     /*!< UART2 global Interrupt                                            */
  LPUART1_IRQn                = 39,     /*!< LPUART1 global Interrupt                                          */
  RTC_ALARM_IRQn              = 40,     /*!< RTC_ALARM global Interrupt                                        */
  I2C1_EV_IRQn                = 41,     /*!< I2C1 Event Interrupt                                              */
  I2C1_ER_IRQn                = 42,     /*!< I2C1 Error Interrupt                                              */
  I2C2_EV_IRQn                = 43,     /*!< I2C2 Event Interrupt                                              */
  I2C2_ER_IRQn                = 44,     /*!< I2C2 Error Interrupt                                              */
  FDCAN_INT0_IRQn             = 45,     /*!< FDCAN_INT0 Interrupt                                              */
  FDCAN_INT1_IRQn             = 46,     /*!< FDCAN_INT1 Interrupt                                              */
  COMP1_IRQn                  = 47,     /*!< COMP1 global Interrupt                                            */
  COMP2_IRQn                  = 48,     /*!< COMP2 global Interrupt                                            */
  COMP3_IRQn                  = 49,     /*!< COMP3 global Interrupt                                            */
  COMP4_IRQn                  = 50,     /*!< COMP4 global Interrupt                                            */
  EPWM1_IRQn                  = 51,     /*!< EPWM1 global Interrupt                                            */
  EPWM2_IRQn                  = 52,     /*!< EPWM2 global Interrupt                                            */
  EPWM3_IRQn                  = 53,     /*!< EPWM3 global Interrupt                                            */
  EPWM4_IRQn                  = 54,     /*!< EPWM4 global Interrupt                                            */
  EPWM5_IRQn                  = 55,     /*!< EPWM5 global Interrupt                                            */
  EPWM6_IRQn                  = 56,     /*!< EPWM6 global Interrupt                                            */
  EPWM1_TZ_IRQn               = 57,     /*!< EPWM1 TZ global Interrupt                                         */
  EPWM2_TZ_IRQn               = 58,     /*!< EPWM2 TZ global Interrupt                                         */
  EPWM3_TZ_IRQn               = 59,     /*!< EPWM3 TZ global Interrupt                                         */
  EPWM4_TZ_IRQn               = 60,     /*!< EPWM4 TZ global Interrupt                                         */
  EPWM5_TZ_IRQn               = 61,     /*!< EPWM5 TZ global Interrupt                                         */
  EPWM6_TZ_IRQn               = 62,     /*!< EPWM6 TZ global Interrupt                                         */
} IRQn_Type;

#include "core_cm4.h"             /* Cortex-M4 processor and core peripherals */
#include "system_py32f4xx.h"
#include <stdint.h>
typedef struct
{
  __IO uint32_t CCR;              /*!< DMA channel x configuration register        */
  __IO uint32_t CNDTR;            /*!< DMA channel x number of data register       */
  __IO uint32_t CPAR;             /*!< DMA channel x peripheral address register   */
  __IO uint32_t CMAR;             /*!< DMA channel x memory address register       */
  __IO uint32_t CNBTR;            /*!< DMA channel x CNBTR register                */
} DMA_Channel_TypeDef;

/**
* @brief FLASH Registers
*/
typedef struct
{
   __IO uint32_t ACR;                             /*!<  FLASH_ACR Register,                          Address offset: 0x00  */
   __IO uint32_t RESERVED1;                        
   __IO uint32_t KEYR;                            /*!<  FLASH_KEYR Register,                         Address offset: 0x08  */
   __IO uint32_t OPTKEYR;                         /*!<  FLASH_OPTKEYR Register,                      Address offset: 0x0C  */
   __IO uint32_t SR;                              /*!<  FLASH_SR Register,                           Address offset: 0x10  */
   __IO uint32_t CR;                              /*!<  FLASH_CR Register,                           Address offset: 0x14  */
   __IO uint32_t RESERVED2[2];                     
   __IO uint32_t OPTR1;                           /*!<  FLASH_OPTR1 Register,                        Address offset: 0x20  */
   __IO uint32_t OPTR2;                           /*!<  FLASH_OPTR2 Register,                        Address offset: 0x24  */
   __IO uint32_t WRPR0;                           /*!<  FLASH_WRPR0 Register,                        Address offset: 0x28  */
   __IO uint32_t PCROPR0;                         /*!<  FLASH_PCROPR0 Register,                      Address offset: 0x2C  */
   __IO uint32_t SECR0;                           /*!<  FLASH_SECR0 Register,                        Address offset: 0x30  */
   __IO uint32_t WRPR1;                           /*!<  FLASH_WRPR1 Register,                        Address offset: 0x34  */
   __IO uint32_t PCROPR1;                         /*!<  FLASH_PCROPR1 Register,                      Address offset: 0x38  */
   __IO uint32_t SECR1;                           /*!<  FLASH_SECR1 Register,                        Address offset: 0x3C  */
   __IO uint32_t RESERVED3[8];                     
   __IO uint32_t OPTBFB;                          /*!<  FLASH_OPTBFB Register,                       Address offset: 0x60  */
} FLASH_TypeDef;

/**
* @brief RCC Registers
*/
typedef struct
{
   __IO uint32_t CR;                              /*!<  RCC_CR Register,                             Address offset: 0x00  */
   __IO uint32_t RESERVED1;                        
   __IO uint32_t ICSCR;                           /*!<  RCC_ICSCR Register,                          Address offset: 0x08  */
   __IO uint32_t RESERVED2[2];                     
   __IO uint32_t CFGR1;                           /*!<  RCC_CFGR1 Register,                          Address offset: 0x14  */
   __IO uint32_t CFGR2;                           /*!<  RCC_CFGR2 Register,                          Address offset: 0x18  */
   __IO uint32_t RESERVED3[2];                     
   __IO uint32_t PLLCFGR1;                        /*!<  RCC_PLLCFGR1 Register,                       Address offset: 0x24  */
   __IO uint32_t RESERVED4[4];                     
   __IO uint32_t ECSCR;                           /*!<  RCC_ECSCR Register,                          Address offset: 0x38  */
   __IO uint32_t CIER;                            /*!<  RCC_CIER Register,                           Address offset: 0x3C  */
   __IO uint32_t CIFR;                            /*!<  RCC_CIFR Register,                           Address offset: 0x40  */
   __IO uint32_t CICR;                            /*!<  RCC_CICR Register,                           Address offset: 0x44  */
   __IO uint32_t AHBRSTR1;                        /*!<  RCC_AHBRSTR1 Register,                       Address offset: 0x48  */
   __IO uint32_t AHBRSTR2;                        /*!<  RCC_AHBRSTR2 Register,                       Address offset: 0x4C  */
   __IO uint32_t RESERVED5[2];                     
   __IO uint32_t APBRSTR1;                        /*!<  RCC_APBRSTR1 Register,                       Address offset: 0x58  */
   __IO uint32_t APBRSTR2;                        /*!<  RCC_APBRSTR2 Register,                       Address offset: 0x5C  */
   __IO uint32_t APBRSTR3;                        /*!<  RCC_APBRSTR3 Register,                       Address offset: 0x60  */
   __IO uint32_t APBRSTR4;                        /*!<  RCC_APBRSTR4 Register,                       Address offset: 0x64  */
   __IO uint32_t RESERVED6[2];                     
   __IO uint32_t AHBENR1;                         /*!<  RCC_AHBENR1 Register,                        Address offset: 0x70  */
   __IO uint32_t AHBENR2;                         /*!<  RCC_AHBENR2 Register,                        Address offset: 0x74  */
   __IO uint32_t RESERVED7[2];                     
   __IO uint32_t APBENR1;                         /*!<  RCC_APBENR1 Register,                        Address offset: 0x80  */
   __IO uint32_t APBENR2;                         /*!<  RCC_APBENR2 Register,                        Address offset: 0x84  */
   __IO uint32_t APBENR3;                         /*!<  RCC_APBENR3 Register,                        Address offset: 0x88  */
   __IO uint32_t APBENR4;                         /*!<  RCC_APBENR4 Register,                        Address offset: 0x8C  */
   __IO uint32_t RESERVED8[2];                     
   __IO uint32_t CCIPR1;                          /*!<  RCC_CCIPR1 Register,                         Address offset: 0x98  */
   __IO uint32_t CCIPR2;                          /*!<  RCC_CCIPR2 Register,                         Address offset: 0x9C  */
   __IO uint32_t CCIPR3;                          /*!<  RCC_CCIPR3 Register,                         Address offset: 0xA0  */
   __IO uint32_t RESERVED9[3];                     
   __IO uint32_t BDCR;                            /*!<  RCC_BDCR Register,                           Address offset: 0xB0  */
   __IO uint32_t RESERVED10;                       
   __IO uint32_t CSR;                             /*!<  RCC_CSR Register,                            Address offset: 0xB8  */
} RCC_TypeDef;

/**
* @brief RTC Registers
*/
typedef struct
{
   __IO uint32_t CRH;                             /*!<  RTC_CRH Register,                            Address offset: 0x00  */
   __IO uint32_t CRL;                             /*!<  RTC_CRL Register,                            Address offset: 0x04  */
   __IO uint32_t PRLH;                            /*!<  RTC_PRLH Register,                           Address offset: 0x08  */
   __IO uint32_t PRLL;                            /*!<  RTC_PRLL Register,                           Address offset: 0x0C  */
   __IO uint32_t DIVH;                            /*!<  RTC_DIVH Register,                           Address offset: 0x10  */
   __IO uint32_t DIVL;                            /*!<  RTC_DIVL Register,                           Address offset: 0x14  */
   __IO uint32_t CNTH;                            /*!<  RTC_CNTH Register,                           Address offset: 0x18  */
   __IO uint32_t CNTL;                            /*!<  RTC_CNTL Register,                           Address offset: 0x1C  */
   __IO uint32_t ALRH;                            /*!<  RTC_ALRH Register,                           Address offset: 0x20  */
   __IO uint32_t ALRL;                            /*!<  RTC_ALRL Register,                           Address offset: 0x24  */
   __IO uint32_t RESERVED1[2];                     
   __IO uint32_t TMPCFGR;                         /*!<  RTC_TMPCFGR Register,                        Address offset: 0x30  */
   __IO uint32_t TMPCSR;                          /*!<  RTC_TMPCSR Register,                         Address offset: 0x34  */
   __IO uint32_t CALIBR;                          /*!<  RTC_CALIBR Register,                         Address offset: 0x38  */
   __IO uint32_t RESERVED2;                        
   __IO uint32_t BKPDR0;                          /*!<  RTC_BKPDR0 Register,                         Address offset: 0x40  */
   __IO uint32_t BKPDR1;                          /*!<  RTC_BKPDR1 Register,                         Address offset: 0x44  */
   __IO uint32_t BKPDR2;                          /*!<  RTC_BKPDR2 Register,                         Address offset: 0x48  */
   __IO uint32_t BKPDR3;                          /*!<  RTC_BKPDR3 Register,                         Address offset: 0x4C  */
   __IO uint32_t BKPDR4;                          /*!<  RTC_BKPDR4 Register,                         Address offset: 0x50  */
} RTC_TypeDef;

/**
* @brief CRC Registers
*/
typedef struct
{
   __IO uint32_t DR;                              /*!<  CRC_DR Register,                             Address offset: 0x00  */
   __IO uint32_t IDR;                             /*!<  CRC_IDR Register,                            Address offset: 0x04  */
   __IO uint32_t CR;                              /*!<  CRC_CR Register,                             Address offset: 0x08  */
} CRC_TypeDef;

/**
* @brief GPIO Registers
*/
typedef struct
{
   __IO uint32_t MODER;                           /*!<  GPIO_MODER Register,                         Address offset: 0x00  */
   __IO uint32_t OTYPER;                          /*!<  GPIO_OTYPER Register,                        Address offset: 0x04  */
   __IO uint32_t OSPEEDR;                         /*!<  GPIO_OSPEEDR Register,                       Address offset: 0x08  */
   __IO uint32_t PUPDR;                           /*!<  GPIO_PUPDR Register,                         Address offset: 0x0C  */
   __IO uint32_t IDR;                             /*!<  GPIO_IDR Register,                           Address offset: 0x10  */
   __IO uint32_t ODR;                             /*!<  GPIO_ODR Register,                           Address offset: 0x14  */
   __IO uint32_t BSRR;                            /*!<  GPIO_BSRR Register,                          Address offset: 0x18  */
   __IO uint32_t LCKR;                            /*!<  GPIO_LCKR Register,                          Address offset: 0x1C  */
   __IO uint32_t AFR[2];                          /*!< GPIO alternate function registers,            Address offset: 0x20-0x24 */
   __IO uint32_t BRR;                             /*!<  GPIO_BRR Register,                           Address offset: 0x28  */
} GPIO_TypeDef;

/**
* @brief SYSCFG Registers
*/
typedef struct
{
   __IO uint32_t CFGR[4];                         /*!<  SYSCFG_CFGR1 Register,                       Address offset: 0x00  */
   __IO uint32_t RESERVED1;                        
   __IO uint32_t EXTICR[4];                       /*!<  SYSCFG_EXTICR1 Register,                     Address offset: 0x14  */
   __IO uint32_t PAENS;                           /*!<  SYSCFG_PAENS Register,                       Address offset: 0x24  */
   __IO uint32_t PBENS;                           /*!<  SYSCFG_PBENS Register,                       Address offset: 0x28  */
   __IO uint32_t PCENS;                           /*!<  SYSCFG_PCENS Register,                       Address offset: 0x2C  */
   __IO uint32_t PDENS;                           /*!<  SYSCFG_PDENS Register,                       Address offset: 0x30  */
} SYSCFG_TypeDef;

/**
* @brief BKP Registers
*/
typedef struct
{
   __IO uint32_t DR0;                             /*!<  BKP_DR0 Register,                            Address offset: 0x00  */
   __IO uint32_t DR1;                             /*!<  BKP_DR1 Register,                            Address offset: 0x04  */
   __IO uint32_t DR2;                             /*!<  BKP_DR2 Register,                            Address offset: 0x08  */
   __IO uint32_t DR3;                             /*!<  BKP_DR3 Register,                            Address offset: 0x0C  */
   __IO uint32_t DR4;                             /*!<  BKP_DR4 Register,                            Address offset: 0x10  */
} BKP_TypeDef;

/**
* @brief DMA Registers
*/
typedef struct
{
   __IO uint32_t ISR;                             /*!<  DMA_ISR Register,                            Address offset: 0x00  */
   __IO uint32_t IFCR;                            /*!<  DMA_IFCR Register,                           Address offset: 0x04  */
   __IO uint32_t CCR1;                            /*!<  DMA_CCR1 Register,                           Address offset: 0x08  */
   __IO uint32_t CNDTR1;                          /*!<  DMA_CNDTR1 Register,                         Address offset: 0x0C  */
   __IO uint32_t CPAR1;                           /*!<  DMA_CPAR1 Register,                          Address offset: 0x10  */
   __IO uint32_t CMAR1;                           /*!<  DMA_CMAR1 Register,                          Address offset: 0x14  */
   __IO uint32_t CCCFGR1;                         /*!<  DMA_CCCFGR1 Register,                        Address offset: 0x18  */
   __IO uint32_t CCR2;                            /*!<  DMA_CCR2 Register,                           Address offset: 0x1C  */
   __IO uint32_t CNDTR2;                          /*!<  DMA_CNDTR2 Register,                         Address offset: 0x20  */
   __IO uint32_t CPAR2;                           /*!<  DMA_CPAR2 Register,                          Address offset: 0x24  */
   __IO uint32_t CMAR2;                           /*!<  DMA_CMAR2 Register,                          Address offset: 0x28  */
   __IO uint32_t CCCFGR2;                         /*!<  DMA_CCCFGR2 Register,                        Address offset: 0x2C  */
   __IO uint32_t CCR3;                            /*!<  DMA_CCR3 Register,                           Address offset: 0x30  */
   __IO uint32_t CNDTR3;                          /*!<  DMA_CNDTR3 Register,                         Address offset: 0x34  */
   __IO uint32_t CPAR3;                           /*!<  DMA_CPAR3 Register,                          Address offset: 0x38  */
   __IO uint32_t CMAR3;                           /*!<  DMA_CMAR3 Register,                          Address offset: 0x3C  */
   __IO uint32_t CCCFGR3;                         /*!<  DMA_CCCFGR3 Register,                        Address offset: 0x40  */
   __IO uint32_t CCR4;                            /*!<  DMA_CCR4 Register,                           Address offset: 0x44  */
   __IO uint32_t CNDTR4;                          /*!<  DMA_CNDTR4 Register,                         Address offset: 0x48  */
   __IO uint32_t CPAR4;                           /*!<  DMA_CPAR4 Register,                          Address offset: 0x4C  */
   __IO uint32_t CMAR4;                           /*!<  DMA_CMAR4 Register,                          Address offset: 0x50  */
   __IO uint32_t CCCFGR4;                         /*!<  DMA_CCCFGR4 Register,                        Address offset: 0x54  */
   __IO uint32_t CCR5;                            /*!<  DMA_CCR5 Register,                           Address offset: 0x58  */
   __IO uint32_t CNDTR5;                          /*!<  DMA_CNDTR5 Register,                         Address offset: 0x5C  */
   __IO uint32_t CPAR5;                           /*!<  DMA_CPAR5 Register,                          Address offset: 0x60  */
   __IO uint32_t CMAR5;                           /*!<  DMA_CMAR5 Register,                          Address offset: 0x64  */
   __IO uint32_t CCCFGR5;                         /*!<  DMA_CCCFGR5 Register,                        Address offset: 0x68  */
} DMA_TypeDef;

/**
* @brief EXTI Registers
*/
typedef struct
{
   __IO uint32_t IMR;                             /*!<  EXTI_IMR Register,                           Address offset: 0x00  */
   __IO uint32_t EMR;                             /*!<  EXTI_EMR Register,                           Address offset: 0x04  */
   __IO uint32_t RTSR;                            /*!<  EXTI_RTSR Register,                          Address offset: 0x08  */
   __IO uint32_t FTSR;                            /*!<  EXTI_FTSR Register,                          Address offset: 0x0C  */
   __IO uint32_t SWIER;                           /*!<  EXTI_SWIER Register,                         Address offset: 0x10  */
   __IO uint32_t PR;                              /*!<  EXTI_PR Register,                            Address offset: 0x14  */
} EXTI_TypeDef;

/**
* @brief ADC Registers
*/
typedef struct
{
   __IO uint32_t ISR;                             /*!<  ADC_ISR Register,                            Address offset: 0x00  */
   __IO uint32_t IER;                             /*!<  ADC_IER Register,                            Address offset: 0x04  */
   __IO uint32_t CR;                              /*!<  ADC_CR Register,                             Address offset: 0x08  */
   __IO uint32_t CFGR;                            /*!<  ADC_CFGR Register,                           Address offset: 0x0C  */
   __IO uint32_t CFGR2;                           /*!<  ADC_CFGR2 Register,                          Address offset: 0x10  */
   __IO uint32_t SMPR1;                           /*!<  ADC_SMPR1 Register,                          Address offset: 0x14  */
   __IO uint32_t SMPR2;                           /*!<  ADC_SMPR2 Register,                          Address offset: 0x18  */
   __IO uint32_t SMPR3;                           /*!<  ADC_SMPR3 Register,                          Address offset: 0x1C  */
   __IO uint32_t RESERVED1;
   __IO uint32_t TR1;                             /*!<  ADC_TR1 Register,                            Address offset: 0x24  */
   __IO uint32_t TR2;                             /*!<  ADC_TR2 Register,                            Address offset: 0x28  */
   __IO uint32_t TR3;                             /*!<  ADC_TR3 Register,                            Address offset: 0x2C  */
   __IO uint32_t SQR1;                            /*!<  ADC_SQR1 Register,                           Address offset: 0x30  */
   __IO uint32_t SQR2;                            /*!<  ADC_SQR2 Register,                           Address offset: 0x34  */
   __IO uint32_t SQR3;                            /*!<  ADC_SQR3 Register,                           Address offset: 0x38  */
   __IO uint32_t SQR4;                            /*!<  ADC_SQR4 Register,                           Address offset: 0x3C  */
   __IO uint32_t DR;                              /*!<  ADC_DR Register,                             Address offset: 0x40  */
   __IO uint32_t RESERVED2[2];                     
   __IO uint32_t JSQR;                            /*!<  ADC_JSQR Register,                           Address offset: 0x4C  */
   __IO uint32_t RESERVED3[4];                     
   __IO uint32_t OFR1;                            /*!<  ADC_OFR1 Register,                           Address offset: 0x60  */
   __IO uint32_t OFR2;                            /*!<  ADC_OFR2 Register,                           Address offset: 0x64  */
   __IO uint32_t OFR3;                            /*!<  ADC_OFR3 Register,                           Address offset: 0x68  */
   __IO uint32_t OFR4;                            /*!<  ADC_OFR4 Register,                           Address offset: 0x6C  */
   __IO uint32_t RESERVED4[4];                     
   __IO uint32_t JDR1;                            /*!<  ADC_JDR1 Register,                           Address offset: 0x80  */
   __IO uint32_t JDR2;                            /*!<  ADC_JDR2 Register,                           Address offset: 0x84  */
   __IO uint32_t JDR3;                            /*!<  ADC_JDR3 Register,                           Address offset: 0x88  */
   __IO uint32_t JDR4;                            /*!<  ADC_JDR4 Register,                           Address offset: 0x8C  */
   __IO uint32_t RESERVED5[4];                     
   __IO uint32_t AWD2CR;                          /*!<  ADC_AWD2CR Register,                         Address offset: 0xA0  */
   __IO uint32_t AWD3CR;                          /*!<  ADC_AWD3CR Register,                         Address offset: 0xA4  */
   __IO uint32_t RESERVED6[2];                     
   __IO uint32_t DIFSEL;                          /*!<  ADC_DIFSEL Register,                         Address offset: 0xB0  */
   __IO uint32_t CALFACT;                         /*!<  ADC_CALFACT Register,                        Address offset: 0xB4  */
   __IO uint32_t RESERVED7[2];                     
   __IO uint32_t GCOMP;                           /*!<  ADC_GCOMP Register,                          Address offset: 0xC0  */
   __IO uint32_t ANACR;                           /*!<  ADC_ANACR Register,                          Address offset: 0xC4  */
   __IO uint32_t RESERVED8[143];                   
   __IO uint32_t CSR;                             /*!<  ADC_CSR Register,                            Address offset: 0x304  */
   __IO uint32_t CCR;                             /*!<  ADC_CCR Register,                            Address offset: 0x308  */
   __IO uint32_t CDR;                             /*!<  ADC_CDR Register,                            Address offset: 0x30C  */
} ADC_TypeDef;

typedef struct
{
  __IO uint32_t CSR;              /*!< ADCX CSR Register,                  Address offset: 0x304  */
  __IO uint32_t CCR;          /*!< ADC common configuration register,     Address offset: 0x300 + 0x08 */
  __IO uint32_t CDR;              /*!< ADCX CDR Register,                  Address offset: 0x30C  */
} ADC_Common_TypeDef;

/**
* @brief DAC Registers
*/
typedef struct
{
   __IO uint32_t CR;                              /*!<  DAC_CR Register,                             Address offset: 0x00  */
   __IO uint32_t SWTRIGR;                         /*!<  DAC_SWTRIGR Register,                        Address offset: 0x04  */
   __IO uint32_t DHR12R1;                         /*!<  DAC_DHR12R1 Register,                        Address offset: 0x08  */
   __IO uint32_t DHR12L1;                         /*!<  DAC_DHR12L1 Register,                        Address offset: 0x0C  */
   __IO uint32_t DHR8R1;                          /*!<  DAC_DHR8R1 Register,                         Address offset: 0x10  */
   __IO uint32_t DHR12R2;                         /*!<  DAC_DHR12R2 Register,                        Address offset: 0x14  */
   __IO uint32_t DHR12L2;                         /*!<  DAC_DHR12L2 Register,                        Address offset: 0x18  */
   __IO uint32_t DHR8R2;                          /*!<  DAC_DHR8R2 Register,                         Address offset: 0x1C  */
   __IO uint32_t DHR12RD;                         /*!<  DAC_DHR12RD Register,                        Address offset: 0x20  */
   __IO uint32_t DHR12LD;                         /*!<  DAC_DHR12LD Register,                        Address offset: 0x24  */
   __IO uint32_t DHR8RD;                          /*!<  DAC_DHR8RD Register,                         Address offset: 0x28  */
   __IO uint32_t DOR1;                            /*!<  DAC_DOR1 Register,                           Address offset: 0x2C  */
   __IO uint32_t DOR2;                            /*!<  DAC_DOR2 Register,                           Address offset: 0x30  */
   __IO uint32_t SR;                              /*!<  DAC_SR Register,                             Address offset: 0x34  */
   __IO uint32_t OC;                              /*!<  DAC_OC Register,                             Address offset: 0x38  */
   __IO uint32_t RESERVED1[7];                     
   __IO uint32_t RAMPCFGR1;                       /*!<  DAC_RAMPCFGR1 Register,                      Address offset: 0x58  */
   __IO uint32_t RAMPCFGR2;                       /*!<  DAC_RAMPCFGR2 Register,                      Address offset: 0x5C  */
   __IO uint32_t RESERVED2;                        
   __IO uint32_t RAMPDLYS;                        /*!<  DAC_RAMPDLYS Register,                       Address offset: 0x64  */
   __IO uint32_t RAMPCR;                          /*!<  DAC_RAMPCR Register,                         Address offset: 0x68  */
   __IO uint32_t CLKCR;                           /*!<  DAC_CLKCR Register,                          Address offset: 0x6C  */
} DAC_TypeDef;

/**
  * @brief Comparator
  */
typedef struct
{
  __IO uint32_t CSR;              /*!< COMP control and status register,           Address offset: 0x00 */
  __IO uint32_t FR;               /*!< COMP filter register,                       Address offset: 0x04 */
} COMP_TypeDef;

typedef struct
{
  __IO uint32_t CSR_ODD;       /*!< COMP control and status register located in register of comparator instance 1, used for bits common to several COMP instances,  Address offset: 0x00 */
  __IO uint32_t FR_ODD;
  uint32_t RESERVED0[2];       /*Reserved*/
  __IO uint32_t CSR_EVEN;      /*!< COMP control and status register located in register of comparator instance 2, used for bits common to several COMP instances, Address offset: 0x010 */
  __IO uint32_t FR_EVEN;
} COMP_Common_TypeDef;



/**
* @brief OPA Registers
*/
typedef struct
{
   __IO uint32_t CSR;                             /*!<  OPA1_CSR Register,                           Address offset: 0x00  */
} OPA_TypeDef;

/**
* @brief TIM Registers
*/
typedef struct
{
   __IO uint32_t CR1;                             /*!<  TIM_CR1 Register,                            Address offset: 0x00  */
   __IO uint32_t CR2;                             /*!<  TIM_CR2 Register,                            Address offset: 0x04  */
   __IO uint32_t SMCR;                            /*!<  TIM_SMCR Register,                           Address offset: 0x08  */
   __IO uint32_t DIER;                            /*!<  TIM_DIER Register,                           Address offset: 0x0C  */
   __IO uint32_t SR;                              /*!<  TIM_SR Register,                             Address offset: 0x10  */
   __IO uint32_t EGR;                             /*!<  TIM_EGR Register,                            Address offset: 0x14  */
   __IO uint32_t CCMR1;                           /*!< TIM desc CCMR1:OUTPUT,                        Address offset: 0x18  */
   __IO uint32_t CCMR2;                           /*!< TIM desc CCMR2:OUTPUT,                        Address offset: 0x1C  */
   __IO uint32_t CCER;                            /*!<  TIM_CCER Register,                           Address offset: 0x20  */
   __IO uint32_t CNT;                             /*!<  TIM_CNT Register,                            Address offset: 0x24  */
   __IO uint32_t PSC;                             /*!<  TIM_PSC Register,                            Address offset: 0x28  */
   __IO uint32_t ARR;                             /*!<  TIM_ARR Register,                            Address offset: 0x2C  */
   __IO uint32_t RCR;                             /*!<  TIM_RCR Register,                            Address offset: 0x30  */
   __IO uint32_t CCR1;                            /*!<  TIM_CCR1 Register,                           Address offset: 0x34  */
   __IO uint32_t CCR2;                            /*!<  TIM_CCR2 Register,                           Address offset: 0x38  */
   __IO uint32_t CCR3;                            /*!<  TIM_CCR3 Register,                           Address offset: 0x3C  */
   __IO uint32_t CCR4;                            /*!<  TIM_CCR4 Register,                           Address offset: 0x40  */
   __IO uint32_t BDTR;                            /*!<  TIM_BDTR Register,                           Address offset: 0x44  */
   __IO uint32_t CCR5;                            /*!<  TIM_CCR5 Register,                           Address offset: 0x48  */
   __IO uint32_t CCR6;                            /*!<  TIM_CCR6 Register,                           Address offset: 0x4C  */
   __IO uint32_t CCMR3;                           /*!<  TIM_CCMR3 Register,                          Address offset: 0x50  */
   __IO uint32_t DTR2;                            /*!<  TIM_DTR2 Register,                           Address offset: 0x54  */
   __IO uint32_t ECR;                             /*!<  TIM_ECR Register,                            Address offset: 0x58  */
   __IO uint32_t TISEL;                           /*!<  TIM_TISEL Register,                          Address offset: 0x5C  */
   __IO uint32_t AF1;                             /*!<  TIM_AF1 Register,                            Address offset: 0x60  */
   __IO uint32_t AF2;                             /*!<  TIM_AF2 Register,                            Address offset: 0x64  */
   __IO uint32_t RESERVED1;
   __IO uint32_t MTADCCR;                         /*!<  TIM_MTADCCR Register,                        Address offset: 0x6C  */
   __IO uint32_t RESERVED2[219];                   
   __IO uint32_t DCR;                             /*!<  TIM_DCR Register,                            Address offset: 0x3DC  */
   __IO uint32_t DMAR;                            /*!<  TIM_DMAR Register,                           Address offset: 0x3E0  */
} TIM_TypeDef;

/**
* @brief EPWMC Registers
*/
typedef struct
{
   __IO uint32_t IXBSEL1_2;                       /*!< EPWMC_IXBSEL1_2 Register,                    Address offset: 0x00  */
   __IO uint32_t IXBSEL3_4;                       /*!< EPWMC_IXBSEL3_4 Register,                    Address offset: 0x04  */
   __IO uint32_t IXBSEL5_6;                       /*!< EPWMC_IXBSEL5_6 Register,                    Address offset: 0x08  */
   __IO uint32_t IXBSEL7_8;                       /*!< EPWMC_IXBSEL7_8 Register,                    Address offset: 0x0C  */
   __IO uint32_t IXBSEL9_10;                      /*!< EPWMC_IXBSEL9_10 Register,                   Address offset: 0x10  */
   __IO uint32_t IXBSEL11_12;                     /*!< EPWMC_IXBSEL11_12 Register,                  Address offset: 0x14  */
   __IO uint32_t IXBSEL13_14;                     /*!< EPWMC_IXBSEL13_14 Register,                  Address offset: 0x18  */
   __IO uint32_t IXBAQSEL;                        /*!< EPWMC_IXBAQSEL Register,                     Address offset: 0x1C  */
   __IO uint32_t IXBSEL_LOCK;                     /*!< EPWMC_IXBSEL_LOCK Register,                  Address offset: 0x20  */
   __IO uint32_t IXBCTRL;                         /*!< EPWMC_IXBCTRL Register,                      Address offset: 0x24  */
   __IO uint32_t RESERVED1[6];                     
   __IO uint32_t HXB4_0;                          /*!< EPWMC_HXB4_0 Register,                       Address offset: 0x40  */
   __IO uint32_t HXB4_1;                          /*!< EPWMC_HXB4_1 Register,                       Address offset: 0x44  */
   __IO uint32_t HXB5_0;                          /*!< EPWMC_HXB5_0 Register,                       Address offset: 0x48  */
   __IO uint32_t HXB5_1;                          /*!< EPWMC_HXB5_1 Register,                       Address offset: 0x4C  */
   __IO uint32_t HXB7_0;                          /*!< EPWMC_HXB7_0 Register,                       Address offset: 0x50  */
   __IO uint32_t HXB7_1;                          /*!< EPWMC_HXB7_1 Register,                       Address offset: 0x54  */
   __IO uint32_t HXB8_0;                          /*!< EPWMC_HXB8_0 Register,                       Address offset: 0x58  */
   __IO uint32_t HXB8_1;                          /*!< EPWMC_HXB8_1 Register,                       Address offset: 0x5C  */
   __IO uint32_t HXB9_0;                          /*!< EPWMC_HXB9_0 Register,                       Address offset: 0x60  */
   __IO uint32_t HXB9_1;                          /*!< EPWMC_HXB9_1 Register,                       Address offset: 0x64  */
   __IO uint32_t HXB10_0;                         /*!< EPWMC_HXB10_0 Register,                      Address offset: 0x68  */
   __IO uint32_t HXB10_1;                         /*!< EPWMC_HXB10_1 Register,                      Address offset: 0x6C  */
   __IO uint32_t HXB11_0;                         /*!< EPWMC_HXB11_0 Register,                      Address offset: 0x70  */
   __IO uint32_t HXB11_1;                         /*!< EPWMC_HXB11_1 Register,                      Address offset: 0x74  */
   __IO uint32_t HXB12_0;                         /*!< EPWMC_HXB12_0 Register,                      Address offset: 0x78  */
   __IO uint32_t HXB12_1;                         /*!< EPWMC_HXB12_1 Register,                      Address offset: 0x7C  */
   __IO uint32_t HXB4_MUX;                        /*!< EPWMC_HXB4_MUX Register,                     Address offset: 0x80  */
   __IO uint32_t HXB5_MUX;                        /*!< EPWMC_HXB5_MUX Register,                     Address offset: 0x84  */
   __IO uint32_t HXB7_MUX;                        /*!< EPWMC_HXB7_MUX Register,                     Address offset: 0x88  */
   __IO uint32_t HXB8_MUX;                        /*!< EPWMC_HXB8_MUX Register,                     Address offset: 0x8C  */
   __IO uint32_t HXB9_MUX;                        /*!< EPWMC_HXB9_MUX Register,                     Address offset: 0x90  */
   __IO uint32_t HXB10_MUX;                       /*!< EPWMC_HXB10_MUX Register,                    Address offset: 0x94  */
   __IO uint32_t HXB11_MUX;                       /*!< EPWMC_HXB11_MUX Register,                    Address offset: 0x98  */
   __IO uint32_t HXB12_MUX;                       /*!< EPWMC_HXB12_MUX Register,                    Address offset: 0x9C  */
   __IO uint32_t HXB_POL;                         /*!< EPWMC_HXB_POL Register,                      Address offset: 0xA0  */
   __IO uint32_t HXB_LOCK;                        /*!< EPWMC_HXB_LOCK Register,                     Address offset: 0xA4  */
   __IO uint32_t RESERVED2[6];                     
   __IO uint32_t SYNCI_SEL1_4;                    /*!< EPWMC_SYNCI_SEL1_4 Register,                 Address offset: 0xC0  */
   __IO uint32_t SYNCI_SEL5_6;                    /*!< EPWMC_SYNCI_SEL5_6 Register,                 Address offset: 0xC4  */
   __IO uint32_t SYNCO_SEL1_4;                    /*!< EPWMC_SYNCO_SEL1_4 Register,                 Address offset: 0xC8  */
   __IO uint32_t SYNCO_SEL5_6;                    /*!< EPWMC_SYNCO_SEL5_6 Register,                 Address offset: 0xCC  */
   __IO uint32_t ADCOUT;                          /*!< EPWMC_ADCOUT Register,                       Address offset: 0xD0  */
   __IO uint32_t SCOUT_CFG;                       /*!< EPWMC_SCOUT_CFG Register,                    Address offset: 0xD4  */
   __IO uint32_t SYNCSOCLOCK;                     /*!< EPWMC_SYNCSOCLOCK Register,                  Address offset: 0xD8  */
   __IO uint32_t EALLOW;                          /*!< EPWMC_EALLOW Register,                       Address offset: 0xDC  */
   __IO uint32_t CLKEN;                           /*!< EPWMC_CLKEN Register,                        Address offset: 0xE0  */
   __IO uint32_t RESERVED3[3];                     
   __IO uint32_t XBARFLG1;                        /*!< EPWMC_XBARFLG1 Register,                     Address offset: 0xF0  */
   __IO uint32_t XBARFLG2;                        /*!< EPWMC_XBARFLG2 Register,                     Address offset: 0xF4  */
   __IO uint32_t XBARCLR1;                        /*!< EPWMC_XBARCLR1 Register,                     Address offset: 0xF8  */
   __IO uint32_t XBARCLR2;                        /*!< EPWMC_XBARCLR2 Register,                     Address offset: 0xFC  */
   __IO uint32_t RESERVED4[188];                   
   __IO uint32_t FPGA_SFO_DBG;                    /*!< EPWMC_FPGA_SFO_DBG Register,                 Address offset: 0x3F0  */
} EPWMC_TypeDef;

/**
* @brief EPWM Registers
*/
typedef struct
{
   __IO uint16_t TBCTL;                           /*!< EPWM_TBCTL Register,                      Address offset: 0x00  */
   __IO uint16_t TBCTL2;                          /*!< EPWM_TBCTL2 Register,                     Address offset: 0x02  */
   __IO uint16_t RESERVED1[2];                         
   __IO uint16_t TBCTR;                           /*!< EPWM_TBCTR Register,                      Address offset: 0x08  */
   __IO uint16_t TBSTS;                           /*!< EPWM_TBSTS Register,                      Address offset: 0x0A  */
   __IO uint16_t RESERVED2[2];                         
   __IO uint16_t CMPCTL;                          /*!< EPWM_CMPCTL Register,                     Address offset: 0x10  */
   __IO uint16_t CMPCTL2;                         /*!< EPWM_CMPCTL2 Register,                    Address offset: 0x12  */
   __IO uint16_t RESERVED3[2];                         
   __IO uint16_t DBCTL;                           /*!< EPWM_DBCTL Register,                      Address offset: 0x18  */
   __IO uint16_t DBCTL2;                          /*!< EPWM_DBCTL2 Register,                     Address offset: 0x1A  */
   __IO uint16_t RESERVED4[2];                         
   __IO uint16_t AQCTL;                           /*!< EPWM_AQCTL Register,                      Address offset: 0x20  */
   __IO uint16_t AQTSRCSEL;                       /*!< EPWM_AQTSRCSEL Register,                  Address offset: 0x22  */
   __IO uint16_t RESERVED5[2];                         
   __IO uint16_t PCCTL;                           /*!< EPWM_PCCTL Register,                      Address offset: 0x28  */
   __IO uint16_t RESERVED6[3];                         
   __IO uint16_t VCAPCTL;                         /*!< EPWM_VCAPCTL Register,                    Address offset: 0x30  */
   __IO uint16_t VCNTCFG;                         /*!< EPWM_VCNTCFG Register,                    Address offset: 0x32  */
   __IO uint16_t RESERVED7[6];                         
   __IO uint16_t HRCNFG;                          /*!< EPWM_HRCNFG Register,                     Address offset: 0x40  */
   __IO uint16_t HRPWR;                           /*!< EPWM_HRPWR Register,                      Address offset: 0x42  */
   __IO uint16_t RESERVED8[4];                         
   __IO uint16_t HRMSTEP;                         /*!< EPWM_HRMSTEP Register,                    Address offset: 0x4C  */
   __IO uint16_t HRCNFG2;                         /*!< EPWM_HRCNFG2 Register,                    Address offset: 0x4E  */
   __IO uint16_t RESERVED9[5];                         
   __IO uint16_t HRPCTL;                          /*!< EPWM_HRPCTL Register,                     Address offset: 0x5A  */
   __IO uint16_t TRREM;                           /*!< EPWM_TRREM Register,                      Address offset: 0x5C  */
   __IO uint16_t RESERVED10[5];                        
   __IO uint16_t GLDCTL;                          /*!< EPWM_GLDCTL Register,                     Address offset: 0x68  */
   __IO uint16_t GLDCFG;                          /*!< EPWM_GLDCFG Register,                     Address offset: 0x6A  */
   __IO uint16_t RESERVED11[2];                        
   __IO uint32_t XLINK;                           /*!< EPWM_XLINK Register,                      Address offset: 0x70  */
   __IO uint32_t RESERVED12[3];                        
   __IO uint16_t AQCTLA;                          /*!< EPWM_AQCTLA Register,                     Address offset: 0x80  */
   __IO uint16_t AQCTLA2;                         /*!< EPWM_AQCTLA2 Register,                    Address offset: 0x82  */
   __IO uint16_t AQCTLB;                          /*!< EPWM_AQCTLB Register,                     Address offset: 0x84  */
   __IO uint16_t AQCTLB2;                         /*!< EPWM_AQCTLB2 Register,                    Address offset: 0x86  */
   __IO uint16_t RESERVED13[3];                        
   __IO uint16_t AQSFRC;                          /*!< EPWM_AQSFRC Register,                     Address offset: 0x8E  */
   __IO uint16_t RESERVED14;                           
   __IO uint16_t AQCSFRC;                         /*!< EPWM_AQCSFRC Register,                    Address offset: 0x92  */
   __IO uint16_t RESERVED15[6];                        
   __IO uint16_t DBREDHR;                         /*!< EPWM_DBREDHR Register,                    Address offset: 0xA0  */
   __IO uint16_t DBRED;                           /*!< EPWM_DBRED Register,                      Address offset: 0xA2  */
   __IO uint16_t DBFEDHR;                         /*!< EPWM_DBFEDHR Register,                    Address offset: 0xA4  */
   __IO uint16_t DBFED;                           /*!< EPWM_DBFED Register,                      Address offset: 0xA6  */
   __IO uint16_t RESERVED16[12];                       
   __IO uint32_t TBPHS;                           /*!< EPWM_TBPHS Register,                      Address offset: 0xC0  */
   __IO uint16_t TBPRDHR;                         /*!< EPWM_TBPRDHR Register,                    Address offset: 0xC4  */
   __IO uint16_t TBPRD;                           /*!< EPWM_TBPRD Register,                      Address offset: 0xC6  */
   __IO uint16_t RESERVED17[6];                        
   __IO uint32_t CMPA;                            /*!< EPWM_CMPA Register,                       Address offset: 0xD4  */
   __IO uint32_t CMPB;                            /*!< EPWM_CMPB Register,                       Address offset: 0xD8  */
   __IO uint16_t RESERVED18;                           
   __IO uint16_t CMPC;                            /*!< EPWM_CMPC Register,                       Address offset: 0xDE  */
   __IO uint16_t RESERVED19;                           
   __IO uint16_t CMPD;                            /*!< EPWM_CMPD Register,                       Address offset: 0xE2  */
   __IO uint16_t RESERVED20[2];                        
   __IO uint16_t GLDCTL2;                         /*!< EPWM_GLDCTL2 Register,                    Address offset: 0xE8  */
   __IO uint16_t RESERVED21[2];                        
   __IO uint16_t SWVDELVAL;                       /*!< EPWM_SWVDELVAL Register,                  Address offset: 0xEE  */
   __IO uint16_t RESERVED22[8];                        
   __IO uint16_t TZSEL;                           /*!< EPWM_TZSEL Register,                      Address offset: 0x100  */
   __IO uint16_t RESERVED23;                           
   __IO uint16_t TZDCSEL;                         /*!< EPWM_TZDCSEL Register,                    Address offset: 0x104  */
   __IO uint16_t RESERVED24;                           
   __IO uint16_t TZCTL;                           /*!< EPWM_TZCTL Register,                      Address offset: 0x108  */
   __IO uint16_t TZCTL2;                          /*!< EPWM_TZCTL2 Register,                     Address offset: 0x10A  */
   __IO uint16_t TZCTLDCA;                        /*!< EPWM_TZCTLDCA Register,                   Address offset: 0x10C  */
   __IO uint16_t TZCTLDCB;                        /*!< EPWM_TZCTLDCB Register,                   Address offset: 0x10E  */
   __IO uint16_t RESERVED25[5];                        
   __IO uint16_t TZEINT;                          /*!< EPWM_TZEINT Register,                     Address offset: 0x11A  */
   __IO uint16_t RESERVED26[5];                        
   __IO uint16_t TZFLG;                           /*!< EPWM_TZFLG Register,                      Address offset: 0x126  */
   __IO uint16_t TZCBCFLG;                        /*!< EPWM_TZCBCFLG Register,                   Address offset: 0x128  */
   __IO uint16_t TZOSTFLG;                        /*!< EPWM_TZOSTFLG Register,                   Address offset: 0x12A  */
   __IO uint16_t RESERVED27;                           
   __IO uint16_t TZCLR;                           /*!< EPWM_TZCLR Register,                      Address offset: 0x12E  */
   __IO uint16_t TZCBCCLR;                        /*!< EPWM_TZCBCCLR Register,                   Address offset: 0x130  */
   __IO uint16_t TZOSTCLR;                        /*!< EPWM_TZOSTCLR Register,                   Address offset: 0x132  */
   __IO uint16_t RESERVED28;                           
   __IO uint16_t TZFRC;                           /*!< EPWM_TZFRC Register,                      Address offset: 0x136  */
   __IO uint16_t RESERVED29[8];                        
   __IO uint16_t ETSEL;                           /*!< EPWM_ETSEL Register,                      Address offset: 0x148  */
   __IO uint16_t RESERVED30;                           
   __IO uint16_t ETPS;                            /*!< EPWM_ETPS Register,                       Address offset: 0x14C  */
   __IO uint16_t RESERVED31;                           
   __IO uint16_t ETFLG;                           /*!< EPWM_ETFLG Register,                      Address offset: 0x150  */
   __IO uint16_t RESERVED32;                           
   __IO uint16_t ETCLR;                           /*!< EPWM_ETCLR Register,                      Address offset: 0x154  */
   __IO uint16_t RESERVED33;                           
   __IO uint16_t ETFRC;                           /*!< EPWM_ETFRC Register,                      Address offset: 0x158  */
   __IO uint16_t RESERVED34;                           
   __IO uint16_t ETINTPS;                         /*!< EPWM_ETINTPS Register,                    Address offset: 0x15C  */
   __IO uint16_t RESERVED35;                           
   __IO uint16_t ETSOCPS;                         /*!< EPWM_ETSOCPS Register,                    Address offset: 0x160  */
   __IO uint16_t RESERVED36;                           
   __IO uint16_t ETCNTINITCTL;                    /*!< EPWM_ETCNTINITCTL Register,               Address offset: 0x164  */
   __IO uint16_t RESERVED37;                           
   __IO uint16_t ETCNTINIT;                       /*!< EPWM_ETCNTINIT Register,                  Address offset: 0x168  */
   __IO uint16_t RESERVED38[11];                       
   __IO uint16_t DCTRIPSEL;                       /*!< EPWM_DCTRIPSEL Register,                  Address offset: 0x180  */
   __IO uint16_t RESERVED39[2];                        
   __IO uint16_t DCACTL;                          /*!< EPWM_DCACTL Register,                     Address offset: 0x186  */
   __IO uint16_t DCBCTL;                          /*!< EPWM_DCBCTL Register,                     Address offset: 0x188  */
   __IO uint16_t RESERVED40[2];                        
   __IO uint16_t DCFCTL;                          /*!< EPWM_DCFCTL Register,                     Address offset: 0x18E  */
   __IO uint16_t DCCAPCTL;                        /*!< EPWM_DCCAPCTL Register,                   Address offset: 0x190  */
   __IO uint16_t DCFOFFSET;                       /*!< EPWM_DCFOFFSET Register,                  Address offset: 0x192  */
   __IO uint16_t DCFOFFSETCNT;                    /*!< EPWM_DCFOFFSETCNT Register,               Address offset: 0x194  */
   __IO uint16_t DCFWINDOW;                       /*!< EPWM_DCFWINDOW Register,                  Address offset: 0x196  */
   __IO uint16_t DCFWINDOWCNT;                    /*!< EPWM_DCFWINDOWCNT Register,               Address offset: 0x198  */
   __IO uint16_t RESERVED41[2];                        
   __IO uint16_t DCCAP;                           /*!< EPWM_DCCAP Register,                      Address offset: 0x19E  */
   __IO uint16_t RESERVED42[2];                        
   __IO uint16_t DCAHTRIPSEL;                     /*!< EPWM_DCAHTRIPSEL Register,                Address offset: 0x1A4  */
   __IO uint16_t DCALTRIPSEL;                     /*!< EPWM_DCALTRIPSEL Register,                Address offset: 0x1A6  */
   __IO uint16_t DCBHTRIPSEL;                     /*!< EPWM_DCBHTRIPSEL Register,                Address offset: 0x1A8  */
   __IO uint16_t DCBLTRIPSEL;                     /*!< EPWM_DCBLTRIPSEL Register,                Address offset: 0x1AA  */
   __IO uint16_t RESERVED43[36];                       
   __IO uint32_t EPWMLOCK;                        /*!< EPWM_EPWMLOCK Register,                   Address offset: 0x1F4  */
   __IO uint16_t RESERVED44;                           
   __IO uint16_t HWVDELVAL;                       /*!< EPWM_HWVDELVAL Register,                  Address offset: 0x1FA  */
   __IO uint16_t VCNTVAL;                         /*!< EPWM_VCNTVAL Register,                    Address offset: 0x1FC  */
} EPWM_TypeDef;

/**
* @brief LPTIM Registers
*/
typedef struct
{
   __IO uint32_t ISR;                              /*!< ISR R Register,                              Address offset: 0x00  */
   __IO uint32_t ICR;                              /*!< ICR R Register,                              Address offset: 0x04  */
   __IO uint32_t IER;                              /*!< IER R Register,                              Address offset: 0x08  */
   __IO uint32_t CFGR;                             /*!< CFGR R Register,                             Address offset: 0x0C  */
   __IO uint32_t CR;                               /*!< CR R Register,                               Address offset: 0x10  */
   __IO uint32_t CMP;                              /*!< CMP P Register,                              Address offset: 0x14  */
   __IO uint32_t ARR;                              /*!< ARR R Register,                              Address offset: 0x18  */
   __IO uint32_t CNT;                              /*!< CNT T Register,                              Address offset: 0x1C  */
   __IO uint32_t OR;                               /*!< OR R Register,                               Address offset: 0x20  */
} LPTIM_TypeDef;

/**
* @brief IWDG Registers
*/
typedef struct
{
   __IO uint16_t KR;                              /*!<  IWDG_KR Register,                            Address offset: 0x00  */
   __IO uint16_t RESERVED1;                        
   __IO uint16_t PR;                              /*!<  IWDG_PR Register,                            Address offset: 0x04  */
   __IO uint16_t RESERVED2;                        
   __IO uint16_t RLR;                             /*!<  IWDG_RLR Register,                           Address offset: 0x08  */
   __IO uint16_t RESERVED3;                        
   __IO uint16_t SR;                              /*!<  IWDG_SR Register,                            Address offset: 0x0C  */
} IWDG_TypeDef;

/**
* @brief WWDG Registers
*/
typedef struct
{
   __IO uint32_t CR;                              /*!<  WWDG_CR Register,                            Address offset: 0x00  */
   __IO uint32_t CFR;                             /*!<  WWDG_CFR Register,                           Address offset: 0x04  */
   __IO uint32_t SR;                              /*!<  WWDG_SR Register,                            Address offset: 0x08  */
} WWDG_TypeDef;

/**
* @brief SPI Registers
*/
typedef struct
{
   __IO uint32_t CR1;                             /*!<  SPI_CR1 Register,                            Address offset: 0x00  */
   __IO uint32_t CR2;                             /*!<  SPI_CR2 Register,                            Address offset: 0x04  */
   __IO uint32_t SR;                              /*!<  SPI_SR Register,                             Address offset: 0x08  */
   __IO uint32_t DR;                              /*!<  SPI_DR Register,                             Address offset: 0x0C  */
   __IO uint32_t CRCPR;                           /*!<  SPI_CRCPR Register,                          Address offset: 0x10  */
   __IO uint32_t RXCRCR;                          /*!<  SPI_RXCRCR Register,                         Address offset: 0x14  */
   __IO uint32_t TXCRCR;                          /*!<  SPI_TXCRCR Register,                         Address offset: 0x18  */
   __IO uint32_t I2S_CFGR;                        /*!<  SPI_I2S_CFGR Register,                       Address offset: 0x1C  */
   __IO uint32_t I2SPR;                           /*!<  SPI_I2SPR Register,                          Address offset: 0x20  */
} SPI_TypeDef;

/**
* @brief FDCAN Registers
*/
typedef struct
{
   __IO uint32_t CREL;                            /*!<  FDCAN_CREL Register,                         Address offset: 0x00  */
   __IO uint32_t ENDN;                            /*!<  FDCAN_ENDN Register,                         Address offset: 0x04  */
   __IO uint32_t RESERVED1;                        
   __IO uint32_t DBTP;                            /*!<  FDCAN_DBTP Register,                         Address offset: 0x0C  */
   __IO uint32_t TEST;                            /*!<  FDCAN_TEST Register,                         Address offset: 0x10  */
   __IO uint32_t RWD;                             /*!<  FDCAN_RWD Register,                          Address offset: 0x14  */
   __IO uint32_t CCCR;                            /*!<  FDCAN_CCCR Register,                         Address offset: 0x18  */
   __IO uint32_t NBTP;                            /*!<  FDCAN_NBTP Register,                         Address offset: 0x1C  */
   __IO uint32_t TSCC;                            /*!<  FDCAN_TSCC Register,                         Address offset: 0x20  */
   __IO uint32_t TSCV;                            /*!<  FDCAN_TSCV Register,                         Address offset: 0x24  */
   __IO uint32_t TOCC;                            /*!<  FDCAN_TOCC Register,                         Address offset: 0x28  */
   __IO uint32_t TOCV;                            /*!<  FDCAN_TOCV Register,                         Address offset: 0x2C  */
   __IO uint32_t RESERVED2[4];                     
   __IO uint32_t ECR;                             /*!<  FDCAN_ECR Register,                          Address offset: 0x40  */
   __IO uint32_t PSR;                             /*!<  FDCAN_PSR Register,                          Address offset: 0x44  */
   __IO uint32_t TDCR;                            /*!<  FDCAN_TDCR Register,                         Address offset: 0x48  */
   __IO uint32_t RESERVED3;                        
   __IO uint32_t IR;                              /*!<  FDCAN_IR Register,                           Address offset: 0x50  */
   __IO uint32_t IE;                              /*!<  FDCAN_IE Register,                           Address offset: 0x54  */
   __IO uint32_t ILS;                             /*!<  FDCAN_ILS Register,                          Address offset: 0x58  */
   __IO uint32_t ILE;                             /*!<  FDCAN_ILE Register,                          Address offset: 0x5C  */
   __IO uint32_t RESERVED4[8];                     
   __IO uint32_t GFC;                             /*!<  FDCAN_GFC Register,                          Address offset: 0x80  */
   __IO uint32_t SIDFC;                           /*!<  FDCAN_SIDFC Register,                        Address offset: 0x84  */
   __IO uint32_t XIDFC;                           /*!<  FDCAN_XIDFC Register,                        Address offset: 0x88  */
   __IO uint32_t RESERVED5;                        
   __IO uint32_t XIDAM;                           /*!<  FDCAN_XIDAM Register,                        Address offset: 0x90  */
   __IO uint32_t HPMS;                            /*!<  FDCAN_HPMS Register,                         Address offset: 0x94  */
   __IO uint32_t NDAT1;                           /*!<  FDCAN_NDAT1 Register,                        Address offset: 0x98  */
   __IO uint32_t NDAT2;                           /*!<  FDCAN_NDAT2 Register,                        Address offset: 0x9C  */
   __IO uint32_t RXF0C;                           /*!<  FDCAN_RXF0C Register,                        Address offset: 0xA0  */
   __IO uint32_t RXF0S;                           /*!<  FDCAN_RXF0S Register,                        Address offset: 0xA4  */
   __IO uint32_t RXF0A;                           /*!<  FDCAN_RXF0A Register,                        Address offset: 0xA8  */
   __IO uint32_t RXBC;                            /*!<  FDCAN_RXBC Register,                         Address offset: 0xAC  */
   __IO uint32_t RXF1C;                           /*!<  FDCAN_RXF1C Register,                        Address offset: 0xB0  */
   __IO uint32_t RXF1S;                           /*!<  FDCAN_RXF1S Register,                        Address offset: 0xB4  */
   __IO uint32_t RXF1A;                           /*!<  FDCAN_RXF1A Register,                        Address offset: 0xB8  */
   __IO uint32_t RXESC;                           /*!<  FDCAN_RXESC Register,                        Address offset: 0xBC  */
   __IO uint32_t TXBC;                            /*!<  FDCAN_TXBC Register,                         Address offset: 0xC0  */
   __IO uint32_t TXFQS;                           /*!<  FDCAN_TXFQS Register,                        Address offset: 0xC4  */
   __IO uint32_t TXESC;                           /*!<  FDCAN_TXESC Register,                        Address offset: 0xC8  */
   __IO uint32_t TXBRP;                           /*!<  FDCAN_TXBRP Register,                        Address offset: 0xCC  */
   __IO uint32_t TXBAR;                           /*!<  FDCAN_TXBAR Register,                        Address offset: 0xD0  */
   __IO uint32_t TXBCR;                           /*!<  FDCAN_TXBCR Register,                        Address offset: 0xD4  */
   __IO uint32_t TXBTO;                           /*!<  FDCAN_TXBTO Register,                        Address offset: 0xD8  */
   __IO uint32_t TXBCF;                           /*!<  FDCAN_TXBCF Register,                        Address offset: 0xDC  */
   __IO uint32_t TXBTIE;                          /*!<  FDCAN_TXBTIE Register,                       Address offset: 0xE0  */
   __IO uint32_t TXBCIE;                          /*!<  FDCAN_TXBCIE Register,                       Address offset: 0xE4  */
   __IO uint32_t RESERVED6[2];                     
   __IO uint32_t TXEFC;                           /*!<  FDCAN_TXEFC Register,                        Address offset: 0xF0  */
   __IO uint32_t TXEFS;                           /*!<  FDCAN_TXEFS Register,                        Address offset: 0xF4  */
   __IO uint32_t TXEFA;                           /*!<  FDCAN_TXEFA Register,                        Address offset: 0xF8  */
} FDCAN_GlobalTypeDef;

/**
* @brief I2C Registers
*/
typedef struct
{
   __IO uint32_t CR1;                             /*!<  I2C_CR1 Register,                            Address offset: 0x00  */
   __IO uint32_t CR2;                             /*!<  I2C_CR2 Register,                            Address offset: 0x04  */
   __IO uint32_t OAR1;                            /*!<  I2C_OAR1 Register,                           Address offset: 0x08  */
   __IO uint32_t OAR2;                            /*!<  I2C_OAR2 Register,                           Address offset: 0x0C  */
   __IO uint32_t DR;                              /*!<  I2C_DR Register,                             Address offset: 0x10  */
   __IO uint32_t SR1;                             /*!<  I2C_SR1 Register,                            Address offset: 0x14  */
   __IO uint32_t SR2;                             /*!<  I2C_SR2 Register,                            Address offset: 0x18  */
   __IO uint32_t CCR;                             /*!<  I2C_CCR Register,                            Address offset: 0x1C  */
   __IO uint32_t TRISE;                           /*!<  I2C_TRISE Register,                          Address offset: 0x20  */
   __IO uint32_t TIMEOUTR;                        /*!<  I2C_TIMEOUTR Register,                       Address offset: 0x24  */
   __IO uint32_t OAR3;                            /*!<  I2C_OAR3 Register,                           Address offset: 0x28  */
} I2C_TypeDef;

/**
* @brief USART Registers
*/
typedef struct
{
   __IO uint32_t SR;                              /*!<  USART_SR Register,                           Address offset: 0x00  */
   __IO uint32_t DR;                              /*!<  USART_DR Register,                           Address offset: 0x04  */
   __IO uint32_t BRR;                             /*!<  USART_BRR Register,                          Address offset: 0x08  */
   __IO uint32_t CR1;                             /*!<  USART_CR1 Register,                          Address offset: 0x0C  */
   __IO uint32_t CR2;                             /*!<  USART_CR2 Register,                          Address offset: 0x10  */
   __IO uint32_t CR3;                             /*!<  USART_CR3 Register,                          Address offset: 0x14  */
   __IO uint32_t GTPR;                            /*!<  USART_GTPR Register,                         Address offset: 0x18  */
   __IO uint32_t RTOR;                            /*!<  USART_RTOR Register,                         Address offset: 0x1C  */
} USART_TypeDef;

/**
* @brief UART Registers
*/
typedef struct
{
   __IO uint32_t DR;                              /*!<  UART_DR Register,                            Address offset: 0x00  */
   __IO uint32_t BRR;                             /*!<  UART_BRR Register,                           Address offset: 0x04  */
   __IO uint32_t RESERVED1[2];                     
   __IO uint32_t SR;                              /*!<  UART_SR Register,                            Address offset: 0x10  */
   __IO uint32_t CR1;                             /*!<  UART_CR1 Register,                           Address offset: 0x14  */
   __IO uint32_t CR2;                             /*!<  UART_CR2 Register,                           Address offset: 0x18  */
   __IO uint32_t CR3;                             /*!<  UART_CR3 Register,                           Address offset: 0x1C  */
   __IO uint32_t RAR;                             /*!<  UART_RAR Register,                           Address offset: 0x20  */
   __IO uint32_t TAR;                             /*!<  UART_TAR Register,                           Address offset: 0x24  */
   __IO uint32_t BRRF;                            /*!<  UART_BRRF Register,                          Address offset: 0x28  */
} UART_TypeDef;

/**
* @brief LPUART Registers
*/
typedef struct
{
   __IO uint32_t CR1;                             /*!<  LPUART_CR1 Register,                         Address offset: 0x00  */
   __IO uint32_t CR2;                             /*!<  LPUART_CR2 Register,                         Address offset: 0x04  */
   __IO uint32_t CR3;                             /*!<  LPUART_CR3 Register,                         Address offset: 0x08  */
   __IO uint32_t BRR;                             /*!<  LPUART_BRR Register,                         Address offset: 0x0C  */
   __IO uint32_t RESERVED1[2];                     
   __IO uint32_t RQR;                             /*!<  LPUART_RQR Register,                         Address offset: 0x18  */
   __IO uint32_t ISR;                             /*!<  LPUART_ISR Register,                         Address offset: 0x1C  */
   __IO uint32_t ICR;                             /*!<  LPUART_ICR Register,                         Address offset: 0x20  */
   __IO uint32_t RDR;                             /*!<  LPUART_RDR Register,                         Address offset: 0x24  */
   __IO uint32_t TDR;                             /*!<  LPUART_TDR Register,                         Address offset: 0x28  */
   __IO uint32_t PRESC;                           /*!<  LPUART_PRESC Register,                       Address offset: 0x2C  */
} LPUART_TypeDef;

/**
* @brief DBGMCU Registers
*/
typedef struct
{
   __IO uint32_t IDCODE;                          /*!<  DBGMCU_IDCODE Register,                      Address offset: 0x00  */
   __IO uint32_t CR1;                             /*!<  DBGMCU_CR1 Register,                         Address offset: 0x04  */
   __IO uint32_t CR2;                             /*!<  DBGMCU_CR2 Register,                         Address offset: 0x08  */
} DBGMCU_TypeDef;

/**
* @brief VREFBUF Registers
*/
typedef struct
{
   __IO uint32_t CR;                              /*!<  VREFBUF_CR Register,                         Address offset: 0x00  */
} VREFBUF_TypeDef;

/**
* @brief PWR Registers
*/
typedef struct
{
   __IO uint32_t CR1;                             /*!<  PWR_CR1 Register,                            Address offset: 0x00  */
   __IO uint32_t CR2;                             /*!<  PWR_CR2 Register,                            Address offset: 0x04  */
   __IO uint32_t CR3;                             /*!<  PWR_CR3 Register,                            Address offset: 0x08  */
   __IO uint32_t CR4;                             /*!<  PWR_CR4 Register,                            Address offset: 0x0C  */
   __IO uint32_t SR;                              /*!<  PWR_SR Register,                             Address offset: 0x10  */
   __IO uint32_t SCR;                             /*!<  PWR_SCR Register,                            Address offset: 0x14  */
} PWR_TypeDef;

/*!< Peripheral memory map */
#define FLASH_BASE            (0x08000000UL)                         /*!< FLASH base address */
#define FLASH_END             (0x0803FFFFUL)                         /*!< FLASH end address */
#define FLASH_SIZE            (FLASH_END - FLASH_BASE + 1)
#define FLASH_PAGE_SIZE       (0x00000100UL)                         /*!< FLASH Page Size, 256 Bytes */
#define FLASH_PAGE_NB         (FLASH_SIZE / FLASH_PAGE_SIZE)
#define FLASH_SECTOR_SIZE     (0x00002000UL)                         /*!< FLASH Sector Size, 8192 Bytes */
#define FLASH_SECTOR_NB       (FLASH_SIZE / FLASH_SECTOR_SIZE)
#define SRAM1_BASE            (0x20000000UL)                         /*!< SRAM1(up to 48 KB) base address */
#define PERIPH_BASE           (0x40000000UL)                         /*!< Peripheral base address */
#define OB_BASE               (0x1FFF1B00UL)                         /*!< Flash Option Bytes base address */
#define UID_BASE              (0x1FFF1A00UL)                         /*!< Unique device ID register base address */
#define OTP0_BASE             (0x1FFF1700UL)
#define OTP1_BASE             (0x1FFF1800UL)

/* Legacy defines */
#define SRAM_BASE             SRAM1_BASE

#define APB1PERIPH_BASE                         PERIPH_BASE
#define APB2PERIPH_BASE                        (PERIPH_BASE + 0x00010000UL)
#define AHBPERIPH_BASE                         (PERIPH_BASE + 0x00020000UL)

/*!< APB1 peripherals */
#define TIM2_BASE                              (0x40000000UL)
#define TIM3_BASE                              (0x40000400UL)
#define TIM6_BASE                              (0x40001000UL)
#define TIM7_BASE                              (0x40001400UL)
#define RTC_BASE                               (0x40002800UL)
#define WWDG_BASE                              (0x40002C00UL)
#define IWDG_BASE                              (0x40003000UL)
#define SPI2_BASE                              (0x40003800UL)
#define UART1_BASE                             (0x40004C00UL)
#define UART2_BASE                             (0x40005000UL)
#define I2C1_BASE                              (0x40005400UL)
#define I2C2_BASE                              (0x40005800UL)
#define PWR_BASE                               (0x40007000UL)
#define DAC_BASE                               (0x40007400UL)
#define LPTIM_BASE                             (0x40007C00UL)
#define LPUART1_BASE                           (0x40008000UL)
#define SRAMCAN_BASE                           (0x4000AC00UL)
#define FDCAN_BASE                             (0x4000CC00UL)

/*!< APB2 peripherals */
#define SYSCFG_BASE                            (0x40010000UL)
#define EXTI_BASE                              (0x40010400UL)
#define VREFBUF_BASE                           (0x40012000UL)
#define ADC1_BASE                              (0x40012400UL)
#define ADC_COMMON_BASE                        (ADC1_BASE + 0x00000304UL)
#define ADC2_BASE                              (0x40012800UL)
#define TIM1_BASE                              (0x40012C00UL)
#define SPI1_BASE                              (0x40013000UL)
#define TIM8_BASE                              (0x40013400UL)
#define USART1_BASE                            (0x40013800UL)
#define COMP1_BASE                             (0x40016C00UL)
#define COMP2_BASE                             (0x40016C10UL)
#define COMP3_BASE                             (0x40016C20UL)
#define COMP4_BASE                             (0x40016C30UL)
#define OPA_BASE                               (0x40017000UL)
#define OPA1_BASE                              (0x40017000UL)
#define OPA2_BASE                              (0x40017004UL)
#define OPA3_BASE                              (0x40017008UL)
#define OPA4_BASE                              (0x4001700CUL)
#define EPWM1_BASE                             (0x40018000UL)
#define EPWM2_BASE                             (0x40018400UL)
#define EPWM3_BASE                             (0x40018800UL)
#define EPWM4_BASE                             (0x40018C00UL)
#define EPWM5_BASE                             (0x40019000UL)
#define EPWM6_BASE                             (0x40019400UL)
#define EPWMC_BASE                             (0x40019800UL)

/*!< AHB1 peripherals */
#define DMA1_BASE                              (AHBPERIPH_BASE + 0x00000000UL)
#define RCC_BASE                               (AHBPERIPH_BASE + 0x1000)
#define FLASH_R_BASE                           (AHBPERIPH_BASE + 0x2000) /*!< Flash registers base address */
#define CRC_BASE                               (AHBPERIPH_BASE + 0x3000)
#define GPIOA_BASE                             (AHBPERIPH_BASE + 0x4000)
#define GPIOB_BASE                             (AHBPERIPH_BASE + 0x4400)
#define GPIOC_BASE                             (AHBPERIPH_BASE + 0x4800)
#define GPIOD_BASE                             (AHBPERIPH_BASE + 0x4C00)

#define DMA_Channel1_BASE                      (AHBPERIPH_BASE + 0x00000008UL)
#define DMA_Channel2_BASE                      (AHBPERIPH_BASE + 0x0000001CUL)
#define DMA_Channel3_BASE                      (AHBPERIPH_BASE + 0x00000030UL)
#define DMA_Channel4_BASE                      (AHBPERIPH_BASE + 0x00000044UL)
#define DMA_Channel5_BASE                      (AHBPERIPH_BASE + 0x00000058UL)

/* Debug MCU registers base address */
#define DBGMCU_BASE                            (0xE0042000UL)
#define DBGMCU                                 ((DBGMCU_TypeDef *) DBGMCU_BASE)
#define OB                                     ((OB_TypeDef *) OB_BASE)

/* APB1 */
#define TIM2                                   ((TIM_TypeDef *) TIM2_BASE)
#define TIM3                                   ((TIM_TypeDef *) TIM3_BASE)
#define TIM6                                   ((TIM_TypeDef *) TIM6_BASE)
#define TIM7                                   ((TIM_TypeDef *) TIM7_BASE)
#define RTC                                    ((RTC_TypeDef *) RTC_BASE)
#define WWDG                                   ((WWDG_TypeDef *) WWDG_BASE)
#define IWDG                                   ((IWDG_TypeDef *) IWDG_BASE)
#define SPI2                                   ((SPI_TypeDef *) SPI2_BASE)
#define UART1                                  ((UART_TypeDef *) UART1_BASE)
#define UART2                                  ((UART_TypeDef *) UART2_BASE)
#define I2C1                                   ((I2C_TypeDef *) I2C1_BASE)
#define I2C2                                   ((I2C_TypeDef *) I2C2_BASE)
#define PWR                                    ((PWR_TypeDef *) PWR_BASE)
#define DAC                                    ((DAC_TypeDef *) DAC_BASE)
#define LPTIM                                  ((LPTIM_TypeDef *) LPTIM_BASE)
#define LPUART1                                ((LPUART_TypeDef *) LPUART1_BASE)
#define FDCAN                                  ((FDCAN_GlobalTypeDef *) FDCAN_BASE)

/* APB2 */
#define SYSCFG                                 ((SYSCFG_TypeDef *) SYSCFG_BASE)
#define EXTI                                   ((EXTI_TypeDef *) EXTI_BASE)
#define VREFBUF                                ((VREFBUF_TypeDef *) VREFBUF_BASE)
#define ADC1                                   ((ADC_TypeDef *) ADC1_BASE)
#define ADC12_COMMON                           ((ADC_Common_TypeDef *) ADC_COMMON_BASE)
#define ADC2                                   ((ADC_TypeDef *) ADC2_BASE)
#define TIM1                                   ((TIM_TypeDef *) TIM1_BASE)
#define SPI1                                   ((SPI_TypeDef *) SPI1_BASE)
#define TIM8                                   ((TIM_TypeDef *) TIM8_BASE)
#define USART1                                 ((USART_TypeDef *) USART1_BASE)
#define COMP1                                  ((COMP_TypeDef *) COMP1_BASE)
#define COMP2                                  ((COMP_TypeDef *) COMP2_BASE)
#define COMP3                                  ((COMP_TypeDef *) COMP3_BASE)
#define COMP4                                  ((COMP_TypeDef *) COMP4_BASE)
#define COMP12_COMMON                          ((COMP_Common_TypeDef *) COMP1_BASE)
#define COMP34_COMMON                          ((COMP_Common_TypeDef *) COMP3_BASE)
#define OPA                                    ((OPA_TypeDef *) OPA_BASE)
#define OPA1                                   ((OPA_TypeDef *) OPA1_BASE)
#define OPA2                                   ((OPA_TypeDef *) OPA2_BASE)
#define OPA3                                   ((OPA_TypeDef *) OPA3_BASE)
#define OPA4                                   ((OPA_TypeDef *) OPA4_BASE)
#define EPWM1                                  ((EPWM_TypeDef *) EPWM1_BASE)
#define EPWM2                                  ((EPWM_TypeDef *) EPWM2_BASE)
#define EPWM3                                  ((EPWM_TypeDef *) EPWM3_BASE)
#define EPWM4                                  ((EPWM_TypeDef *) EPWM4_BASE)
#define EPWM5                                  ((EPWM_TypeDef *) EPWM5_BASE)
#define EPWM6                                  ((EPWM_TypeDef *) EPWM6_BASE)
#define EPWMC                                  ((EPWMC_TypeDef *) EPWMC_BASE)

/* AHB */
#define DMA                                    ((DMA_TypeDef *)DMA1_BASE)
#define DMA_Channel1                           ((DMA_Channel_TypeDef *)DMA_Channel1_BASE)
#define DMA_Channel2                           ((DMA_Channel_TypeDef *)DMA_Channel2_BASE)
#define DMA_Channel3                           ((DMA_Channel_TypeDef *)DMA_Channel3_BASE)
#define DMA_Channel4                           ((DMA_Channel_TypeDef *)DMA_Channel4_BASE)
#define DMA_Channel5                           ((DMA_Channel_TypeDef *)DMA_Channel5_BASE)
#define RCC                                    ((RCC_TypeDef *) RCC_BASE)
#define FLASH                                  ((FLASH_TypeDef *) FLASH_R_BASE)
#define CRC                                    ((CRC_TypeDef *) CRC_BASE)
#define GPIOA                                  ((GPIO_TypeDef *) GPIOA_BASE)
#define GPIOB                                  ((GPIO_TypeDef *) GPIOB_BASE)
#define GPIOC                                  ((GPIO_TypeDef *) GPIOC_BASE)
#define GPIOD                                  ((GPIO_TypeDef *) GPIOD_BASE)

/********************************************************************************************************************/
/********************************* DMA ******************************************************************************/
/********************************************************************************************************************/

/********************************* Bit definition for DMA_ISR register **********************************************/
#define DMA_ISR_TCIF1_Pos                         (0U)
#define DMA_ISR_TCIF1_Msk                         (0x1UL<<DMA_ISR_TCIF1_Pos)                        /*!< 0x00000001 */
#define DMA_ISR_TCIF1                             DMA_ISR_TCIF1_Msk                                 /*!< Transfer Complete Flag for Channel 1 */
#define DMA_ISR_BTCIF1_Pos                        (1U)
#define DMA_ISR_BTCIF1_Msk                        (0x1UL<<DMA_ISR_BTCIF1_Pos)                       /*!< 0x00000002 */
#define DMA_ISR_BTCIF1                            DMA_ISR_BTCIF1_Msk                                /*!< Block Transfer Complete Flag for Channel 1 */
#define DMA_ISR_HBTIF1_Pos                        (2U)
#define DMA_ISR_HBTIF1_Msk                        (0x1UL<<DMA_ISR_HBTIF1_Pos)                       /*!< 0x00000004 */
#define DMA_ISR_HBTIF1                            DMA_ISR_HBTIF1_Msk                                /*!< Half Block Transfer Complete Flag for Channel 1 */
#define DMA_ISR_TEIF1_Pos                         (3U)
#define DMA_ISR_TEIF1_Msk                         (0x1UL<<DMA_ISR_TEIF1_Pos)                        /*!< 0x00000008 */
#define DMA_ISR_TEIF1                             DMA_ISR_TEIF1_Msk                                 /*!< Transfer Error Flag for Channel 1 */
#define DMA_ISR_TCIF2_Pos                         (4U)
#define DMA_ISR_TCIF2_Msk                         (0x1UL<<DMA_ISR_TCIF2_Pos)                        /*!< 0x00000010 */
#define DMA_ISR_TCIF2                             DMA_ISR_TCIF2_Msk                                 /*!< Transfer Complete Flag for Channel 2 */
#define DMA_ISR_BTCIF2_Pos                        (5U)
#define DMA_ISR_BTCIF2_Msk                        (0x1UL<<DMA_ISR_BTCIF2_Pos)                       /*!< 0x00000020 */
#define DMA_ISR_BTCIF2                            DMA_ISR_BTCIF2_Msk                                /*!< Block Transfer Complete Flag for Channel 2 */
#define DMA_ISR_HBTIF2_Pos                        (6U)
#define DMA_ISR_HBTIF2_Msk                        (0x1UL<<DMA_ISR_HBTIF2_Pos)                       /*!< 0x00000040 */
#define DMA_ISR_HBTIF2                            DMA_ISR_HBTIF2_Msk                                /*!< Half Block Transfer Complete Flag for Channel 2 */
#define DMA_ISR_TEIF2_Pos                         (7U)
#define DMA_ISR_TEIF2_Msk                         (0x1UL<<DMA_ISR_TEIF2_Pos)                        /*!< 0x00000080 */
#define DMA_ISR_TEIF2                             DMA_ISR_TEIF2_Msk                                 /*!< Transfer Error Flag for Channel 2 */
#define DMA_ISR_TCIF3_Pos                         (8U)
#define DMA_ISR_TCIF3_Msk                         (0x1UL<<DMA_ISR_TCIF3_Pos)                        /*!< 0x00000100 */
#define DMA_ISR_TCIF3                             DMA_ISR_TCIF3_Msk                                 /*!< Transfer Complete Flag for Channel 3 */
#define DMA_ISR_BTCIF3_Pos                        (9U)
#define DMA_ISR_BTCIF3_Msk                        (0x1UL<<DMA_ISR_BTCIF3_Pos)                       /*!< 0x00000200 */
#define DMA_ISR_BTCIF3                            DMA_ISR_BTCIF3_Msk                                /*!< Block Transfer Complete Flag for Channel 3 */
#define DMA_ISR_HBTIF3_Pos                        (10U)
#define DMA_ISR_HBTIF3_Msk                        (0x1UL<<DMA_ISR_HBTIF3_Pos)                       /*!< 0x00000400 */
#define DMA_ISR_HBTIF3                            DMA_ISR_HBTIF3_Msk                                /*!< Half Block Transfer Complete Flag for Channel 3 */
#define DMA_ISR_TEIF3_Pos                         (11U)
#define DMA_ISR_TEIF3_Msk                         (0x1UL<<DMA_ISR_TEIF3_Pos)                        /*!< 0x00000800 */
#define DMA_ISR_TEIF3                             DMA_ISR_TEIF3_Msk                                 /*!< Transfer Error Flag for Channel 3 */
#define DMA_ISR_TCIF4_Pos                         (12U)
#define DMA_ISR_TCIF4_Msk                         (0x1UL<<DMA_ISR_TCIF4_Pos)                        /*!< 0x00001000 */
#define DMA_ISR_TCIF4                             DMA_ISR_TCIF4_Msk                                 /*!< Transfer Complete Flag for Channel 4 */
#define DMA_ISR_BTCIF4_Pos                        (13U)
#define DMA_ISR_BTCIF4_Msk                        (0x1UL<<DMA_ISR_BTCIF4_Pos)                       /*!< 0x00002000 */
#define DMA_ISR_BTCIF4                            DMA_ISR_BTCIF4_Msk                                /*!< Block Transfer Complete Flag for Channel 4 */
#define DMA_ISR_HBTIF4_Pos                        (14U)
#define DMA_ISR_HBTIF4_Msk                        (0x1UL<<DMA_ISR_HBTIF4_Pos)                       /*!< 0x00004000 */
#define DMA_ISR_HBTIF4                            DMA_ISR_HBTIF4_Msk                                /*!< Half Block Transfer Complete Flag for Channel 4 */
#define DMA_ISR_TEIF4_Pos                         (15U)
#define DMA_ISR_TEIF4_Msk                         (0x1UL<<DMA_ISR_TEIF4_Pos)                        /*!< 0x00008000 */
#define DMA_ISR_TEIF4                             DMA_ISR_TEIF4_Msk                                 /*!< Transfer Error Flag for Channel 4 */
#define DMA_ISR_TCIF5_Pos                         (16U)
#define DMA_ISR_TCIF5_Msk                         (0x1UL<<DMA_ISR_TCIF5_Pos)                        /*!< 0x00010000 */
#define DMA_ISR_TCIF5                             DMA_ISR_TCIF5_Msk                                 /*!< Transfer Complete Flag for Channel 5 */
#define DMA_ISR_BTCIF5_Pos                        (17U)
#define DMA_ISR_BTCIF5_Msk                        (0x1UL<<DMA_ISR_BTCIF5_Pos)                       /*!< 0x00020000 */
#define DMA_ISR_BTCIF5                            DMA_ISR_BTCIF5_Msk                                /*!< Block Transfer Complete Flag for Channel 5 */
#define DMA_ISR_HBTIF5_Pos                        (18U)
#define DMA_ISR_HBTIF5_Msk                        (0x1UL<<DMA_ISR_HBTIF5_Pos)                       /*!< 0x00040000 */
#define DMA_ISR_HBTIF5                            DMA_ISR_HBTIF5_Msk                                /*!< Half Block Transfer Complete Flag for Channel 5 */
#define DMA_ISR_TEIF5_Pos                         (19U)
#define DMA_ISR_TEIF5_Msk                         (0x1UL<<DMA_ISR_TEIF5_Pos)                        /*!< 0x00080000 */
#define DMA_ISR_TEIF5                             DMA_ISR_TEIF5_Msk                                 /*!< Transfer Error Flag for Channel 5 */

/********************************* Bit definition for DMA_IFCR register *********************************************/
#define DMA_IFCR_CTCIF1_Pos                       (0U)
#define DMA_IFCR_CTCIF1_Msk                       (0x1UL<<DMA_IFCR_CTCIF1_Pos)                      /*!< 0x00000001 */
#define DMA_IFCR_CTCIF1                           DMA_IFCR_CTCIF1_Msk                               /*!< Transfer Complete Flag Clear for Channel 1 */
#define DMA_IFCR_CBTCIF1_Pos                      (1U)
#define DMA_IFCR_CBTCIF1_Msk                      (0x1UL<<DMA_IFCR_CBTCIF1_Pos)                     /*!< 0x00000002 */
#define DMA_IFCR_CBTCIF1                          DMA_IFCR_CBTCIF1_Msk                              /*!< Block Transfer Complete Flag Clear for Channel 1 */
#define DMA_IFCR_CHBTIF1_Pos                      (2U)
#define DMA_IFCR_CHBTIF1_Msk                      (0x1UL<<DMA_IFCR_CHBTIF1_Pos)                     /*!< 0x00000004 */
#define DMA_IFCR_CHBTIF1                          DMA_IFCR_CHBTIF1_Msk                              /*!< Half Block Transfer Complete Flag Clear for Channel 1 */
#define DMA_IFCR_CTEIF1_Pos                       (3U)
#define DMA_IFCR_CTEIF1_Msk                       (0x1UL<<DMA_IFCR_CTEIF1_Pos)                      /*!< 0x00000008 */
#define DMA_IFCR_CTEIF1                           DMA_IFCR_CTEIF1_Msk                               /*!< Transfer Error Flag Clear for Channel 1 */
#define DMA_IFCR_CTCIF2_Pos                       (4U)
#define DMA_IFCR_CTCIF2_Msk                       (0x1UL<<DMA_IFCR_CTCIF2_Pos)                      /*!< 0x00000010 */
#define DMA_IFCR_CTCIF2                           DMA_IFCR_CTCIF2_Msk                               /*!< Transfer Complete Flag Clear for Channel 2 */
#define DMA_IFCR_CBTCIF2_Pos                      (5U)
#define DMA_IFCR_CBTCIF2_Msk                      (0x1UL<<DMA_IFCR_CBTCIF2_Pos)                     /*!< 0x00000020 */
#define DMA_IFCR_CBTCIF2                          DMA_IFCR_CBTCIF2_Msk                              /*!< Block Transfer Complete Flag Clear for Channel 2 */
#define DMA_IFCR_CHBTIF2_Pos                      (6U)
#define DMA_IFCR_CHBTIF2_Msk                      (0x1UL<<DMA_IFCR_CHBTIF2_Pos)                     /*!< 0x00000040 */
#define DMA_IFCR_CHBTIF2                          DMA_IFCR_CHBTIF2_Msk                              /*!< Half Block Transfer Complete Flag Clear for Channel 2 */
#define DMA_IFCR_CTEIF2_Pos                       (7U)
#define DMA_IFCR_CTEIF2_Msk                       (0x1UL<<DMA_IFCR_CTEIF2_Pos)                      /*!< 0x00000080 */
#define DMA_IFCR_CTEIF2                           DMA_IFCR_CTEIF2_Msk                               /*!< Transfer Error Flag Clear for Channel 2 */
#define DMA_IFCR_CTCIF3_Pos                       (8U)
#define DMA_IFCR_CTCIF3_Msk                       (0x1UL<<DMA_IFCR_CTCIF3_Pos)                      /*!< 0x00000100 */
#define DMA_IFCR_CTCIF3                           DMA_IFCR_CTCIF3_Msk                               /*!< Transfer Complete Flag Clear for Channel 3 */
#define DMA_IFCR_CBTCIF3_Pos                      (9U)
#define DMA_IFCR_CBTCIF3_Msk                      (0x1UL<<DMA_IFCR_CBTCIF3_Pos)                     /*!< 0x00000200 */
#define DMA_IFCR_CBTCIF3                          DMA_IFCR_CBTCIF3_Msk                              /*!< Block Transfer Complete Flag Clear for Channel 3 */
#define DMA_IFCR_CHBTIF3_Pos                      (10U)
#define DMA_IFCR_CHBTIF3_Msk                      (0x1UL<<DMA_IFCR_CHBTIF3_Pos)                     /*!< 0x00000400 */
#define DMA_IFCR_CHBTIF3                          DMA_IFCR_CHBTIF3_Msk                              /*!< Half Block Transfer Complete Flag Clear for Channel 3 */
#define DMA_IFCR_CTEIF3_Pos                       (11U)
#define DMA_IFCR_CTEIF3_Msk                       (0x1UL<<DMA_IFCR_CTEIF3_Pos)                      /*!< 0x00000800 */
#define DMA_IFCR_CTEIF3                           DMA_IFCR_CTEIF3_Msk                               /*!< Transfer Error Flag Clear for Channel 3 */
#define DMA_IFCR_CTCIF4_Pos                       (12U)
#define DMA_IFCR_CTCIF4_Msk                       (0x1UL<<DMA_IFCR_CTCIF4_Pos)                      /*!< 0x00001000 */
#define DMA_IFCR_CTCIF4                           DMA_IFCR_CTCIF4_Msk                               /*!< Transfer Complete Flag Clear for Channel 4 */
#define DMA_IFCR_CBTCIF4_Pos                      (13U)
#define DMA_IFCR_CBTCIF4_Msk                      (0x1UL<<DMA_IFCR_CBTCIF4_Pos)                     /*!< 0x00002000 */
#define DMA_IFCR_CBTCIF4                          DMA_IFCR_CBTCIF4_Msk                              /*!< Block Transfer Complete Flag Clear for Channel 4 */
#define DMA_IFCR_CHBTIF4_Pos                      (14U)
#define DMA_IFCR_CHBTIF4_Msk                      (0x1UL<<DMA_IFCR_CHBTIF4_Pos)                     /*!< 0x00004000 */
#define DMA_IFCR_CHBTIF4                          DMA_IFCR_CHBTIF4_Msk                              /*!< Half Block Transfer Complete Flag Clear for Channel 4 */
#define DMA_IFCR_CTEIF4_Pos                       (15U)
#define DMA_IFCR_CTEIF4_Msk                       (0x1UL<<DMA_IFCR_CTEIF4_Pos)                      /*!< 0x00008000 */
#define DMA_IFCR_CTEIF4                           DMA_IFCR_CTEIF4_Msk                               /*!< Transfer Error Flag Clear for Channel 4 */
#define DMA_IFCR_CTCIF5_Pos                       (16U)
#define DMA_IFCR_CTCIF5_Msk                       (0x1UL<<DMA_IFCR_CTCIF5_Pos)                      /*!< 0x00010000 */
#define DMA_IFCR_CTCIF5                           DMA_IFCR_CTCIF5_Msk                               /*!< Transfer Complete Flag Clear for Channel 5 */
#define DMA_IFCR_CBTCIF5_Pos                      (17U)
#define DMA_IFCR_CBTCIF5_Msk                      (0x1UL<<DMA_IFCR_CBTCIF5_Pos)                     /*!< 0x00020000 */
#define DMA_IFCR_CBTCIF5                          DMA_IFCR_CBTCIF5_Msk                              /*!< Block Transfer Complete Flag Clear for Channel 5 */
#define DMA_IFCR_CHBTIF5_Pos                      (18U)
#define DMA_IFCR_CHBTIF5_Msk                      (0x1UL<<DMA_IFCR_CHBTIF5_Pos)                     /*!< 0x00040000 */
#define DMA_IFCR_CHBTIF5                          DMA_IFCR_CHBTIF5_Msk                              /*!< Half Block Transfer Complete Flag Clear for Channel 5 */
#define DMA_IFCR_CTEIF5_Pos                       (19U)
#define DMA_IFCR_CTEIF5_Msk                       (0x1UL<<DMA_IFCR_CTEIF5_Pos)                      /*!< 0x00080000 */
#define DMA_IFCR_CTEIF5                           DMA_IFCR_CTEIF5_Msk                               /*!< Transfer Error Flag Clear for Channel 5 */

/********************************* Bit definition for DMA_CCR register *********************************************/
#define DMA_CCR_EN_Pos                           (0U)
#define DMA_CCR_EN_Msk                           (0x1UL<<DMA_CCR_EN_Pos)                          /*!< 0x00000001 */
#define DMA_CCR_EN                               DMA_CCR_EN_Msk                                   /*!< Channel Enable */
#define DMA_CCR_TCIE_Pos                         (1U)
#define DMA_CCR_TCIE_Msk                         (0x1UL<<DMA_CCR_TCIE_Pos)                        /*!< 0x00000002 */
#define DMA_CCR_TCIE                             DMA_CCR_TCIE_Msk                                 /*!< Transfer Complete Interrupt Enable */
#define DMA_CCR_BTCIE_Pos                        (2U)
#define DMA_CCR_BTCIE_Msk                        (0x1UL<<DMA_CCR_BTCIE_Pos)                       /*!< 0x00000004 */
#define DMA_CCR_BTCIE                            DMA_CCR_BTCIE_Msk                                /*!< Block Transfer Complete Interrupt Enable */
#define DMA_CCR_HBTIE_Pos                        (3U)
#define DMA_CCR_HBTIE_Msk                        (0x1UL<<DMA_CCR_HBTIE_Pos)                       /*!< 0x00000008 */
#define DMA_CCR_HBTIE                            DMA_CCR_HBTIE_Msk                                /*!< Half Block Transfer Complete Interrupt Enable */
#define DMA_CCR_TEIE_Pos                         (4U)
#define DMA_CCR_TEIE_Msk                         (0x1UL<<DMA_CCR_TEIE_Pos)                        /*!< 0x00000010 */
#define DMA_CCR_TEIE                             DMA_CCR_TEIE_Msk                                 /*!< Transfer Error Interrupt Enable */
#define DMA_CCR_DIR_Pos                          (5U)
#define DMA_CCR_DIR_Msk                          (0x1UL<<DMA_CCR_DIR_Pos)                         /*!< 0x00000020 */
#define DMA_CCR_DIR                              DMA_CCR_DIR_Msk                                  /*!< Data Transfer Direction */
#define DMA_CCR_CIRC_Pos                         (6U)
#define DMA_CCR_CIRC_Msk                         (0x1UL<<DMA_CCR_CIRC_Pos)                        /*!< 0x00000040 */
#define DMA_CCR_CIRC                             DMA_CCR_CIRC_Msk                                 /*!< Circular Mode */
#define DMA_CCR_TRANST_Pos                       (7U)
#define DMA_CCR_TRANST_Msk                       (0x1UL<<DMA_CCR_TRANST_Pos)                      /*!< 0x00000080 */
#define DMA_CCR_TRANST                           DMA_CCR_TRANST_Msk                               /*!< Transfer Type */
#define DMA_CCR_PINC_Pos                         (8U)
#define DMA_CCR_PINC_Msk                         (0x3UL<<DMA_CCR_PINC_Pos)                        /*!< 0x00000300 */
#define DMA_CCR_PINC                             DMA_CCR_PINC_Msk                                 /*!< Peripheral Increment Mode */
#define DMA_CCR_PINC_0                           (0x1UL<<DMA_CCR_PINC_Pos)                        /*!< 0x00000100 */
#define DMA_CCR_PINC_1                           (0x2UL<<DMA_CCR_PINC_Pos)                        /*!< 0x00000200 */
#define DMA_CCR_MINC_Pos                         (10U)
#define DMA_CCR_MINC_Msk                         (0x3UL<<DMA_CCR_MINC_Pos)                        /*!< 0x00000C00 */
#define DMA_CCR_MINC                             DMA_CCR_MINC_Msk                                 /*!< Memory Increment Mode */
#define DMA_CCR_MINC_0                           (0x1UL<<DMA_CCR_MINC_Pos)                        /*!< 0x00000400 */
#define DMA_CCR_MINC_1                           (0x2UL<<DMA_CCR_MINC_Pos)                        /*!< 0x00000800 */
#define DMA_CCR_PSIZE_Pos                        (12U)
#define DMA_CCR_PSIZE_Msk                        (0x3UL<<DMA_CCR_PSIZE_Pos)                       /*!< 0x00003000 */
#define DMA_CCR_PSIZE                            DMA_CCR_PSIZE_Msk                                /*!< Peripheral Size */
#define DMA_CCR_PSIZE_0                          (0x1UL<<DMA_CCR_PSIZE_Pos)                       /*!< 0x00001000 */
#define DMA_CCR_PSIZE_1                          (0x2UL<<DMA_CCR_PSIZE_Pos)                       /*!< 0x00002000 */
#define DMA_CCR_MSIZE_Pos                        (14U)
#define DMA_CCR_MSIZE_Msk                        (0x3UL<<DMA_CCR_MSIZE_Pos)                       /*!< 0x0000C000 */
#define DMA_CCR_MSIZE                            DMA_CCR_MSIZE_Msk                                /*!< Memory Size */
#define DMA_CCR_MSIZE_0                          (0x1UL<<DMA_CCR_MSIZE_Pos)                       /*!< 0x00004000 */
#define DMA_CCR_MSIZE_1                          (0x2UL<<DMA_CCR_MSIZE_Pos)                       /*!< 0x00008000 */
#define DMA_CCR_PL_Pos                           (16U)
#define DMA_CCR_PL_Msk                           (0x7UL<<DMA_CCR_PL_Pos)                          /*!< 0x00070000 */
#define DMA_CCR_PL                               DMA_CCR_PL_Msk                                   /*!< Priority Level */
#define DMA_CCR_PL_0                             (0x1UL<<DMA_CCR_PL_Pos)                          /*!< 0x00010000 */
#define DMA_CCR_PL_1                             (0x2UL<<DMA_CCR_PL_Pos)                          /*!< 0x00020000 */
#define DMA_CCR_PL_2                             (0x4UL<<DMA_CCR_PL_Pos)                          /*!< 0x00040000 */
#define DMA_CCR_MEM2MEM_Pos                      (19U)
#define DMA_CCR_MEM2MEM_Msk                      (0x1UL<<DMA_CCR_MEM2MEM_Pos)                     /*!< 0x00080000 */
#define DMA_CCR_MEM2MEM                          DMA_CCR_MEM2MEM_Msk                              /*!< Memory-to-memory Mode */
#define DMA_CCR_PNORLD_Pos                       (20U)
#define DMA_CCR_PNORLD_Msk                       (0x1UL<<DMA_CCR_PNORLD_Pos)                      /*!< 0x00100000 */
#define DMA_CCR_PNORLD                           DMA_CCR_PNORLD_Msk                               /*!< Peripheral No Reload */
#define DMA_CCR_MNORLD_Pos                       (21U)
#define DMA_CCR_MNORLD_Msk                       (0x1UL<<DMA_CCR_MNORLD_Pos)                      /*!< 0x00200000 */
#define DMA_CCR_MNORLD                           DMA_CCR_MNORLD_Msk                               /*!< Memory No Reload */
#define DMA_CCR_BTCSUSP_Pos                      (22U)
#define DMA_CCR_BTCSUSP_Msk                      (0x1UL<<DMA_CCR_BTCSUSP_Pos)                     /*!< 0x00400000 */
#define DMA_CCR_BTCSUSP                          DMA_CCR_BTCSUSP_Msk                              /*!< Suspend in Block Transfer Complete Interrupt */
#define DMA_CCR_M2MARB_Pos                       (23U)
#define DMA_CCR_M2MARB_Msk                       (0x1UL<<DMA_CCR_M2MARB_Pos)                      /*!< 0x00800000 */
#define DMA_CCR_M2MARB                           DMA_CCR_M2MARB_Msk                               /*!< Memory-to-memory Mode Arbitration */

/********************************* Bit definition for DMA_CNDTR register *******************************************/
#define DMA_CNDTR_NDT_Pos                        (0U)
#define DMA_CNDTR_NDT_Msk                        (0xFFFFUL<<DMA_CNDTR_NDT_Pos)                    /*!< 0x0000FFFF */
#define DMA_CNDTR_NDT                            DMA_CNDTR_NDT_Msk                                /*!< Number of Data to Transfer */

/********************************* Bit definition for DMA_CPAR register ********************************************/
#define DMA_CPAR_PA_Pos                          (0U)
#define DMA_CPAR_PA_Msk                          (0xFFFFFFFFUL<<DMA_CPAR_PA_Pos)                  /*!< 0xFFFFFFFF */
#define DMA_CPAR_PA                              DMA_CPAR_PA_Msk                                  /*!< Peripheral Address */

/********************************* Bit definition for DMA_CMAR register ********************************************/
#define DMA_CMAR_MA_Pos                          (0U)
#define DMA_CMAR_MA_Msk                          (0xFFFFFFFFUL<<DMA_CMAR_MA_Pos)                  /*!< 0xFFFFFFFF */
#define DMA_CMAR_MA                              DMA_CMAR_MA_Msk                                  /*!< Memory Address */

/********************************* Bit definition for DMA_CCCFGR register ******************************************/
#define DMA_CNBTR_NBT_Pos                        (0U)
#define DMA_CNBTR_NBT_Msk                        (0xFFUL<<DMA_CNBTR_NBT_Pos)                      /*!< 0x000000FF */
#define DMA_CNBTR_NBT                            DMA_CNBTR_NBT_Msk                                /*!< Number of Block to Loop Transfer */
#define DMA_CNBTR_NDTL_Pos                       (16U)
#define DMA_CNBTR_NDTL_Msk                       (0xFFFFUL<<DMA_CNBTR_NDTL_Pos)                   /*!< 0xFFFF0000 */
#define DMA_CNBTR_NDTL                           DMA_CNBTR_NDTL_Msk                               /*!< Number of Data to Transfer Last Loop */

/********************************************************************************************************************/
/********************************* FLASH ****************************************************************************/
/********************************************************************************************************************/

/********************************* Bit definition for FLASH_ACR register ********************************************/
#define FLASH_ACR_LATENCY_Pos                     (0U)
#define FLASH_ACR_LATENCY_Msk                     (0xFUL<<FLASH_ACR_LATENCY_Pos)                    /*!< 0x0000000F */
#define FLASH_ACR_LATENCY                         FLASH_ACR_LATENCY_Msk                             /*!< Latency */
#define FLASH_ACR_LATENCY_0                       (0x1UL<<FLASH_ACR_LATENCY_Pos)                    /*!< 0x00000001 */
#define FLASH_ACR_LATENCY_1                       (0x2UL<<FLASH_ACR_LATENCY_Pos)                    /*!< 0x00000002 */
#define FLASH_ACR_LATENCY_2                       (0x4UL<<FLASH_ACR_LATENCY_Pos)                    /*!< 0x00000004 */
#define FLASH_ACR_LATENCY_3                       (0x8UL<<FLASH_ACR_LATENCY_Pos)                    /*!< 0x00000008 */
#define FLASH_ACR_PRFTEN_Pos                      (8U)
#define FLASH_ACR_PRFTEN_Msk                      (0x1UL<<FLASH_ACR_PRFTEN_Pos)                     /*!< 0x00000100 */
#define FLASH_ACR_PRFTEN                          FLASH_ACR_PRFTEN_Msk                              
#define FLASH_ACR_ICEN_Pos                        (9U)
#define FLASH_ACR_ICEN_Msk                        (0x1UL<<FLASH_ACR_ICEN_Pos)                       /*!< 0x00000200 */
#define FLASH_ACR_ICEN                            FLASH_ACR_ICEN_Msk                                
#define FLASH_ACR_DCEN_Pos                        (10U)
#define FLASH_ACR_DCEN_Msk                        (0x1UL<<FLASH_ACR_DCEN_Pos)                       /*!< 0x00000400 */
#define FLASH_ACR_DCEN                            FLASH_ACR_DCEN_Msk                                

/********************************* Bit definition for FLASH_KEYR register *******************************************/
#define FLASH_KEYR_KEY_Pos                        (0U)
#define FLASH_KEYR_KEY_Msk                        (0xFFFFFFFFUL<<FLASH_KEYR_KEY_Pos)                /*!< 0xFFFFFFFF */
#define FLASH_KEYR_KEY                            FLASH_KEYR_KEY_Msk                                /*!< Flash CR key */

/********************************* Bit definition for FLASH_OPTKEYR register ****************************************/
#define FLASH_OPTKEYR_OPTKEY_Pos                  (0U)
#define FLASH_OPTKEYR_OPTKEY_Msk                  (0xFFFFFFFFUL<<FLASH_OPTKEYR_OPTKEY_Pos)          /*!< 0xFFFFFFFF */
#define FLASH_OPTKEYR_OPTKEY                      FLASH_OPTKEYR_OPTKEY_Msk                          /*!< Flash Option key */

#define FLASH_KEY1_Pos                            (0U)
#define FLASH_KEY1_Msk                            (0x45670123UL << FLASH_KEY1_Pos)                  /*!< 0x45670123 */
#define FLASH_KEY1                                FLASH_KEY1_Msk                                    /*!< Flash program erase key1 */
#define FLASH_KEY2_Pos                            (0U)
#define FLASH_KEY2_Msk                            (0xCDEF89ABUL << FLASH_KEY2_Pos)                  /*!< 0xCDEF89AB */
#define FLASH_KEY2                                FLASH_KEY2_Msk                                    /*!< Flash program erase key2: used with FLASH_PEKEY1 to unlock the write access to the FPEC. */

#define FLASH_OPTKEY1_Pos                         (0U)
#define FLASH_OPTKEY1_Msk                         (0x08192A3BUL << FLASH_OPTKEY1_Pos)               /*!< 0x08192A3B */
#define FLASH_OPTKEY1                             FLASH_OPTKEY1_Msk                                 /*!< Flash option key1 */
#define FLASH_OPTKEY2_Pos                         (0U)
#define FLASH_OPTKEY2_Msk                         (0x4C5D6E7FUL << FLASH_OPTKEY2_Pos)               /*!< 0x4C5D6E7F */
#define FLASH_OPTKEY2                             FLASH_OPTKEY2_Msk                                 /*!< Flash option key2: used with FLASH_OPTKEY1 to unlock the write access to the option byte block */

/********************************* Bit definition for FLASH_SR register *********************************************/
#define FLASH_SR_EOP_Pos                          (0U)
#define FLASH_SR_EOP_Msk                          (0x1UL<<FLASH_SR_EOP_Pos)                         /*!< 0x00000001 */
#define FLASH_SR_EOP                              FLASH_SR_EOP_Msk                                  /*!< End of operation */
#define FLASH_SR_WRPERR_Pos                       (4U)
#define FLASH_SR_WRPERR_Msk                       (0x1UL<<FLASH_SR_WRPERR_Pos)                      /*!< 0x00000010 */
#define FLASH_SR_WRPERR                           FLASH_SR_WRPERR_Msk                               /*!< Write protection error */
#define FLASH_SR_RDERR_Pos                        (11U)
#define FLASH_SR_RDERR_Msk                        (0x1UL<<FLASH_SR_RDERR_Pos)                       /*!< 0x00000800 */
#define FLASH_SR_RDERR                            FLASH_SR_RDERR_Msk                                /*!< bank0 read error */
#define FLASH_SR_VRPRGERR_Pos                     (12U)
#define FLASH_SR_VRPRGERR_Msk                     (0x1UL<<FLASH_SR_VRPRGERR_Pos)                    /*!< 0x00001000 */
#define FLASH_SR_VRPRGERR                         FLASH_SR_VRPRGERR_Msk                             
#define FLASH_SR_VRERSERR_Pos                     (13U)
#define FLASH_SR_VRERSERR_Msk                     (0x1UL<<FLASH_SR_VRERSERR_Pos)                    /*!< 0x00002000 */
#define FLASH_SR_VRERSERR                         FLASH_SR_VRERSERR_Msk                             
#define FLASH_SR_OPTWERR_Pos                      (14U)
#define FLASH_SR_OPTWERR_Msk                      (0x1UL<<FLASH_SR_OPTWERR_Pos)                     /*!< 0x00004000 */
#define FLASH_SR_OPTWERR                          FLASH_SR_OPTWERR_Msk                              
#define FLASH_SR_OPTVERR_Pos                      (15U)
#define FLASH_SR_OPTVERR_Msk                      (0x1UL<<FLASH_SR_OPTVERR_Pos)                     /*!< 0x00008000 */
#define FLASH_SR_OPTVERR                          FLASH_SR_OPTVERR_Msk                              /*!< Option and trimming bits loading validity error */
#define FLASH_SR_BSY0_Pos                         (16U)
#define FLASH_SR_BSY0_Msk                         (0x1UL<<FLASH_SR_BSY0_Pos)                        /*!< 0x00010000 */
#define FLASH_SR_BSY0                             FLASH_SR_BSY0_Msk                                 /*!< Bank0 Busy */
#define FLASH_SR_BSY1_Pos                         (17U)
#define FLASH_SR_BSY1_Msk                         (0x1UL<<FLASH_SR_BSY1_Pos)                        /*!< 0x00020000 */
#define FLASH_SR_BSY1                             FLASH_SR_BSY1_Msk                                 /*!< Bank1 Busy */
#define FLASH_SR_USRLOCK0_Pos                     (30U)
#define FLASH_SR_USRLOCK0_Msk                     (0x1UL<<FLASH_SR_USRLOCK0_Pos)                    /*!< 0x40000000 */
#define FLASH_SR_USRLOCK0                         FLASH_SR_USRLOCK0_Msk                             /*!< Userdata Lock  */
#define FLASH_SR_USRLOCK1_Pos                     (31U)
#define FLASH_SR_USRLOCK1_Msk                     (0x1UL<<FLASH_SR_USRLOCK1_Pos)                    /*!< 0x80000000 */
#define FLASH_SR_USRLOCK1                         FLASH_SR_USRLOCK1_Msk                             /*!< Userdata Lock  */

/********************************* Bit definition for FLASH_CR register *********************************************/
#define FLASH_CR_PG_Pos                           (0U)
#define FLASH_CR_PG_Msk                           (0x1UL<<FLASH_CR_PG_Pos)                          /*!< 0x00000001 */
#define FLASH_CR_PG                               FLASH_CR_PG_Msk                                   /*!< Page Program */
#define FLASH_CR_PER_Pos                          (1U)
#define FLASH_CR_PER_Msk                          (0x1UL<<FLASH_CR_PER_Pos)                         /*!< 0x00000002 */
#define FLASH_CR_PER                              FLASH_CR_PER_Msk                                  /*!< Page Erase */
#define FLASH_CR_MER_Pos                          (2U)
#define FLASH_CR_MER_Msk                          (0x1UL<<FLASH_CR_MER_Pos)                         /*!< 0x00000004 */
#define FLASH_CR_MER                              FLASH_CR_MER_Msk                                  /*!< Bank 0 Mass Erase */
#define FLASH_CR_UPG_Pos                          (4U)
#define FLASH_CR_UPG_Msk                          (0x1UL<<FLASH_CR_UPG_Pos)                         /*!< 0x00000010 */
#define FLASH_CR_UPG                              FLASH_CR_UPG_Msk                                  /*!< User data区Program */
#define FLASH_CR_UPER_Pos                         (5U)
#define FLASH_CR_UPER_Msk                         (0x1UL<<FLASH_CR_UPER_Pos)                        /*!< 0x00000020 */
#define FLASH_CR_UPER                             FLASH_CR_UPER_Msk                                 /*!< User data Page erase */
#define FLASH_CR_SER_Pos                          (11U)
#define FLASH_CR_SER_Msk                          (0x1UL<<FLASH_CR_SER_Pos)                         /*!< 0x00000800 */
#define FLASH_CR_SER                              FLASH_CR_SER_Msk                                  /*!< Sector Erase */
#define FLASH_CR_OPTSTRT_Pos                      (17U)
#define FLASH_CR_OPTSTRT_Msk                      (0x1UL<<FLASH_CR_OPTSTRT_Pos)                     /*!< 0x00020000 */
#define FLASH_CR_OPTSTRT                          FLASH_CR_OPTSTRT_Msk                              /*!< Option bytes Programming Start */
#define FLASH_CR_UPGSTRT_Pos                      (18U)
#define FLASH_CR_UPGSTRT_Msk                      (0x1UL<<FLASH_CR_UPGSTRT_Pos)                     /*!< 0x00020000 */
#define FLASH_CR_UPGSTRT                          FLASH_CR_UPGSTRT_Msk                              /*!< User data Programming Start */
#define FLASH_CR_PGSTRT_Pos                       (19U)
#define FLASH_CR_PGSTRT_Msk                       (0x1UL<<FLASH_CR_PGSTRT_Pos)                      /*!< 0x00080000 */
#define FLASH_CR_PGSTRT                           FLASH_CR_PGSTRT_Msk                               /*!< Programming Start */
#define FLASH_CR_VRPRGERRIE_Pos                   (20U)
#define FLASH_CR_VRPRGERRIE_Msk                   (0x1UL<<FLASH_CR_VRPRGERRIE_Pos)                  /*!< 0x00100000 */
#define FLASH_CR_VRPRGERRIE                       FLASH_CR_VRPRGERRIE_Msk                           
#define FLASH_CR_VRERSERRIE_Pos                   (21U)
#define FLASH_CR_VRERSERRIE_Msk                   (0x1UL<<FLASH_CR_VRERSERRIE_Pos)                  /*!< 0x00200000 */
#define FLASH_CR_VRERSERRIE                       FLASH_CR_VRERSERRIE_Msk                           
#define FLASH_CR_RDERRIE_Pos                      (22U)
#define FLASH_CR_RDERRIE_Msk                      (0x1UL<<FLASH_CR_RDERRIE_Pos)                     /*!< 0x00400000 */
#define FLASH_CR_RDERRIE                          FLASH_CR_RDERRIE_Msk                              /*!< bank1 read error */
#define FLASH_CR_EOPIE_Pos                        (24U)
#define FLASH_CR_EOPIE_Msk                        (0x1UL<<FLASH_CR_EOPIE_Pos)                       /*!< 0x01000000 */
#define FLASH_CR_EOPIE                            FLASH_CR_EOPIE_Msk                                /*!< End of operation interrupt enable */
#define FLASH_CR_ERRIE_Pos                        (25U)
#define FLASH_CR_ERRIE_Msk                        (0x1UL<<FLASH_CR_ERRIE_Pos)                       /*!< 0x02000000 */
#define FLASH_CR_ERRIE                            FLASH_CR_ERRIE_Msk                                /*!< Error interrupt enable */
#define FLASH_CR_OBL_LAUNCH_Pos                   (27U)
#define FLASH_CR_OBL_LAUNCH_Msk                   (0x1UL<<FLASH_CR_OBL_LAUNCH_Pos)                  /*!< 0x08000000 */
#define FLASH_CR_OBL_LAUNCH                       FLASH_CR_OBL_LAUNCH_Msk                           /*!< Force the option bytes loading */
#define FLASH_CR_SECPROT0_Pos                     (28U)
#define FLASH_CR_SECPROT0_Msk                     (0x1UL<<FLASH_CR_SECPROT0_Pos)                    /*!< 0x10000000 */
#define FLASH_CR_SECPROT0                         FLASH_CR_SECPROT0_Msk                             /*!< bank0 sec protect */
#define FLASH_CR_SECPROT1_Pos                     (29U)
#define FLASH_CR_SECPROT1_Msk                     (0x1UL<<FLASH_CR_SECPROT1_Pos)                    /*!< 0x20000000 */
#define FLASH_CR_SECPROT1                         FLASH_CR_SECPROT1_Msk                             /*!< bank1 sec protect */
#define FLASH_CR_OPTLOCK_Pos                      (30U)
#define FLASH_CR_OPTLOCK_Msk                      (0x1UL<<FLASH_CR_OPTLOCK_Pos)                     /*!< 0x40000000 */
#define FLASH_CR_OPTLOCK                          FLASH_CR_OPTLOCK_Msk                              /*!< Option Lock */
#define FLASH_CR_LOCK_Pos                         (31U)
#define FLASH_CR_LOCK_Msk                         (0x1UL<<FLASH_CR_LOCK_Pos)                        /*!< 0x80000000 */
#define FLASH_CR_LOCK                             FLASH_CR_LOCK_Msk                                 /*!< Lock */

/********************************* Bit definition for FLASH_OPTR1 register ******************************************/
#define FLASH_OPTR1_RDP_Pos                       (0U)
#define FLASH_OPTR1_RDP_Msk                       (0xFFUL<<FLASH_OPTR1_RDP_Pos)                     /*!< 0x000000FF */
#define FLASH_OPTR1_RDP                           FLASH_OPTR1_RDP_Msk                               /*!< Read Protection */
#define FLASH_OPTR1_NRST_STDBY_Pos                (8U)
#define FLASH_OPTR1_NRST_STDBY_Msk                (0x1UL<<FLASH_OPTR1_NRST_STDBY_Pos)               /*!< 0x00000100 */
#define FLASH_OPTR1_NRST_STDBY                    FLASH_OPTR1_NRST_STDBY_Msk                        
#define FLASH_OPTR1_NRST_STOP_Pos                 (9U)
#define FLASH_OPTR1_NRST_STOP_Msk                 (0x1UL<<FLASH_OPTR1_NRST_STOP_Pos)                /*!< 0x00000200 */
#define FLASH_OPTR1_NRST_STOP                     FLASH_OPTR1_NRST_STOP_Msk                         
#define FLASH_OPTR1_NRST_MODE_Pos                 (10U)
#define FLASH_OPTR1_NRST_MODE_Msk                 (0x3UL<<FLASH_OPTR1_NRST_MODE_Pos)                /*!< 0x00000C00 */
#define FLASH_OPTR1_NRST_MODE                     FLASH_OPTR1_NRST_MODE_Msk
#define FLASH_OPTR1_NRST_MODE_0                   (0x1UL<<FLASH_OPTR1_NRST_MODE_Pos)                /*!< 0x00000400 */
#define FLASH_OPTR1_NRST_MODE_1                   (0x2UL<<FLASH_OPTR1_NRST_MODE_Pos)                /*!< 0x00000800 */
#define FLASH_OPTR1_IWDG_STDBY_Pos                (12U)
#define FLASH_OPTR1_IWDG_STDBY_Msk                (0x1UL<<FLASH_OPTR1_IWDG_STDBY_Pos)               /*!< 0x00001000 */
#define FLASH_OPTR1_IWDG_STDBY                    FLASH_OPTR1_IWDG_STDBY_Msk                        
#define FLASH_OPTR1_IWDG_STOP_Pos                 (13U)
#define FLASH_OPTR1_IWDG_STOP_Msk                 (0x1UL<<FLASH_OPTR1_IWDG_STOP_Pos)                /*!< 0x00002000 */
#define FLASH_OPTR1_IWDG_STOP                     FLASH_OPTR1_IWDG_STOP_Msk                         
#define FLASH_OPTR1_IWDG_SW_Pos                   (14U)
#define FLASH_OPTR1_IWDG_SW_Msk                   (0x1UL<<FLASH_OPTR1_IWDG_SW_Pos)                  /*!< 0x00004000 */
#define FLASH_OPTR1_IWDG_SW                       FLASH_OPTR1_IWDG_SW_Msk                           /*!< IWDG Software Enable */
#define FLASH_OPTR1_WWDG_SW_Pos                   (15U)
#define FLASH_OPTR1_WWDG_SW_Msk                   (0x1UL<<FLASH_OPTR1_WWDG_SW_Pos)                  /*!< 0x00008000 */
#define FLASH_OPTR1_WWDG_SW                       FLASH_OPTR1_WWDG_SW_Msk                           
#define FLASH_OPTR1_NBOOT0_Pos                    (16U)
#define FLASH_OPTR1_NBOOT0_Msk                    (0x1UL<<FLASH_OPTR1_NBOOT0_Pos)                   /*!< 0x00010000 */
#define FLASH_OPTR1_NBOOT0                        FLASH_OPTR1_NBOOT0_Msk                            
#define FLASH_OPTR1_NBOOT1_Pos                    (17U)
#define FLASH_OPTR1_NBOOT1_Msk                    (0x1UL<<FLASH_OPTR1_NBOOT1_Pos)                   /*!< 0x00020000 */
#define FLASH_OPTR1_NBOOT1                        FLASH_OPTR1_NBOOT1_Msk                            
#define FLASH_OPTR1_NSWBOOT0_Pos                  (18U)
#define FLASH_OPTR1_NSWBOOT0_Msk                  (0x1UL<<FLASH_OPTR1_NSWBOOT0_Pos)                 /*!< 0x00040000 */
#define FLASH_OPTR1_NSWBOOT0                      FLASH_OPTR1_NSWBOOT0_Msk                          
#define FLASH_OPTR1_BOOT_LOCK_Pos                 (20U)
#define FLASH_OPTR1_BOOT_LOCK_Msk                 (0x1UL<<FLASH_OPTR1_BOOT_LOCK_Pos)                /*!< 0x00100000 */
#define FLASH_OPTR1_BOOT_LOCK                     FLASH_OPTR1_BOOT_LOCK_Msk                         
#define FLASH_OPTR1_SWD_MODE_Pos                  (25U)
#define FLASH_OPTR1_SWD_MODE_Msk                  (0x3UL<<FLASH_OPTR1_SWD_MODE_Pos)                 /*!< 0x06000000 */
#define FLASH_OPTR1_SWD_MODE                      FLASH_OPTR1_SWD_MODE_Msk
#define FLASH_OPTR1_SWD_MODE_0                    (0x1UL<<FLASH_OPTR1_SWD_MODE_Pos)                 /*!< 0x02000000 */
#define FLASH_OPTR1_SWD_MODE_1                    (0x2UL<<FLASH_OPTR1_SWD_MODE_Pos)                 /*!< 0x04000000 */

/********************************* Bit definition for FLASH_OPTR2 register ******************************************/
#define FLASH_OPTR2_ACC_CTRL_Pos                  (0U)
#define FLASH_OPTR2_ACC_CTRL_Msk                  (0x7UL<<FLASH_OPTR2_ACC_CTRL_Pos)                 /*!< 0x00000007 */
#define FLASH_OPTR2_ACC_CTRL                      FLASH_OPTR2_ACC_CTRL_Msk
#define FLASH_OPTR2_ACC_CTRL_0                    (0x1UL<<FLASH_OPTR2_ACC_CTRL_Pos)                 /*!< 0x00000001 */
#define FLASH_OPTR2_ACC_CTRL_1                    (0x2UL<<FLASH_OPTR2_ACC_CTRL_Pos)                 /*!< 0x00000002 */
#define FLASH_OPTR2_ACC_CTRL_2                    (0x4UL<<FLASH_OPTR2_ACC_CTRL_Pos)                 /*!< 0x00000004 */
#define FLASH_OPTR2_PLL_UNLOCK_RSTEN_Pos          (3U)
#define FLASH_OPTR2_PLL_UNLOCK_RSTEN_Msk          (0x1UL<<FLASH_OPTR2_PLL_UNLOCK_RSTEN_Pos)         /*!< 0x00000008 */
#define FLASH_OPTR2_PLL_UNLOCK_RSTEN              FLASH_OPTR2_PLL_UNLOCK_RSTEN_Msk  
#define FLASH_OPTR2_VERIFY_READ_EN_Pos            (4U)
#define FLASH_OPTR2_VERIFY_READ_EN_Msk            (0x1UL<<FLASH_OPTR2_VERIFY_READ_EN_Pos)         /*!< 0x00000008 */
#define FLASH_OPTR2_VERIFY_READ_EN                FLASH_OPTR2_VERIFY_READ_EN_Msk   

/********************************* Bit definition for FLASH_WRPR0 register ******************************************/
#define FLASH_WRPR0_BANK0_WRPR_Pos                (0U)
#define FLASH_WRPR0_BANK0_WRPR_Msk                (0xFFFFUL<<FLASH_WRPR0_BANK0_WRPR_Pos)            /*!< 0x0000FFFF */
#define FLASH_WRPR0_BANK0_WRPR                    FLASH_WRPR0_BANK0_WRPR_Msk                        /*!< Write Protection Disable */

/********************************* Bit definition for FLASH_PCROPR0 register ****************************************/
#define FLASH_PCROPR0_PCROP0SR_Pos                (0U)
#define FLASH_PCROPR0_PCROP0SR_Msk                (0x1FFUL<<FLASH_PCROPR0_PCROP0SR_Pos)             /*!< 0x000001FF */
#define FLASH_PCROPR0_PCROP0SR                    FLASH_PCROPR0_PCROP0SR_Msk
#define FLASH_PCROPR0_PCROP0ER_Pos                (16U)
#define FLASH_PCROPR0_PCROP0ER_Msk                (0x1FFUL<<FLASH_PCROPR0_PCROP0ER_Pos)             /*!< 0x01FF0000 */
#define FLASH_PCROPR0_PCROP0ER                    FLASH_PCROPR0_PCROP0ER_Msk

/********************************* Bit definition for FLASH_SECR0 register ******************************************/
#define FLASH_SECR0_SEC_SIZEER0_Pos               (16U)
#define FLASH_SECR0_SEC_SIZEER0_Msk               (0x1FFUL<<FLASH_SECR0_SEC_SIZEER0_Pos)            /*!< 0x01FF0000 */
#define FLASH_SECR0_SEC_SIZEER0                   FLASH_SECR0_SEC_SIZEER0_Msk

/********************************* Bit definition for FLASH_WRPR1 register ******************************************/
#define FLASH_WRPR1_BANK1_WRPR_Pos                (0U)
#define FLASH_WRPR1_BANK1_WRPR_Msk                (0xFFFFUL<<FLASH_WRPR1_BANK1_WRPR_Pos)            /*!< 0x0000FFFF */
#define FLASH_WRPR1_BANK1_WRPR                    FLASH_WRPR1_BANK1_WRPR_Msk                        /*!< Write Protection Disable */

/********************************* Bit definition for FLASH_PCROPR1 register ****************************************/
#define FLASH_PCROPR1_PCROP1SR_Pos                (0U)
#define FLASH_PCROPR1_PCROP1SR_Msk                (0x1FFUL<<FLASH_PCROPR1_PCROP1SR_Pos)             /*!< 0x000001FF */
#define FLASH_PCROPR1_PCROP1SR                    FLASH_PCROPR1_PCROP1SR_Msk
#define FLASH_PCROPR1_PCROP1ER_Pos                (16U)
#define FLASH_PCROPR1_PCROP1ER_Msk                (0x1FFUL<<FLASH_PCROPR1_PCROP1ER_Pos)             /*!< 0x01FF0000 */
#define FLASH_PCROPR1_PCROP1ER                    FLASH_PCROPR1_PCROP1ER_Msk

/********************************* Bit definition for FLASH_SECR1 register ******************************************/
#define FLASH_SECR1_SEC_SIZEER1_Pos               (16U)
#define FLASH_SECR1_SEC_SIZEER1_Msk               (0x1FFUL<<FLASH_SECR1_SEC_SIZEER1_Pos)            /*!< 0x01FF0000 */
#define FLASH_SECR1_SEC_SIZEER1                   FLASH_SECR1_SEC_SIZEER1_Msk

/********************************* Bit definition for FLASH_OPTBFB register *****************************************/
#define FLASH_OPTBFB_BFB_Pos                      (0U)
#define FLASH_OPTBFB_BFB_Msk                      (0x1UL<<FLASH_OPTBFB_BFB_Pos)                     /*!< 0x00000001 */
#define FLASH_OPTBFB_BFB                          FLASH_OPTBFB_BFB_Msk                        

/********************************************************************************************************************/
/********************************* RCC ******************************************************************************/
/********************************************************************************************************************/
#define RCC_HSE_SUPPORT
#define RCC_LSE_SUPPORT
#define RCC_PLL_SUPPORT

/********************************* Bit definition for RCC_CR register ***********************************************/
#define RCC_CR_HSION_Pos                          (8U)
#define RCC_CR_HSION_Msk                          (0x1UL<<RCC_CR_HSION_Pos)                         /*!< 0x00000100 */
#define RCC_CR_HSION                              RCC_CR_HSION_Msk                                  
#define RCC_CR_HSIKERON_Pos                       (9U)
#define RCC_CR_HSIKERON_Msk                       (0x1UL<<RCC_CR_HSIKERON_Pos)                      /*!< 0x00000200 */
#define RCC_CR_HSIKERON                           RCC_CR_HSIKERON_Msk                               
#define RCC_CR_HSIRDY_Pos                         (10U)
#define RCC_CR_HSIRDY_Msk                         (0x1UL<<RCC_CR_HSIRDY_Pos)                        /*!< 0x00000400 */
#define RCC_CR_HSIRDY                             RCC_CR_HSIRDY_Msk                                 
#define RCC_CR_HSIDIV_Pos                         (11U)
#define RCC_CR_HSIDIV_Msk                         (0x3UL<<RCC_CR_HSIDIV_Pos)                        /*!< 0x00001800 */
#define RCC_CR_HSIDIV                             RCC_CR_HSIDIV_Msk
#define RCC_CR_HSIDIV_0                           (0x1UL<<RCC_CR_HSIDIV_Pos)                        /*!< 0x00000800 */
#define RCC_CR_HSIDIV_1                           (0x2UL<<RCC_CR_HSIDIV_Pos)                        /*!< 0x00001000 */
#define RCC_CR_HSEON_Pos                          (16U)
#define RCC_CR_HSEON_Msk                          (0x1UL<<RCC_CR_HSEON_Pos)                         /*!< 0x00010000 */
#define RCC_CR_HSEON                              RCC_CR_HSEON_Msk                                  
#define RCC_CR_HSERDY_Pos                         (17U)
#define RCC_CR_HSERDY_Msk                         (0x1UL<<RCC_CR_HSERDY_Pos)                        /*!< 0x00020000 */
#define RCC_CR_HSERDY                             RCC_CR_HSERDY_Msk                                 
#define RCC_CR_HSEBYP_Pos                         (18U)
#define RCC_CR_HSEBYP_Msk                         (0x1UL<<RCC_CR_HSEBYP_Pos)                        /*!< 0x00040000 */
#define RCC_CR_HSEBYP                             RCC_CR_HSEBYP_Msk                                 
#define RCC_CR_HSECSSON_Pos                       (19U)
#define RCC_CR_HSECSSON_Msk                       (0x1UL<<RCC_CR_HSECSSON_Pos)                      /*!< 0x00080000 */
#define RCC_CR_HSECSSON                           RCC_CR_HSECSSON_Msk                               
#define RCC_CR_PLLON_Pos                          (24U)
#define RCC_CR_PLLON_Msk                          (0x1UL<<RCC_CR_PLLON_Pos)                         /*!< 0x01000000 */
#define RCC_CR_PLLON                              RCC_CR_PLLON_Msk                                  
#define RCC_CR_PLLRDY_Pos                         (25U)
#define RCC_CR_PLLRDY_Msk                         (0x1UL<<RCC_CR_PLLRDY_Pos)                        /*!< 0x02000000 */
#define RCC_CR_PLLRDY                             RCC_CR_PLLRDY_Msk                                 

/********************************* Bit definition for RCC_ICSCR register ********************************************/
#define RCC_ICSCR_HSI_TRIMCR_Pos                  (0U)
#define RCC_ICSCR_HSI_TRIMCR_Msk                  (0xFFFFUL<<RCC_ICSCR_HSI_TRIMCR_Pos)              /*!< 0x0000FFFF */
#define RCC_ICSCR_HSI_TRIMCR                      RCC_ICSCR_HSI_TRIMCR_Msk
#define RCC_ICSCR_HSI_FS_Pos                      (16U)
#define RCC_ICSCR_HSI_FS_Msk                      (0x3UL<<RCC_ICSCR_HSI_FS_Pos)                     /*!< 0x00030000 */
#define RCC_ICSCR_HSI_FS                          RCC_ICSCR_HSI_FS_Msk
#define RCC_ICSCR_HSI_FS_0                        (0x1UL<<RCC_ICSCR_HSI_FS_Pos)                     /*!< 0x00010000 */
#define RCC_ICSCR_HSI_FS_1                        (0x2UL<<RCC_ICSCR_HSI_FS_Pos)                     /*!< 0x00020000 */

/********************************* Bit definition for RCC_CFGR1 register ********************************************/
#define RCC_CFGR1_SW_Pos                          (0U)
#define RCC_CFGR1_SW_Msk                          (0x3UL<<RCC_CFGR1_SW_Pos)                         /*!< 0x00000003 */
#define RCC_CFGR1_SW                              RCC_CFGR1_SW_Msk
#define RCC_CFGR1_SW_0                            (0x1UL<<RCC_CFGR1_SW_Pos)                         /*!< 0x00000001 */
#define RCC_CFGR1_SW_1                            (0x2UL<<RCC_CFGR1_SW_Pos)                         /*!< 0x00000002 */
#define RCC_CFGR1_SWS_Pos                         (4U)
#define RCC_CFGR1_SWS_Msk                         (0x3UL<<RCC_CFGR1_SWS_Pos)                        /*!< 0x00000030 */
#define RCC_CFGR1_SWS                             RCC_CFGR1_SWS_Msk
#define RCC_CFGR1_SWS_0                           (0x1UL<<RCC_CFGR1_SWS_Pos)                        /*!< 0x00000010 */
#define RCC_CFGR1_SWS_1                           (0x2UL<<RCC_CFGR1_SWS_Pos)                        /*!< 0x00000020 */
#define RCC_CFGR1_HPRE_Pos                        (8U)
#define RCC_CFGR1_HPRE_Msk                        (0xFUL<<RCC_CFGR1_HPRE_Pos)                       /*!< 0x00000F00 */
#define RCC_CFGR1_HPRE                            RCC_CFGR1_HPRE_Msk
#define RCC_CFGR1_HPRE_0                          (0x1UL<<RCC_CFGR1_HPRE_Pos)                       /*!< 0x00000100 */
#define RCC_CFGR1_HPRE_1                          (0x2UL<<RCC_CFGR1_HPRE_Pos)                       /*!< 0x00000200 */
#define RCC_CFGR1_HPRE_2                          (0x4UL<<RCC_CFGR1_HPRE_Pos)                       /*!< 0x00000400 */
#define RCC_CFGR1_HPRE_3                          (0x8UL<<RCC_CFGR1_HPRE_Pos)                       /*!< 0x00000800 */
#define RCC_CFGR1_PPRE1_Pos                       (12U)
#define RCC_CFGR1_PPRE1_Msk                       (0x7UL<<RCC_CFGR1_PPRE1_Pos)                      /*!< 0x00007000 */
#define RCC_CFGR1_PPRE1                           RCC_CFGR1_PPRE1_Msk
#define RCC_CFGR1_PPRE1_0                         (0x1UL<<RCC_CFGR1_PPRE1_Pos)                      /*!< 0x00001000 */
#define RCC_CFGR1_PPRE1_1                         (0x2UL<<RCC_CFGR1_PPRE1_Pos)                      /*!< 0x00002000 */
#define RCC_CFGR1_PPRE1_2                         (0x4UL<<RCC_CFGR1_PPRE1_Pos)                      /*!< 0x00004000 */
#define RCC_CFGR1_MCO1SEL_Pos                     (16U)
#define RCC_CFGR1_MCO1SEL_Msk                     (0xFUL<<RCC_CFGR1_MCO1SEL_Pos)                    /*!< 0x000F0000 */
#define RCC_CFGR1_MCO1SEL                         RCC_CFGR1_MCO1SEL_Msk
#define RCC_CFGR1_MCO1SEL_0                       (0x1UL<<RCC_CFGR1_MCO1SEL_Pos)                    /*!< 0x00010000 */
#define RCC_CFGR1_MCO1SEL_1                       (0x2UL<<RCC_CFGR1_MCO1SEL_Pos)                    /*!< 0x00020000 */
#define RCC_CFGR1_MCO1SEL_2                       (0x4UL<<RCC_CFGR1_MCO1SEL_Pos)                    /*!< 0x00040000 */
#define RCC_CFGR1_MCO1SEL_3                       (0x8UL<<RCC_CFGR1_MCO1SEL_Pos)                    /*!< 0x00080000 */
#define RCC_CFGR1_MCO1PRE_Pos                     (20U)
#define RCC_CFGR1_MCO1PRE_Msk                     (0xFUL<<RCC_CFGR1_MCO1PRE_Pos)                    /*!< 0x00F00000 */
#define RCC_CFGR1_MCO1PRE                         RCC_CFGR1_MCO1PRE_Msk
#define RCC_CFGR1_MCO1PRE_0                       (0x1UL<<RCC_CFGR1_MCO1PRE_Pos)                    /*!< 0x00100000 */
#define RCC_CFGR1_MCO1PRE_1                       (0x2UL<<RCC_CFGR1_MCO1PRE_Pos)                    /*!< 0x00200000 */
#define RCC_CFGR1_MCO1PRE_2                       (0x4UL<<RCC_CFGR1_MCO1PRE_Pos)                    /*!< 0x00400000 */
#define RCC_CFGR1_MCO1PRE_3                       (0x8UL<<RCC_CFGR1_MCO1PRE_Pos)                    /*!< 0x00800000 */
#define RCC_CFGR1_MCO2SEL_Pos                     (24U)
#define RCC_CFGR1_MCO2SEL_Msk                     (0xFUL<<RCC_CFGR1_MCO2SEL_Pos)                    /*!< 0x0F000000 */
#define RCC_CFGR1_MCO2SEL                         RCC_CFGR1_MCO2SEL_Msk
#define RCC_CFGR1_MCO2SEL_0                       (0x1UL<<RCC_CFGR1_MCO2SEL_Pos)                    /*!< 0x01000000 */
#define RCC_CFGR1_MCO2SEL_1                       (0x2UL<<RCC_CFGR1_MCO2SEL_Pos)                    /*!< 0x02000000 */
#define RCC_CFGR1_MCO2SEL_2                       (0x4UL<<RCC_CFGR1_MCO2SEL_Pos)                    /*!< 0x04000000 */
#define RCC_CFGR1_MCO2SEL_3                       (0x8UL<<RCC_CFGR1_MCO2SEL_Pos)                    /*!< 0x08000000 */
#define RCC_CFGR1_MCO2PRE_Pos                     (28U)
#define RCC_CFGR1_MCO2PRE_Msk                     (0xFUL<<RCC_CFGR1_MCO2PRE_Pos)                    /*!< 0xF0000000 */
#define RCC_CFGR1_MCO2PRE                         RCC_CFGR1_MCO2PRE_Msk
#define RCC_CFGR1_MCO2PRE_0                       (0x1UL<<RCC_CFGR1_MCO2PRE_Pos)                    /*!< 0x10000000 */
#define RCC_CFGR1_MCO2PRE_1                       (0x2UL<<RCC_CFGR1_MCO2PRE_Pos)                    /*!< 0x20000000 */
#define RCC_CFGR1_MCO2PRE_2                       (0x4UL<<RCC_CFGR1_MCO2PRE_Pos)                    /*!< 0x40000000 */
#define RCC_CFGR1_MCO2PRE_3                       (0x8UL<<RCC_CFGR1_MCO2PRE_Pos)                    /*!< 0x80000000 */

#define RCC_CFGR1_SW_HSISYS                       (0x00000000U)                                     /*!< HSI selected as system clock */
#define RCC_CFGR1_SW_HSE                          (0x00000001U)                                     /*!< HSE selected as system clock */
#define RCC_CFGR1_SW_PLL                          (0x00000002U)

#define RCC_CFGR1_SWS_HSISYS                      (0x00000000U)                                     /*!< HSISYS used as system clock */
#define RCC_CFGR1_SWS_HSE                         (0x00000010U)                                     /*!< HSE used as system clock */
#define RCC_CFGR1_SWS_PLL                         (0x00000020U)                                     /*!< PLL used as system clock */

/********************************* Bit definition for RCC_CFGR2 register ********************************************/
#define RCC_CFGR2_PPRE2_Pos                       (8U)
#define RCC_CFGR2_PPRE2_Msk                       (0x7UL<<RCC_CFGR2_PPRE2_Pos)                      /*!< 0x00000700 */
#define RCC_CFGR2_PPRE2                           RCC_CFGR2_PPRE2_Msk
#define RCC_CFGR2_PPRE2_0                         (0x1UL<<RCC_CFGR2_PPRE2_Pos)                      /*!< 0x00000100 */
#define RCC_CFGR2_PPRE2_1                         (0x2UL<<RCC_CFGR2_PPRE2_Pos)                      /*!< 0x00000200 */
#define RCC_CFGR2_PPRE2_2                         (0x4UL<<RCC_CFGR2_PPRE2_Pos)                      /*!< 0x00000400 */

/********************************* Bit definition for RCC_PLLCFGR1 register *****************************************/
#define RCC_PLLCFGR1_PLLSRC_Pos                   (0U)
#define RCC_PLLCFGR1_PLLSRC_Msk                   (0x1UL<<RCC_PLLCFGR1_PLLSRC_Pos)                  /*!< 0x00000001 */
#define RCC_PLLCFGR1_PLLSRC                       RCC_PLLCFGR1_PLLSRC_Msk                           
#define RCC_PLLCFGR1_PLLMUL_Pos                   (2U)
#define RCC_PLLCFGR1_PLLMUL_Msk                   (0xFUL<<RCC_PLLCFGR1_PLLMUL_Pos)                  /*!< 0x0000003C */
#define RCC_PLLCFGR1_PLLMUL                       RCC_PLLCFGR1_PLLMUL_Msk
#define RCC_PLLCFGR1_PLLMUL_0                     (0x1UL<<RCC_PLLCFGR1_PLLMUL_Pos)                  /*!< 0x00000004 */
#define RCC_PLLCFGR1_PLLMUL_1                     (0x2UL<<RCC_PLLCFGR1_PLLMUL_Pos)                  /*!< 0x00000008 */
#define RCC_PLLCFGR1_PLLMUL_2                     (0x4UL<<RCC_PLLCFGR1_PLLMUL_Pos)                  /*!< 0x00000010 */
#define RCC_PLLCFGR1_PLLMUL_3                     (0x8UL<<RCC_PLLCFGR1_PLLMUL_Pos)                  /*!< 0x00000020 */

/********************************* Bit definition for RCC_ECSCR register ********************************************/
#define RCC_ECSCR_HSE_DRV_Pos                     (0U)
#define RCC_ECSCR_HSE_DRV_Msk                     (0x3UL<<RCC_ECSCR_HSE_DRV_Pos)                    /*!< 0x00000003 */
#define RCC_ECSCR_HSE_DRV                         RCC_ECSCR_HSE_DRV_Msk
#define RCC_ECSCR_HSE_DRV_0                       (0x1UL<<RCC_ECSCR_HSE_DRV_Pos)                    /*!< 0x00000001 */
#define RCC_ECSCR_HSE_DRV_1                       (0x2UL<<RCC_ECSCR_HSE_DRV_Pos)                    /*!< 0x00000002 */
#define RCC_ECSCR_HSE_RDYSEL_Pos                  (2U)
#define RCC_ECSCR_HSE_RDYSEL_Msk                  (0x3UL<<RCC_ECSCR_HSE_RDYSEL_Pos)                 /*!< 0x0000000C */
#define RCC_ECSCR_HSE_RDYSEL                      RCC_ECSCR_HSE_RDYSEL_Msk
#define RCC_ECSCR_HSE_RDYSEL_0                    (0x1UL<<RCC_ECSCR_HSE_RDYSEL_Pos)                 /*!< 0x00000004 */
#define RCC_ECSCR_HSE_RDYSEL_1                    (0x2UL<<RCC_ECSCR_HSE_RDYSEL_Pos)                 /*!< 0x00000008 */
#define RCC_ECSCR_HSE_FILT_ENB_Pos                (4U)
#define RCC_ECSCR_HSE_FILT_ENB_Msk                (0x1UL<<RCC_ECSCR_HSE_FILT_ENB_Pos)               /*!< 0x00000010 */
#define RCC_ECSCR_HSE_FILT_ENB                    RCC_ECSCR_HSE_FILT_ENB_Msk                        

/********************************* Bit definition for RCC_CIER register *********************************************/
#define RCC_CIER_LSIRDYIE_Pos                     (0U)
#define RCC_CIER_LSIRDYIE_Msk                     (0x1UL<<RCC_CIER_LSIRDYIE_Pos)                    /*!< 0x00000001 */
#define RCC_CIER_LSIRDYIE                         RCC_CIER_LSIRDYIE_Msk                             
#define RCC_CIER_LSERDYIE_Pos                     (1U)
#define RCC_CIER_LSERDYIE_Msk                     (0x1UL<<RCC_CIER_LSERDYIE_Pos)                    /*!< 0x00000002 */
#define RCC_CIER_LSERDYIE                         RCC_CIER_LSERDYIE_Msk                             
#define RCC_CIER_HSIRDYIE_Pos                     (2U)
#define RCC_CIER_HSIRDYIE_Msk                     (0x1UL<<RCC_CIER_HSIRDYIE_Pos)                    /*!< 0x00000004 */
#define RCC_CIER_HSIRDYIE                         RCC_CIER_HSIRDYIE_Msk                             
#define RCC_CIER_HSERDYIE_Pos                     (3U)
#define RCC_CIER_HSERDYIE_Msk                     (0x1UL<<RCC_CIER_HSERDYIE_Pos)                    /*!< 0x00000008 */
#define RCC_CIER_HSERDYIE                         RCC_CIER_HSERDYIE_Msk                             
#define RCC_CIER_PLLRDYIE_Pos                     (4U)
#define RCC_CIER_PLLRDYIE_Msk                     (0x1UL<<RCC_CIER_PLLRDYIE_Pos)                    /*!< 0x00000010 */
#define RCC_CIER_PLLRDYIE                         RCC_CIER_PLLRDYIE_Msk                             

/********************************* Bit definition for RCC_CIFR register *********************************************/
#define RCC_CIFR_LSIRDYF_Pos                      (0U)
#define RCC_CIFR_LSIRDYF_Msk                      (0x1UL<<RCC_CIFR_LSIRDYF_Pos)                     /*!< 0x00000001 */
#define RCC_CIFR_LSIRDYF                          RCC_CIFR_LSIRDYF_Msk                              
#define RCC_CIFR_LSERDYF_Pos                      (1U)
#define RCC_CIFR_LSERDYF_Msk                      (0x1UL<<RCC_CIFR_LSERDYF_Pos)                     /*!< 0x00000002 */
#define RCC_CIFR_LSERDYF                          RCC_CIFR_LSERDYF_Msk                              
#define RCC_CIFR_HSIRDYF_Pos                      (2U)
#define RCC_CIFR_HSIRDYF_Msk                      (0x1UL<<RCC_CIFR_HSIRDYF_Pos)                     /*!< 0x00000004 */
#define RCC_CIFR_HSIRDYF                          RCC_CIFR_HSIRDYF_Msk                              
#define RCC_CIFR_HSERDYF_Pos                      (3U)
#define RCC_CIFR_HSERDYF_Msk                      (0x1UL<<RCC_CIFR_HSERDYF_Pos)                     /*!< 0x00000008 */
#define RCC_CIFR_HSERDYF                          RCC_CIFR_HSERDYF_Msk                              
#define RCC_CIFR_PLLRDYF_Pos                      (4U)
#define RCC_CIFR_PLLRDYF_Msk                      (0x1UL<<RCC_CIFR_PLLRDYF_Pos)                     /*!< 0x00000010 */
#define RCC_CIFR_PLLRDYF                          RCC_CIFR_PLLRDYF_Msk                              
#define RCC_CIFR_LSECSSF_Pos                      (7U)
#define RCC_CIFR_LSECSSF_Msk                      (0x1UL<<RCC_CIFR_LSECSSF_Pos)                     /*!< 0x00000080 */
#define RCC_CIFR_LSECSSF                          RCC_CIFR_LSECSSF_Msk                              
#define RCC_CIFR_HSECSSF_Pos                      (8U)
#define RCC_CIFR_HSECSSF_Msk                      (0x1UL<<RCC_CIFR_HSECSSF_Pos)                     /*!< 0x00000100 */
#define RCC_CIFR_HSECSSF                          RCC_CIFR_HSECSSF_Msk                              

/********************************* Bit definition for RCC_CICR register *********************************************/
#define RCC_CICR_LSIRDYC_Pos                      (0U)
#define RCC_CICR_LSIRDYC_Msk                      (0x1UL<<RCC_CICR_LSIRDYC_Pos)                     /*!< 0x00000001 */
#define RCC_CICR_LSIRDYC                          RCC_CICR_LSIRDYC_Msk                              
#define RCC_CICR_LSERDYC_Pos                      (1U)
#define RCC_CICR_LSERDYC_Msk                      (0x1UL<<RCC_CICR_LSERDYC_Pos)                     /*!< 0x00000002 */
#define RCC_CICR_LSERDYC                          RCC_CICR_LSERDYC_Msk                              
#define RCC_CICR_HSIRDYC_Pos                      (2U)
#define RCC_CICR_HSIRDYC_Msk                      (0x1UL<<RCC_CICR_HSIRDYC_Pos)                     /*!< 0x00000004 */
#define RCC_CICR_HSIRDYC                          RCC_CICR_HSIRDYC_Msk                              
#define RCC_CICR_HSERDYC_Pos                      (3U)
#define RCC_CICR_HSERDYC_Msk                      (0x1UL<<RCC_CICR_HSERDYC_Pos)                     /*!< 0x00000008 */
#define RCC_CICR_HSERDYC                          RCC_CICR_HSERDYC_Msk                              
#define RCC_CICR_PLLRDYC_Pos                      (4U)
#define RCC_CICR_PLLRDYC_Msk                      (0x1UL<<RCC_CICR_PLLRDYC_Pos)                     /*!< 0x00000010 */
#define RCC_CICR_PLLRDYC                          RCC_CICR_PLLRDYC_Msk                              
#define RCC_CICR_LSECSSC_Pos                      (7U)
#define RCC_CICR_LSECSSC_Msk                      (0x1UL<<RCC_CICR_LSECSSC_Pos)                     /*!< 0x00000080 */
#define RCC_CICR_LSECSSC                          RCC_CICR_LSECSSC_Msk                              
#define RCC_CICR_HSECSSC_Pos                      (8U)
#define RCC_CICR_HSECSSC_Msk                      (0x1UL<<RCC_CICR_HSECSSC_Pos)                     /*!< 0x00000100 */
#define RCC_CICR_HSECSSC                          RCC_CICR_HSECSSC_Msk                              

/********************************* Bit definition for RCC_AHBRSTR1 register *****************************************/
#define RCC_AHBRSTR1_DMARST_Pos                   (0U)
#define RCC_AHBRSTR1_DMARST_Msk                   (0x1UL<<RCC_AHBRSTR1_DMARST_Pos)                  /*!< 0x00000001 */
#define RCC_AHBRSTR1_DMARST                       RCC_AHBRSTR1_DMARST_Msk                           
#define RCC_AHBRSTR1_CRCRST_Pos                   (16U)
#define RCC_AHBRSTR1_CRCRST_Msk                   (0x1UL<<RCC_AHBRSTR1_CRCRST_Pos)                  /*!< 0x00010000 */
#define RCC_AHBRSTR1_CRCRST                       RCC_AHBRSTR1_CRCRST_Msk                           

/********************************* Bit definition for RCC_AHBRSTR2 register *****************************************/
#define RCC_AHBRSTR2_GPIOARST_Pos                 (0U)
#define RCC_AHBRSTR2_GPIOARST_Msk                 (0x1UL<<RCC_AHBRSTR2_GPIOARST_Pos)                /*!< 0x00000001 */
#define RCC_AHBRSTR2_GPIOARST                     RCC_AHBRSTR2_GPIOARST_Msk                         
#define RCC_AHBRSTR2_GPIOBRST_Pos                 (1U)
#define RCC_AHBRSTR2_GPIOBRST_Msk                 (0x1UL<<RCC_AHBRSTR2_GPIOBRST_Pos)                /*!< 0x00000002 */
#define RCC_AHBRSTR2_GPIOBRST                     RCC_AHBRSTR2_GPIOBRST_Msk                         
#define RCC_AHBRSTR2_GPIOCRST_Pos                 (2U)
#define RCC_AHBRSTR2_GPIOCRST_Msk                 (0x1UL<<RCC_AHBRSTR2_GPIOCRST_Pos)                /*!< 0x00000004 */
#define RCC_AHBRSTR2_GPIOCRST                     RCC_AHBRSTR2_GPIOCRST_Msk                         
#define RCC_AHBRSTR2_GPIODRST_Pos                 (3U)
#define RCC_AHBRSTR2_GPIODRST_Msk                 (0x1UL<<RCC_AHBRSTR2_GPIODRST_Pos)                /*!< 0x00000008 */
#define RCC_AHBRSTR2_GPIODRST                     RCC_AHBRSTR2_GPIODRST_Msk                         

/********************************* Bit definition for RCC_APBRSTR1 register *****************************************/
#define RCC_APBRSTR1_TIM1RST_Pos                  (1U)
#define RCC_APBRSTR1_TIM1RST_Msk                  (0x1UL<<RCC_APBRSTR1_TIM1RST_Pos)                 /*!< 0x00000002 */
#define RCC_APBRSTR1_TIM1RST                      RCC_APBRSTR1_TIM1RST_Msk                          
#define RCC_APBRSTR1_TIM2RST_Pos                  (2U)
#define RCC_APBRSTR1_TIM2RST_Msk                  (0x1UL<<RCC_APBRSTR1_TIM2RST_Pos)                 /*!< 0x00000004 */
#define RCC_APBRSTR1_TIM2RST                      RCC_APBRSTR1_TIM2RST_Msk                          
#define RCC_APBRSTR1_TIM3RST_Pos                  (3U)
#define RCC_APBRSTR1_TIM3RST_Msk                  (0x1UL<<RCC_APBRSTR1_TIM3RST_Pos)                 /*!< 0x00000008 */
#define RCC_APBRSTR1_TIM3RST                      RCC_APBRSTR1_TIM3RST_Msk                          
#define RCC_APBRSTR1_TIM6RST_Pos                  (6U)
#define RCC_APBRSTR1_TIM6RST_Msk                  (0x1UL<<RCC_APBRSTR1_TIM6RST_Pos)                 /*!< 0x00000040 */
#define RCC_APBRSTR1_TIM6RST                      RCC_APBRSTR1_TIM6RST_Msk                          
#define RCC_APBRSTR1_TIM7RST_Pos                  (7U)
#define RCC_APBRSTR1_TIM7RST_Msk                  (0x1UL<<RCC_APBRSTR1_TIM7RST_Pos)                 /*!< 0x00000080 */
#define RCC_APBRSTR1_TIM7RST                      RCC_APBRSTR1_TIM7RST_Msk                          
#define RCC_APBRSTR1_TIM8RST_Pos                  (8U)
#define RCC_APBRSTR1_TIM8RST_Msk                  (0x1UL<<RCC_APBRSTR1_TIM8RST_Pos)                 /*!< 0x00000100 */
#define RCC_APBRSTR1_TIM8RST                      RCC_APBRSTR1_TIM8RST_Msk                          

/********************************* Bit definition for RCC_APBRSTR2 register *****************************************/
#define RCC_APBRSTR2_EPWMRST_Pos                  (8U)
#define RCC_APBRSTR2_EPWMRST_Msk                  (0x1UL<<RCC_APBRSTR2_EPWMRST_Pos)                 /*!< 0x00000100 */
#define RCC_APBRSTR2_EPWMRST                      RCC_APBRSTR2_EPWMRST_Msk                         
#define RCC_APBRSTR2_LPTIMRST_Pos                 (16U)
#define RCC_APBRSTR2_LPTIMRST_Msk                 (0x1UL<<RCC_APBRSTR2_LPTIMRST_Pos)                /*!< 0x00010000 */
#define RCC_APBRSTR2_LPTIMRST                     RCC_APBRSTR2_LPTIMRST_Msk                         

/********************************* Bit definition for RCC_APBRSTR3 register *****************************************/
#define RCC_APBRSTR3_UART1RST_Pos                 (0U)
#define RCC_APBRSTR3_UART1RST_Msk                 (0x1UL<<RCC_APBRSTR3_UART1RST_Pos)                /*!< 0x00000001 */
#define RCC_APBRSTR3_UART1RST                     RCC_APBRSTR3_UART1RST_Msk                         
#define RCC_APBRSTR3_UART2RST_Pos                 (1U)
#define RCC_APBRSTR3_UART2RST_Msk                 (0x1UL<<RCC_APBRSTR3_UART2RST_Pos)                /*!< 0x00000002 */
#define RCC_APBRSTR3_UART2RST                     RCC_APBRSTR3_UART2RST_Msk                         
#define RCC_APBRSTR3_USARTRST_Pos                 (6U)
#define RCC_APBRSTR3_USARTRST_Msk                 (0x1UL<<RCC_APBRSTR3_USARTRST_Pos)                /*!< 0x00000040 */
#define RCC_APBRSTR3_USARTRST                     RCC_APBRSTR3_USARTRST_Msk                         
#define RCC_APBRSTR3_LPUARTRST_Pos                (12U)
#define RCC_APBRSTR3_LPUARTRST_Msk                (0x1UL<<RCC_APBRSTR3_LPUARTRST_Pos)               /*!< 0x00001000 */
#define RCC_APBRSTR3_LPUARTRST                    RCC_APBRSTR3_LPUARTRST_Msk                        
#define RCC_APBRSTR3_I2C1RST_Pos                  (16U)
#define RCC_APBRSTR3_I2C1RST_Msk                  (0x1UL<<RCC_APBRSTR3_I2C1RST_Pos)                 /*!< 0x00010000 */
#define RCC_APBRSTR3_I2C1RST                      RCC_APBRSTR3_I2C1RST_Msk                          
#define RCC_APBRSTR3_I2C2RST_Pos                  (17U)
#define RCC_APBRSTR3_I2C2RST_Msk                  (0x1UL<<RCC_APBRSTR3_I2C2RST_Pos)                 /*!< 0x00020000 */
#define RCC_APBRSTR3_I2C2RST                      RCC_APBRSTR3_I2C2RST_Msk                          
#define RCC_APBRSTR3_SPI1RST_Pos                  (22U)
#define RCC_APBRSTR3_SPI1RST_Msk                  (0x1UL<<RCC_APBRSTR3_SPI1RST_Pos)                 /*!< 0x00400000 */
#define RCC_APBRSTR3_SPI1RST                      RCC_APBRSTR3_SPI1RST_Msk                          
#define RCC_APBRSTR3_SPI2RST_Pos                  (23U)
#define RCC_APBRSTR3_SPI2RST_Msk                  (0x1UL<<RCC_APBRSTR3_SPI2RST_Pos)                 /*!< 0x00800000 */
#define RCC_APBRSTR3_SPI2RST                      RCC_APBRSTR3_SPI2RST_Msk                          
#define RCC_APBRSTR3_FDCANRST_Pos                   (28U)
#define RCC_APBRSTR3_FDCANRST_Msk                   (0x1UL<<RCC_APBRSTR3_FDCANRST_Pos)                  /*!< 0x10000000 */
#define RCC_APBRSTR3_FDCANRST                       RCC_APBRSTR3_FDCANRST_Msk                           

/********************************* Bit definition for RCC_APBRSTR4 register *****************************************/
#define RCC_APBRSTR4_SYSCFGRST_Pos                (0U)
#define RCC_APBRSTR4_SYSCFGRST_Msk                (0x1UL<<RCC_APBRSTR4_SYSCFGRST_Pos)               /*!< 0x00000001 */
#define RCC_APBRSTR4_SYSCFGRST                    RCC_APBRSTR4_SYSCFGRST_Msk                        
#define RCC_APBRSTR4_VREFBUFRST_Pos               (8U)
#define RCC_APBRSTR4_VREFBUFRST_Msk               (0x1UL<<RCC_APBRSTR4_VREFBUFRST_Pos)              /*!< 0x00000100 */
#define RCC_APBRSTR4_VREFBUFRST                   RCC_APBRSTR4_VREFBUFRST_Msk                       
#define RCC_APBRSTR4_PWRRST_Pos                   (9U)
#define RCC_APBRSTR4_PWRRST_Msk                   (0x1UL<<RCC_APBRSTR4_PWRRST_Pos)                  /*!< 0x00000200 */
#define RCC_APBRSTR4_PWRRST                       RCC_APBRSTR4_PWRRST_Msk                           
#define RCC_APBRSTR4_ADC1RST_Pos                  (11U)
#define RCC_APBRSTR4_ADC1RST_Msk                  (0x1UL<<RCC_APBRSTR4_ADC1RST_Pos)                 /*!< 0x00000800 */
#define RCC_APBRSTR4_ADC1RST                      RCC_APBRSTR4_ADC1RST_Msk                          
#define RCC_APBRSTR4_ADC2RST_Pos                  (12U)
#define RCC_APBRSTR4_ADC2RST_Msk                  (0x1UL<<RCC_APBRSTR4_ADC2RST_Pos)                 /*!< 0x00001000 */
#define RCC_APBRSTR4_ADC2RST                      RCC_APBRSTR4_ADC2RST_Msk                          
#define RCC_APBRSTR4_DACRST_Pos                   (16U)
#define RCC_APBRSTR4_DACRST_Msk                   (0x1UL<<RCC_APBRSTR4_DACRST_Pos)                  /*!< 0x00010000 */
#define RCC_APBRSTR4_DACRST                       RCC_APBRSTR4_DACRST_Msk                           
#define RCC_APBRSTR4_OPARST_Pos                   (20U)
#define RCC_APBRSTR4_OPARST_Msk                   (0x1UL<<RCC_APBRSTR4_OPARST_Pos)                  /*!< 0x00100000 */
#define RCC_APBRSTR4_OPARST                       RCC_APBRSTR4_OPARST_Msk                           
#define RCC_APBRSTR4_COMPRST_Pos                  (24U)
#define RCC_APBRSTR4_COMPRST_Msk                  (0x1UL<<RCC_APBRSTR4_COMPRST_Pos)                 /*!< 0x01000000 */
#define RCC_APBRSTR4_COMPRST                      RCC_APBRSTR4_COMPRST_Msk                          

/********************************* Bit definition for RCC_AHBENR1 register ******************************************/
#define RCC_AHBENR1_DMAEN_Pos                     (0U)
#define RCC_AHBENR1_DMAEN_Msk                     (0x1UL<<RCC_AHBENR1_DMAEN_Pos)                    /*!< 0x00000001 */
#define RCC_AHBENR1_DMAEN                         RCC_AHBENR1_DMAEN_Msk                             
#define RCC_AHBENR1_SRAMSMEN_Pos                  (5U)
#define RCC_AHBENR1_SRAMSMEN_Msk                  (0x1UL<<RCC_AHBENR1_SRAMSMEN_Pos)                 /*!< 0x00000020 */
#define RCC_AHBENR1_SRAMSMEN                      RCC_AHBENR1_SRAMSMEN_Msk                          
#define RCC_AHBENR1_CRCEN_Pos                     (16U)
#define RCC_AHBENR1_CRCEN_Msk                     (0x1UL<<RCC_AHBENR1_CRCEN_Pos)                    /*!< 0x00010000 */
#define RCC_AHBENR1_CRCEN                         RCC_AHBENR1_CRCEN_Msk                             

/********************************* Bit definition for RCC_AHBENR2 register ******************************************/
#define RCC_AHBENR2_GPIOAEN_Pos                   (0U)
#define RCC_AHBENR2_GPIOAEN_Msk                   (0x1UL<<RCC_AHBENR2_GPIOAEN_Pos)                  /*!< 0x00000001 */
#define RCC_AHBENR2_GPIOAEN                       RCC_AHBENR2_GPIOAEN_Msk                           
#define RCC_AHBENR2_GPIOBEN_Pos                   (1U)
#define RCC_AHBENR2_GPIOBEN_Msk                   (0x1UL<<RCC_AHBENR2_GPIOBEN_Pos)                  /*!< 0x00000002 */
#define RCC_AHBENR2_GPIOBEN                       RCC_AHBENR2_GPIOBEN_Msk                           
#define RCC_AHBENR2_GPIOCEN_Pos                   (2U)
#define RCC_AHBENR2_GPIOCEN_Msk                   (0x1UL<<RCC_AHBENR2_GPIOCEN_Pos)                  /*!< 0x00000004 */
#define RCC_AHBENR2_GPIOCEN                       RCC_AHBENR2_GPIOCEN_Msk                           
#define RCC_AHBENR2_GPIODEN_Pos                   (3U)
#define RCC_AHBENR2_GPIODEN_Msk                   (0x1UL<<RCC_AHBENR2_GPIODEN_Pos)                  /*!< 0x00000008 */
#define RCC_AHBENR2_GPIODEN                       RCC_AHBENR2_GPIODEN_Msk                           

/********************************* Bit definition for RCC_APBENR1 register ******************************************/
#define RCC_APBENR1_TIM1EN_Pos                    (1U)
#define RCC_APBENR1_TIM1EN_Msk                    (0x1UL<<RCC_APBENR1_TIM1EN_Pos)                   /*!< 0x00000002 */
#define RCC_APBENR1_TIM1EN                        RCC_APBENR1_TIM1EN_Msk                            
#define RCC_APBENR1_TIM2EN_Pos                    (2U)
#define RCC_APBENR1_TIM2EN_Msk                    (0x1UL<<RCC_APBENR1_TIM2EN_Pos)                   /*!< 0x00000004 */
#define RCC_APBENR1_TIM2EN                        RCC_APBENR1_TIM2EN_Msk                            
#define RCC_APBENR1_TIM3EN_Pos                    (3U)
#define RCC_APBENR1_TIM3EN_Msk                    (0x1UL<<RCC_APBENR1_TIM3EN_Pos)                   /*!< 0x00000008 */
#define RCC_APBENR1_TIM3EN                        RCC_APBENR1_TIM3EN_Msk                            
#define RCC_APBENR1_TIM6EN_Pos                    (6U)
#define RCC_APBENR1_TIM6EN_Msk                    (0x1UL<<RCC_APBENR1_TIM6EN_Pos)                   /*!< 0x00000040 */
#define RCC_APBENR1_TIM6EN                        RCC_APBENR1_TIM6EN_Msk                            
#define RCC_APBENR1_TIM7EN_Pos                    (7U)
#define RCC_APBENR1_TIM7EN_Msk                    (0x1UL<<RCC_APBENR1_TIM7EN_Pos)                   /*!< 0x00000080 */
#define RCC_APBENR1_TIM7EN                        RCC_APBENR1_TIM7EN_Msk                            
#define RCC_APBENR1_TIM8EN_Pos                    (8U)
#define RCC_APBENR1_TIM8EN_Msk                    (0x1UL<<RCC_APBENR1_TIM8EN_Pos)                   /*!< 0x00000100 */
#define RCC_APBENR1_TIM8EN                        RCC_APBENR1_TIM8EN_Msk                            

/********************************* Bit definition for RCC_APBENR2 register ******************************************/
#define RCC_APBENR2_EPWMEN_Pos                    (8U)
#define RCC_APBENR2_EPWMEN_Msk                    (0x1UL<<RCC_APBENR2_EPWMEN_Pos)                   /*!< 0x00000100 */
#define RCC_APBENR2_EPWMEN                        RCC_APBENR2_EPWMEN_Msk                           
#define RCC_APBENR2_LPTIMEN_Pos                   (16U)
#define RCC_APBENR2_LPTIMEN_Msk                   (0x1UL<<RCC_APBENR2_LPTIMEN_Pos)                  /*!< 0x00010000 */
#define RCC_APBENR2_LPTIMEN                       RCC_APBENR2_LPTIMEN_Msk                           
#define RCC_APBENR2_WWDGEN_Pos                    (31U)
#define RCC_APBENR2_WWDGEN_Msk                    (0x1UL<<RCC_APBENR2_WWDGEN_Pos)                   /*!< 0x80000000 */
#define RCC_APBENR2_WWDGEN                        RCC_APBENR2_WWDGEN_Msk                            

/********************************* Bit definition for RCC_APBENR3 register ******************************************/
#define RCC_APBENR3_UART1EN_Pos                   (0U)
#define RCC_APBENR3_UART1EN_Msk                   (0x1UL<<RCC_APBENR3_UART1EN_Pos)                  /*!< 0x00000001 */
#define RCC_APBENR3_UART1EN                       RCC_APBENR3_UART1EN_Msk                           
#define RCC_APBENR3_UART2EN_Pos                   (1U)
#define RCC_APBENR3_UART2EN_Msk                   (0x1UL<<RCC_APBENR3_UART2EN_Pos)                  /*!< 0x00000002 */
#define RCC_APBENR3_UART2EN                       RCC_APBENR3_UART2EN_Msk                           
#define RCC_APBENR3_USARTEN_Pos                   (6U)
#define RCC_APBENR3_USARTEN_Msk                   (0x1UL<<RCC_APBENR3_USARTEN_Pos)                  /*!< 0x00000040 */
#define RCC_APBENR3_USARTEN                       RCC_APBENR3_USARTEN_Msk                           
#define RCC_APBENR3_LPUARTEN_Pos                  (12U)
#define RCC_APBENR3_LPUARTEN_Msk                  (0x1UL<<RCC_APBENR3_LPUARTEN_Pos)                 /*!< 0x00001000 */
#define RCC_APBENR3_LPUARTEN                      RCC_APBENR3_LPUARTEN_Msk                          
#define RCC_APBENR3_I2C1EN_Pos                    (16U)
#define RCC_APBENR3_I2C1EN_Msk                    (0x1UL<<RCC_APBENR3_I2C1EN_Pos)                   /*!< 0x00010000 */
#define RCC_APBENR3_I2C1EN                        RCC_APBENR3_I2C1EN_Msk                            
#define RCC_APBENR3_I2C2EN_Pos                    (17U)
#define RCC_APBENR3_I2C2EN_Msk                    (0x1UL<<RCC_APBENR3_I2C2EN_Pos)                   /*!< 0x00020000 */
#define RCC_APBENR3_I2C2EN                        RCC_APBENR3_I2C2EN_Msk                            
#define RCC_APBENR3_SPI1EN_Pos                    (22U)
#define RCC_APBENR3_SPI1EN_Msk                    (0x1UL<<RCC_APBENR3_SPI1EN_Pos)                   /*!< 0x00400000 */
#define RCC_APBENR3_SPI1EN                        RCC_APBENR3_SPI1EN_Msk                            
#define RCC_APBENR3_SPI2EN_Pos                    (23U)
#define RCC_APBENR3_SPI2EN_Msk                    (0x1UL<<RCC_APBENR3_SPI2EN_Pos)                   /*!< 0x00800000 */
#define RCC_APBENR3_SPI2EN                        RCC_APBENR3_SPI2EN_Msk                            
#define RCC_APBENR3_FDCANEN_Pos                     (28U)
#define RCC_APBENR3_FDCANEN_Msk                     (0x1UL<<RCC_APBENR3_FDCANEN_Pos)                    /*!< 0x10000000 */
#define RCC_APBENR3_FDCANEN                         RCC_APBENR3_FDCANEN_Msk                             

/********************************* Bit definition for RCC_APBENR4 register ******************************************/
#define RCC_APBENR4_SYSCFGEN_Pos                  (0U)
#define RCC_APBENR4_SYSCFGEN_Msk                  (0x1UL<<RCC_APBENR4_SYSCFGEN_Pos)                 /*!< 0x00000001 */
#define RCC_APBENR4_SYSCFGEN                      RCC_APBENR4_SYSCFGEN_Msk                          
#define RCC_APBENR4_VREFBUFEN_Pos                 (8U)
#define RCC_APBENR4_VREFBUFEN_Msk                 (0x1UL<<RCC_APBENR4_VREFBUFEN_Pos)                /*!< 0x00000100 */
#define RCC_APBENR4_VREFBUFEN                     RCC_APBENR4_VREFBUFEN_Msk                         
#define RCC_APBENR4_PWREN_Pos                     (9U)
#define RCC_APBENR4_PWREN_Msk                     (0x1UL<<RCC_APBENR4_PWREN_Pos)                    /*!< 0x00000200 */
#define RCC_APBENR4_PWREN                         RCC_APBENR4_PWREN_Msk                             
#define RCC_APBENR4_ADC1EN_Pos                    (11U)
#define RCC_APBENR4_ADC1EN_Msk                    (0x1UL<<RCC_APBENR4_ADC1EN_Pos)                   /*!< 0x00000800 */
#define RCC_APBENR4_ADC1EN                        RCC_APBENR4_ADC1EN_Msk                            
#define RCC_APBENR4_ADC2EN_Pos                    (12U)
#define RCC_APBENR4_ADC2EN_Msk                    (0x1UL<<RCC_APBENR4_ADC2EN_Pos)                   /*!< 0x00001000 */
#define RCC_APBENR4_ADC2EN                        RCC_APBENR4_ADC2EN_Msk                            
#define RCC_APBENR4_DACEN_Pos                     (16U)
#define RCC_APBENR4_DACEN_Msk                     (0x1UL<<RCC_APBENR4_DACEN_Pos)                    /*!< 0x00010000 */
#define RCC_APBENR4_DACEN                         RCC_APBENR4_DACEN_Msk                             
#define RCC_APBENR4_OPAEN_Pos                     (20U)
#define RCC_APBENR4_OPAEN_Msk                     (0x1UL<<RCC_APBENR4_OPAEN_Pos)                    /*!< 0x00100000 */
#define RCC_APBENR4_OPAEN                         RCC_APBENR4_OPAEN_Msk                             
#define RCC_APBENR4_COMPEN_Pos                    (24U)
#define RCC_APBENR4_COMPEN_Msk                    (0x1UL<<RCC_APBENR4_COMPEN_Pos)                   /*!< 0x01000000 */
#define RCC_APBENR4_COMPEN                        RCC_APBENR4_COMPEN_Msk                            

/********************************* Bit definition for RCC_CCIPR1 register *******************************************/
#define RCC_CCIPR1_USARTSEL_Pos                   (0U)
#define RCC_CCIPR1_USARTSEL_Msk                   (0x3UL<<RCC_CCIPR1_USARTSEL_Pos)                  /*!< 0x00000003 */
#define RCC_CCIPR1_USARTSEL                       RCC_CCIPR1_USARTSEL_Msk
#define RCC_CCIPR1_USARTSEL_0                     (0x1UL<<RCC_CCIPR1_USARTSEL_Pos)                  /*!< 0x00000001 */
#define RCC_CCIPR1_USARTSEL_1                     (0x2UL<<RCC_CCIPR1_USARTSEL_Pos)                  /*!< 0x00000002 */
#define RCC_CCIPR1_LPUARTSEL_Pos                  (12U)
#define RCC_CCIPR1_LPUARTSEL_Msk                  (0x3UL<<RCC_CCIPR1_LPUARTSEL_Pos)                 /*!< 0x00003000 */
#define RCC_CCIPR1_LPUARTSEL                      RCC_CCIPR1_LPUARTSEL_Msk
#define RCC_CCIPR1_LPUARTSEL_0                    (0x1UL<<RCC_CCIPR1_LPUARTSEL_Pos)                 /*!< 0x00001000 */
#define RCC_CCIPR1_LPUARTSEL_1                    (0x2UL<<RCC_CCIPR1_LPUARTSEL_Pos)                 /*!< 0x00002000 */
#define RCC_CCIPR1_COMP1SEL_Pos                   (20U)
#define RCC_CCIPR1_COMP1SEL_Msk                   (0x3UL<<RCC_CCIPR1_COMP1SEL_Pos)                  /*!< 0x00300000 */
#define RCC_CCIPR1_COMP1SEL                       RCC_CCIPR1_COMP1SEL_Msk
#define RCC_CCIPR1_COMP1SEL_0                     (0x1UL<<RCC_CCIPR1_COMP1SEL_Pos)                  /*!< 0x00100000 */
#define RCC_CCIPR1_COMP1SEL_1                     (0x2UL<<RCC_CCIPR1_COMP1SEL_Pos)                  /*!< 0x00200000 */
#define RCC_CCIPR1_COMP2SEL_Pos                   (22U)
#define RCC_CCIPR1_COMP2SEL_Msk                   (0x3UL<<RCC_CCIPR1_COMP2SEL_Pos)                  /*!< 0x00C00000 */
#define RCC_CCIPR1_COMP2SEL                       RCC_CCIPR1_COMP2SEL_Msk
#define RCC_CCIPR1_COMP2SEL_0                     (0x1UL<<RCC_CCIPR1_COMP2SEL_Pos)                  /*!< 0x00400000 */
#define RCC_CCIPR1_COMP2SEL_1                     (0x2UL<<RCC_CCIPR1_COMP2SEL_Pos)                  /*!< 0x00800000 */
#define RCC_CCIPR1_COMP3SEL_Pos                   (24U)
#define RCC_CCIPR1_COMP3SEL_Msk                   (0x3UL<<RCC_CCIPR1_COMP3SEL_Pos)                  /*!< 0x03000000 */
#define RCC_CCIPR1_COMP3SEL                       RCC_CCIPR1_COMP3SEL_Msk
#define RCC_CCIPR1_COMP3SEL_0                     (0x1UL<<RCC_CCIPR1_COMP3SEL_Pos)                  /*!< 0x01000000 */
#define RCC_CCIPR1_COMP3SEL_1                     (0x2UL<<RCC_CCIPR1_COMP3SEL_Pos)                  /*!< 0x02000000 */
#define RCC_CCIPR1_COMP4SEL_Pos                   (26U)
#define RCC_CCIPR1_COMP4SEL_Msk                   (0x3UL<<RCC_CCIPR1_COMP4SEL_Pos)                  /*!< 0x0C000000 */
#define RCC_CCIPR1_COMP4SEL                       RCC_CCIPR1_COMP4SEL_Msk
#define RCC_CCIPR1_COMP4SEL_0                     (0x1UL<<RCC_CCIPR1_COMP4SEL_Pos)                  /*!< 0x04000000 */
#define RCC_CCIPR1_COMP4SEL_1                     (0x2UL<<RCC_CCIPR1_COMP4SEL_Pos)                  /*!< 0x08000000 */
#define RCC_CCIPR1_TIMCLKCTRL_Pos                 (28U)
#define RCC_CCIPR1_TIMCLKCTRL_Msk                 (0x1UL<<RCC_CCIPR1_TIMCLKCTRL_Pos)                /*!< 0x10000000 */
#define RCC_CCIPR1_TIMCLKCTRL                     RCC_CCIPR1_TIMCLKCTRL_Msk                         
#define RCC_CCIPR1_PVDSEL_Pos                     (29U)
#define RCC_CCIPR1_PVDSEL_Msk                     (0x3UL<<RCC_CCIPR1_PVDSEL_Pos)                    /*!< 0x60000000 */
#define RCC_CCIPR1_PVDSEL                         RCC_CCIPR1_PVDSEL_Msk
#define RCC_CCIPR1_PVDSEL_0                       (0x1UL<<RCC_CCIPR1_PVDSEL_Pos)                    /*!< 0x20000000 */
#define RCC_CCIPR1_PVDSEL_1                       (0x2UL<<RCC_CCIPR1_PVDSEL_Pos)                    /*!< 0x40000000 */

/********************************* Bit definition for RCC_CCIPR2 register *******************************************/
#define RCC_CCIPR2_FDCANCKSEL_Pos                   (0U)
#define RCC_CCIPR2_FDCANCKSEL_Msk                   (0x3UL<<RCC_CCIPR2_FDCANCKSEL_Pos)                  /*!< 0x00000003 */
#define RCC_CCIPR2_FDCANCKSEL                       RCC_CCIPR2_FDCANCKSEL_Msk
#define RCC_CCIPR2_FDCANCKSEL_0                     (0x1UL<<RCC_CCIPR2_FDCANCKSEL_Pos)                  /*!< 0x00000001 */
#define RCC_CCIPR2_FDCANCKSEL_1                     (0x2UL<<RCC_CCIPR2_FDCANCKSEL_Pos)                  /*!< 0x00000002 */
#define RCC_CCIPR2_ADC12SEL_Pos                   (8U)
#define RCC_CCIPR2_ADC12SEL_Msk                   (0x3UL<<RCC_CCIPR2_ADC12SEL_Pos)                  /*!< 0x00000300 */
#define RCC_CCIPR2_ADC12SEL                       RCC_CCIPR2_ADC12SEL_Msk
#define RCC_CCIPR2_ADC12SEL_0                     (0x1UL<<RCC_CCIPR2_ADC12SEL_Pos)                  /*!< 0x00000100 */
#define RCC_CCIPR2_ADC12SEL_1                     (0x2UL<<RCC_CCIPR2_ADC12SEL_Pos)                  /*!< 0x00000200 */
#define RCC_CCIPR2_ADC1KEN_Pos                    (10U)
#define RCC_CCIPR2_ADC1KEN_Msk                    (0x1UL<<RCC_CCIPR2_ADC1KEN_Pos)                   /*!< 0x00000400 */
#define RCC_CCIPR2_ADC1KEN                        RCC_CCIPR2_ADC1KEN_Msk                            
#define RCC_CCIPR2_ADC2KEN_Pos                    (14U)
#define RCC_CCIPR2_ADC2KEN_Msk                    (0x1UL<<RCC_CCIPR2_ADC2KEN_Pos)                   /*!< 0x00004000 */
#define RCC_CCIPR2_ADC2KEN                        RCC_CCIPR2_ADC2KEN_Msk                            
#define RCC_CCIPR2_LPTIMSEL_Pos                   (16U)
#define RCC_CCIPR2_LPTIMSEL_Msk                   (0x3UL<<RCC_CCIPR2_LPTIMSEL_Pos)                  /*!< 0x00030000 */
#define RCC_CCIPR2_LPTIMSEL                       RCC_CCIPR2_LPTIMSEL_Msk
#define RCC_CCIPR2_LPTIMSEL_0                     (0x1UL<<RCC_CCIPR2_LPTIMSEL_Pos)                  /*!< 0x00010000 */
#define RCC_CCIPR2_LPTIMSEL_1                     (0x2UL<<RCC_CCIPR2_LPTIMSEL_Pos)                  /*!< 0x00020000 */
#define RCC_CCIPR2_RTC_HSEDIV_SEL_Pos             (22U)
#define RCC_CCIPR2_RTC_HSEDIV_SEL_Msk             (0x3UL<<RCC_CCIPR2_RTC_HSEDIV_SEL_Pos)            /*!< 0x00C00000 */
#define RCC_CCIPR2_RTC_HSEDIV_SEL                 RCC_CCIPR2_RTC_HSEDIV_SEL_Msk
#define RCC_CCIPR2_RTC_HSEDIV_SEL_0               (0x1UL<<RCC_CCIPR2_RTC_HSEDIV_SEL_Pos)            /*!< 0x00400000 */
#define RCC_CCIPR2_RTC_HSEDIV_SEL_1               (0x2UL<<RCC_CCIPR2_RTC_HSEDIV_SEL_Pos)            /*!< 0x00800000 */
#define RCC_CCIPR2_EPWM_TBCLKSYNC_Pos             (31U)
#define RCC_CCIPR2_EPWM_TBCLKSYNC_Msk             (0x1UL<<RCC_CCIPR2_EPWM_TBCLKSYNC_Pos)            /*!< 0x80000000 */
#define RCC_CCIPR2_EPWM_TBCLKSYNC                 RCC_CCIPR2_EPWM_TBCLKSYNC_Msk                    

/********************************* Bit definition for RCC_CCIPR3 register *******************************************/
#define RCC_CCIPR3_PLL_ADC_DIV_Pos                (0U)
#define RCC_CCIPR3_PLL_ADC_DIV_Msk                (0x3UL<<RCC_CCIPR3_PLL_ADC_DIV_Pos)               /*!< 0x00000003 */
#define RCC_CCIPR3_PLL_ADC_DIV                    RCC_CCIPR3_PLL_ADC_DIV_Msk
#define RCC_CCIPR3_PLL_ADC_DIV_0                  (0x1UL<<RCC_CCIPR3_PLL_ADC_DIV_Pos)               /*!< 0x00000001 */
#define RCC_CCIPR3_PLL_ADC_DIV_1                  (0x2UL<<RCC_CCIPR3_PLL_ADC_DIV_Pos)               /*!< 0x00000002 */
#define RCC_CCIPR3_PLL_FDCAN_DIV_Pos                (24U)
#define RCC_CCIPR3_PLL_FDCAN_DIV_Msk                (0xFUL<<RCC_CCIPR3_PLL_FDCAN_DIV_Pos)               /*!< 0x0F000000 */
#define RCC_CCIPR3_PLL_FDCAN_DIV                    RCC_CCIPR3_PLL_FDCAN_DIV_Msk
#define RCC_CCIPR3_PLL_FDCAN_DIV_0                  (0x1UL<<RCC_CCIPR3_PLL_FDCAN_DIV_Pos)               /*!< 0x01000000 */
#define RCC_CCIPR3_PLL_FDCAN_DIV_1                  (0x2UL<<RCC_CCIPR3_PLL_FDCAN_DIV_Pos)               /*!< 0x02000000 */
#define RCC_CCIPR3_PLL_FDCAN_DIV_2                  (0x4UL<<RCC_CCIPR3_PLL_FDCAN_DIV_Pos)               /*!< 0x04000000 */
#define RCC_CCIPR3_PLL_FDCAN_DIV_3                  (0x8UL<<RCC_CCIPR3_PLL_FDCAN_DIV_Pos)               /*!< 0x08000000 */

/********************************* Bit definition for RCC_BDCR register *********************************************/
#define RCC_BDCR_LSEON_Pos                        (0U)
#define RCC_BDCR_LSEON_Msk                        (0x1UL<<RCC_BDCR_LSEON_Pos)                       /*!< 0x00000001 */
#define RCC_BDCR_LSEON                            RCC_BDCR_LSEON_Msk                                
#define RCC_BDCR_LSERDY_Pos                       (1U)
#define RCC_BDCR_LSERDY_Msk                       (0x1UL<<RCC_BDCR_LSERDY_Pos)                      /*!< 0x00000002 */
#define RCC_BDCR_LSERDY                           RCC_BDCR_LSERDY_Msk                               
#define RCC_BDCR_LSEBYP_Pos                       (2U)
#define RCC_BDCR_LSEBYP_Msk                       (0x1UL<<RCC_BDCR_LSEBYP_Pos)                      /*!< 0x00000004 */
#define RCC_BDCR_LSEBYP                           RCC_BDCR_LSEBYP_Msk                               
#define RCC_BDCR_LSEDRV_Pos                       (3U)
#define RCC_BDCR_LSEDRV_Msk                       (0x3UL<<RCC_BDCR_LSEDRV_Pos)                      /*!< 0x00000018 */
#define RCC_BDCR_LSEDRV                           RCC_BDCR_LSEDRV_Msk
#define RCC_BDCR_LSEDRV_0                         (0x1UL<<RCC_BDCR_LSEDRV_Pos)                      /*!< 0x00000008 */
#define RCC_BDCR_LSEDRV_1                         (0x2UL<<RCC_BDCR_LSEDRV_Pos)                      /*!< 0x00000010 */
#define RCC_BDCR_LSECSSON_Pos                     (5U)
#define RCC_BDCR_LSECSSON_Msk                     (0x1UL<<RCC_BDCR_LSECSSON_Pos)                    /*!< 0x00000020 */
#define RCC_BDCR_LSECSSON                         RCC_BDCR_LSECSSON_Msk                             
#define RCC_BDCR_LSECSSD_Pos                      (6U)
#define RCC_BDCR_LSECSSD_Msk                      (0x1UL<<RCC_BDCR_LSECSSD_Pos)                     /*!< 0x00000040 */
#define RCC_BDCR_LSECSSD                          RCC_BDCR_LSECSSD_Msk                              
#define RCC_BDCR_RTCSEL_Pos                       (8U)
#define RCC_BDCR_RTCSEL_Msk                       (0x3UL<<RCC_BDCR_RTCSEL_Pos)                      /*!< 0x00000300 */
#define RCC_BDCR_RTCSEL                           RCC_BDCR_RTCSEL_Msk
#define RCC_BDCR_RTCSEL_0                         (0x1UL<<RCC_BDCR_RTCSEL_Pos)                      /*!< 0x00000100 */
#define RCC_BDCR_RTCSEL_1                         (0x2UL<<RCC_BDCR_RTCSEL_Pos)                      /*!< 0x00000200 */
#define RCC_BDCR_RTCEN_Pos                        (15U)
#define RCC_BDCR_RTCEN_Msk                        (0x1UL<<RCC_BDCR_RTCEN_Pos)                       /*!< 0x00008000 */
#define RCC_BDCR_RTCEN                            RCC_BDCR_RTCEN_Msk                                
#define RCC_BDCR_BDRST_Pos                        (16U)
#define RCC_BDCR_BDRST_Msk                        (0x1UL<<RCC_BDCR_BDRST_Pos)                       /*!< 0x00010000 */
#define RCC_BDCR_BDRST                            RCC_BDCR_BDRST_Msk                                
#define RCC_BDCR_LSI_TRIMCR_Pos                   (17U)
#define RCC_BDCR_LSI_TRIMCR_Msk                   (0x1FFUL<<RCC_BDCR_LSI_TRIMCR_Pos)                /*!< 0x03FE0000 */
#define RCC_BDCR_LSI_TRIMCR                       RCC_BDCR_LSI_TRIMCR_Msk
#define RCC_BDCR_LSION_Pos                        (26U)
#define RCC_BDCR_LSION_Msk                        (0x1UL<<RCC_BDCR_LSION_Pos)                       /*!< 0x04000000 */
#define RCC_BDCR_LSION                            RCC_BDCR_LSION_Msk                                
#define RCC_BDCR_LSIRDY_Pos                       (27U)
#define RCC_BDCR_LSIRDY_Msk                       (0x1UL<<RCC_BDCR_LSIRDY_Pos)                      /*!< 0x08000000 */
#define RCC_BDCR_LSIRDY                           RCC_BDCR_LSIRDY_Msk                               
#define RCC_BDCR_LSE_RDYSEL_Pos                   (28U)
#define RCC_BDCR_LSE_RDYSEL_Msk                   (0x3UL<<RCC_BDCR_LSE_RDYSEL_Pos)                  /*!< 0x30000000 */
#define RCC_BDCR_LSE_RDYSEL                       RCC_BDCR_LSE_RDYSEL_Msk
#define RCC_BDCR_LSE_RDYSEL_0                     (0x1UL<<RCC_BDCR_LSE_RDYSEL_Pos)                  /*!< 0x10000000 */
#define RCC_BDCR_LSE_RDYSEL_1                     (0x2UL<<RCC_BDCR_LSE_RDYSEL_Pos)                  /*!< 0x20000000 */

/********************************* Bit definition for RCC_CSR register **********************************************/
#define RCC_CSR_NRST_FLTDIS_Pos                   (0U)
#define RCC_CSR_NRST_FLTDIS_Msk                   (0x1UL<<RCC_CSR_NRST_FLTDIS_Pos)                  /*!< 0x00000001 */
#define RCC_CSR_NRST_FLTDIS                       RCC_CSR_NRST_FLTDIS_Msk                           
#define RCC_CSR_EPWM_SFTRST_RELEASE_Pos           (4U)
#define RCC_CSR_EPWM_SFTRST_RELEASE_Msk           (0x1UL<<RCC_CSR_EPWM_SFTRST_RELEASE_Pos)          /*!< 0x00000010 */
#define RCC_CSR_EPWM_SFTRST_RELEASE               RCC_CSR_EPWM_SFTRST_RELEASE_Msk                  
#define RCC_CSR_EPWM_PRST_RELEASE_Pos             (5U)
#define RCC_CSR_EPWM_PRST_RELEASE_Msk             (0x1UL<<RCC_CSR_EPWM_PRST_RELEASE_Pos)            /*!< 0x00000020 */
#define RCC_CSR_EPWM_PRST_RELEASE                 RCC_CSR_EPWM_PRST_RELEASE_Msk                    
#define RCC_CSR_RMVF_Pos                          (8U)
#define RCC_CSR_RMVF_Msk                          (0x1UL<<RCC_CSR_RMVF_Pos)                         /*!< 0x00000100 */
#define RCC_CSR_RMVF                              RCC_CSR_RMVF_Msk                                  
#define RCC_CSR_PLLULRSTF_Pos                     (19U)
#define RCC_CSR_PLLULRSTF_Msk                     (0x1UL<<RCC_CSR_PLLULRSTF_Pos)                    /*!< 0x00080000 */
#define RCC_CSR_PLLULRSTF                         RCC_CSR_PLLULRSTF_Msk                             
#define RCC_CSR_OBLRSTF_Pos                       (25U)
#define RCC_CSR_OBLRSTF_Msk                       (0x1UL<<RCC_CSR_OBLRSTF_Pos)                      /*!< 0x02000000 */
#define RCC_CSR_OBLRSTF                           RCC_CSR_OBLRSTF_Msk                               
#define RCC_CSR_PINRSTF_Pos                       (26U)
#define RCC_CSR_PINRSTF_Msk                       (0x1UL<<RCC_CSR_PINRSTF_Pos)                      /*!< 0x04000000 */
#define RCC_CSR_PINRSTF                           RCC_CSR_PINRSTF_Msk                               
#define RCC_CSR_PWRRSTF_Pos                       (27U)
#define RCC_CSR_PWRRSTF_Msk                       (0x1UL<<RCC_CSR_PWRRSTF_Pos)                      /*!< 0x08000000 */
#define RCC_CSR_PWRRSTF                           RCC_CSR_PWRRSTF_Msk                               
#define RCC_CSR_SFTRSTF_Pos                       (28U)
#define RCC_CSR_SFTRSTF_Msk                       (0x1UL<<RCC_CSR_SFTRSTF_Pos)                      /*!< 0x10000000 */
#define RCC_CSR_SFTRSTF                           RCC_CSR_SFTRSTF_Msk                               
#define RCC_CSR_IWDGRSTF_Pos                      (29U)
#define RCC_CSR_IWDGRSTF_Msk                      (0x1UL<<RCC_CSR_IWDGRSTF_Pos)                     /*!< 0x20000000 */
#define RCC_CSR_IWDGRSTF                          RCC_CSR_IWDGRSTF_Msk                              
#define RCC_CSR_WWDGRSTF_Pos                      (30U)
#define RCC_CSR_WWDGRSTF_Msk                      (0x1UL<<RCC_CSR_WWDGRSTF_Pos)                     /*!< 0x40000000 */
#define RCC_CSR_WWDGRSTF                          RCC_CSR_WWDGRSTF_Msk                              
#define RCC_CSR_LPWRRSTF_Pos                      (31U)
#define RCC_CSR_LPWRRSTF_Msk                      (0x1UL<<RCC_CSR_LPWRRSTF_Pos)                     /*!< 0x80000000 */
#define RCC_CSR_LPWRRSTF                          RCC_CSR_LPWRRSTF_Msk                              

/********************************************************************************************************************/
/********************************* CRC ******************************************************************************/
/********************************************************************************************************************/

/********************************* Bit definition for CRC_DR register ***********************************************/
#define CRC_DR_DR_Pos                             (0U)
#define CRC_DR_DR_Msk                             (0xFFFFFFFFUL<<CRC_DR_DR_Pos)                     /*!< 0xFFFFFFFF */
#define CRC_DR_DR                                 CRC_DR_DR_Msk                                     /*!< CRC data */

/********************************* Bit definition for CRC_IDR register **********************************************/
#define CRC_IDR_IDR_Pos                           (0U)
#define CRC_IDR_IDR_Msk                           (0xFFUL<<CRC_IDR_IDR_Pos)                         /*!< 0x000000FF */
#define CRC_IDR_IDR                               CRC_IDR_IDR_Msk                                   /*!< CRC independent data */

/********************************* Bit definition for CRC_CR register ***********************************************/
#define CRC_CR_RESET_Pos                          (0U)
#define CRC_CR_RESET_Msk                          (0x1UL<<CRC_CR_RESET_Pos)                         /*!< 0x00000001 */
#define CRC_CR_RESET                              CRC_CR_RESET_Msk                                  /*!< CRC software reset */

/********************************************************************************************************************/
/********************************* GPIO *****************************************************************************/
/********************************************************************************************************************/

/********************************* Bit definition for GPIO_MODER register *******************************************/
#define GPIO_MODER_MODE0_Pos                      (0U)
#define GPIO_MODER_MODE0_Msk                      (0x3UL<<GPIO_MODER_MODE0_Pos)                     /*!< 0x00000003 */
#define GPIO_MODER_MODE0                          GPIO_MODER_MODE0_Msk                              /*!< GPIO0 MODE */
#define GPIO_MODER_MODE0_0                        (0x1UL<<GPIO_MODER_MODE0_Pos)                     /*!< 0x00000001 */
#define GPIO_MODER_MODE0_1                        (0x2UL<<GPIO_MODER_MODE0_Pos)                     /*!< 0x00000002 */
#define GPIO_MODER_MODE1_Pos                      (2U)
#define GPIO_MODER_MODE1_Msk                      (0x3UL<<GPIO_MODER_MODE1_Pos)                     /*!< 0x0000000C */
#define GPIO_MODER_MODE1                          GPIO_MODER_MODE1_Msk                              /*!< GPIO1 MODE */
#define GPIO_MODER_MODE1_0                        (0x1UL<<GPIO_MODER_MODE1_Pos)                     /*!< 0x00000004 */
#define GPIO_MODER_MODE1_1                        (0x2UL<<GPIO_MODER_MODE1_Pos)                     /*!< 0x00000008 */
#define GPIO_MODER_MODE2_Pos                      (4U)
#define GPIO_MODER_MODE2_Msk                      (0x3UL<<GPIO_MODER_MODE2_Pos)                     /*!< 0x00000030 */
#define GPIO_MODER_MODE2                          GPIO_MODER_MODE2_Msk                              /*!< GPIO2 MODE */
#define GPIO_MODER_MODE2_0                        (0x1UL<<GPIO_MODER_MODE2_Pos)                     /*!< 0x00000010 */
#define GPIO_MODER_MODE2_1                        (0x2UL<<GPIO_MODER_MODE2_Pos)                     /*!< 0x00000020 */
#define GPIO_MODER_MODE3_Pos                      (6U)
#define GPIO_MODER_MODE3_Msk                      (0x3UL<<GPIO_MODER_MODE3_Pos)                     /*!< 0x000000C0 */
#define GPIO_MODER_MODE3                          GPIO_MODER_MODE3_Msk                              /*!< GPIO3 MODE */
#define GPIO_MODER_MODE3_0                        (0x1UL<<GPIO_MODER_MODE3_Pos)                     /*!< 0x00000040 */
#define GPIO_MODER_MODE3_1                        (0x2UL<<GPIO_MODER_MODE3_Pos)                     /*!< 0x00000080 */
#define GPIO_MODER_MODE4_Pos                      (8U)
#define GPIO_MODER_MODE4_Msk                      (0x3UL<<GPIO_MODER_MODE4_Pos)                     /*!< 0x00000300 */
#define GPIO_MODER_MODE4                          GPIO_MODER_MODE4_Msk                              /*!< GPIO4 MODE */
#define GPIO_MODER_MODE4_0                        (0x1UL<<GPIO_MODER_MODE4_Pos)                     /*!< 0x00000100 */
#define GPIO_MODER_MODE4_1                        (0x2UL<<GPIO_MODER_MODE4_Pos)                     /*!< 0x00000200 */
#define GPIO_MODER_MODE5_Pos                      (10U)
#define GPIO_MODER_MODE5_Msk                      (0x3UL<<GPIO_MODER_MODE5_Pos)                     /*!< 0x00000C00 */
#define GPIO_MODER_MODE5                          GPIO_MODER_MODE5_Msk                              /*!< GPIO5 MODE */
#define GPIO_MODER_MODE5_0                        (0x1UL<<GPIO_MODER_MODE5_Pos)                     /*!< 0x00000400 */
#define GPIO_MODER_MODE5_1                        (0x2UL<<GPIO_MODER_MODE5_Pos)                     /*!< 0x00000800 */
#define GPIO_MODER_MODE6_Pos                      (12U)
#define GPIO_MODER_MODE6_Msk                      (0x3UL<<GPIO_MODER_MODE6_Pos)                     /*!< 0x00003000 */
#define GPIO_MODER_MODE6                          GPIO_MODER_MODE6_Msk                              /*!< GPIO6 MODE */
#define GPIO_MODER_MODE6_0                        (0x1UL<<GPIO_MODER_MODE6_Pos)                     /*!< 0x00001000 */
#define GPIO_MODER_MODE6_1                        (0x2UL<<GPIO_MODER_MODE6_Pos)                     /*!< 0x00002000 */
#define GPIO_MODER_MODE7_Pos                      (14U)
#define GPIO_MODER_MODE7_Msk                      (0x3UL<<GPIO_MODER_MODE7_Pos)                     /*!< 0x0000C000 */
#define GPIO_MODER_MODE7                          GPIO_MODER_MODE7_Msk                              /*!< GPIO7 MODE */
#define GPIO_MODER_MODE7_0                        (0x1UL<<GPIO_MODER_MODE7_Pos)                     /*!< 0x00004000 */
#define GPIO_MODER_MODE7_1                        (0x2UL<<GPIO_MODER_MODE7_Pos)                     /*!< 0x00008000 */
#define GPIO_MODER_MODE8_Pos                      (16U)
#define GPIO_MODER_MODE8_Msk                      (0x3UL<<GPIO_MODER_MODE8_Pos)                     /*!< 0x00030000 */
#define GPIO_MODER_MODE8                          GPIO_MODER_MODE8_Msk                              /*!< GPIO8 MODE */
#define GPIO_MODER_MODE8_0                        (0x1UL<<GPIO_MODER_MODE8_Pos)                     /*!< 0x00010000 */
#define GPIO_MODER_MODE8_1                        (0x2UL<<GPIO_MODER_MODE8_Pos)                     /*!< 0x00020000 */
#define GPIO_MODER_MODE9_Pos                      (18U)
#define GPIO_MODER_MODE9_Msk                      (0x3UL<<GPIO_MODER_MODE9_Pos)                     /*!< 0x000C0000 */
#define GPIO_MODER_MODE9                          GPIO_MODER_MODE9_Msk                              /*!< GPIO9 MODE */
#define GPIO_MODER_MODE9_0                        (0x1UL<<GPIO_MODER_MODE9_Pos)                     /*!< 0x00040000 */
#define GPIO_MODER_MODE9_1                        (0x2UL<<GPIO_MODER_MODE9_Pos)                     /*!< 0x00080000 */
#define GPIO_MODER_MODE10_Pos                     (20U)
#define GPIO_MODER_MODE10_Msk                     (0x3UL<<GPIO_MODER_MODE10_Pos)                    /*!< 0x00300000 */
#define GPIO_MODER_MODE10                         GPIO_MODER_MODE10_Msk                             /*!< GPIO10 MODE */
#define GPIO_MODER_MODE10_0                       (0x1UL<<GPIO_MODER_MODE10_Pos)                    /*!< 0x00100000 */
#define GPIO_MODER_MODE10_1                       (0x2UL<<GPIO_MODER_MODE10_Pos)                    /*!< 0x00200000 */
#define GPIO_MODER_MODE11_Pos                     (22U)
#define GPIO_MODER_MODE11_Msk                     (0x3UL<<GPIO_MODER_MODE11_Pos)                    /*!< 0x00C00000 */
#define GPIO_MODER_MODE11                         GPIO_MODER_MODE11_Msk                             /*!< GPIO11 MODE */
#define GPIO_MODER_MODE11_0                       (0x1UL<<GPIO_MODER_MODE11_Pos)                    /*!< 0x00400000 */
#define GPIO_MODER_MODE11_1                       (0x2UL<<GPIO_MODER_MODE11_Pos)                    /*!< 0x00800000 */
#define GPIO_MODER_MODE12_Pos                     (24U)
#define GPIO_MODER_MODE12_Msk                     (0x3UL<<GPIO_MODER_MODE12_Pos)                    /*!< 0x03000000 */
#define GPIO_MODER_MODE12                         GPIO_MODER_MODE12_Msk                             /*!< GPIO12 MODE */
#define GPIO_MODER_MODE12_0                       (0x1UL<<GPIO_MODER_MODE12_Pos)                    /*!< 0x01000000 */
#define GPIO_MODER_MODE12_1                       (0x2UL<<GPIO_MODER_MODE12_Pos)                    /*!< 0x02000000 */
#define GPIO_MODER_MODE13_Pos                     (26U)
#define GPIO_MODER_MODE13_Msk                     (0x3UL<<GPIO_MODER_MODE13_Pos)                    /*!< 0x0C000000 */
#define GPIO_MODER_MODE13                         GPIO_MODER_MODE13_Msk                             /*!< GPIO13 MODE */
#define GPIO_MODER_MODE13_0                       (0x1UL<<GPIO_MODER_MODE13_Pos)                    /*!< 0x04000000 */
#define GPIO_MODER_MODE13_1                       (0x2UL<<GPIO_MODER_MODE13_Pos)                    /*!< 0x08000000 */
#define GPIO_MODER_MODE14_Pos                     (28U)
#define GPIO_MODER_MODE14_Msk                     (0x3UL<<GPIO_MODER_MODE14_Pos)                    /*!< 0x30000000 */
#define GPIO_MODER_MODE14                         GPIO_MODER_MODE14_Msk                             /*!< GPIO14 MODE */
#define GPIO_MODER_MODE14_0                       (0x1UL<<GPIO_MODER_MODE14_Pos)                    /*!< 0x10000000 */
#define GPIO_MODER_MODE14_1                       (0x2UL<<GPIO_MODER_MODE14_Pos)                    /*!< 0x20000000 */
#define GPIO_MODER_MODE15_Pos                     (30U)
#define GPIO_MODER_MODE15_Msk                     (0x3UL<<GPIO_MODER_MODE15_Pos)                    /*!< 0xC0000000 */
#define GPIO_MODER_MODE15                         GPIO_MODER_MODE15_Msk                             /*!< GPIO15 MODE */
#define GPIO_MODER_MODE15_0                       (0x1UL<<GPIO_MODER_MODE15_Pos)                    /*!< 0x40000000 */
#define GPIO_MODER_MODE15_1                       (0x2UL<<GPIO_MODER_MODE15_Pos)                    /*!< 0x80000000 */

/********************************* Bit definition for GPIO_OTYPER register ******************************************/
#define GPIO_OTYPER_OT0_Pos                       (0U)
#define GPIO_OTYPER_OT0_Msk                       (0x1UL<<GPIO_OTYPER_OT0_Pos)                      /*!< 0x00000001 */
#define GPIO_OTYPER_OT0                           GPIO_OTYPER_OT0_Msk                               /*!< GPIO0 Output type */
#define GPIO_OTYPER_OT1_Pos                       (1U)
#define GPIO_OTYPER_OT1_Msk                       (0x1UL<<GPIO_OTYPER_OT1_Pos)                      /*!< 0x00000002 */
#define GPIO_OTYPER_OT1                           GPIO_OTYPER_OT1_Msk                               /*!< GPIO1 Output type */
#define GPIO_OTYPER_OT2_Pos                       (2U)
#define GPIO_OTYPER_OT2_Msk                       (0x1UL<<GPIO_OTYPER_OT2_Pos)                      /*!< 0x00000004 */
#define GPIO_OTYPER_OT2                           GPIO_OTYPER_OT2_Msk                               /*!< GPIO2 Output type */
#define GPIO_OTYPER_OT3_Pos                       (3U)
#define GPIO_OTYPER_OT3_Msk                       (0x1UL<<GPIO_OTYPER_OT3_Pos)                      /*!< 0x00000008 */
#define GPIO_OTYPER_OT3                           GPIO_OTYPER_OT3_Msk                               /*!< GPIO3 Output type */
#define GPIO_OTYPER_OT4_Pos                       (4U)
#define GPIO_OTYPER_OT4_Msk                       (0x1UL<<GPIO_OTYPER_OT4_Pos)                      /*!< 0x00000010 */
#define GPIO_OTYPER_OT4                           GPIO_OTYPER_OT4_Msk                               /*!< GPIO4 Output type */
#define GPIO_OTYPER_OT5_Pos                       (5U)
#define GPIO_OTYPER_OT5_Msk                       (0x1UL<<GPIO_OTYPER_OT5_Pos)                      /*!< 0x00000020 */
#define GPIO_OTYPER_OT5                           GPIO_OTYPER_OT5_Msk                               /*!< GPIO5 Output type */
#define GPIO_OTYPER_OT6_Pos                       (6U)
#define GPIO_OTYPER_OT6_Msk                       (0x1UL<<GPIO_OTYPER_OT6_Pos)                      /*!< 0x00000040 */
#define GPIO_OTYPER_OT6                           GPIO_OTYPER_OT6_Msk                               /*!< GPIO6 Output type */
#define GPIO_OTYPER_OT7_Pos                       (7U)
#define GPIO_OTYPER_OT7_Msk                       (0x1UL<<GPIO_OTYPER_OT7_Pos)                      /*!< 0x00000080 */
#define GPIO_OTYPER_OT7                           GPIO_OTYPER_OT7_Msk                               /*!< GPIO7 Output type */
#define GPIO_OTYPER_OT8_Pos                       (8U)
#define GPIO_OTYPER_OT8_Msk                       (0x1UL<<GPIO_OTYPER_OT8_Pos)                      /*!< 0x00000100 */
#define GPIO_OTYPER_OT8                           GPIO_OTYPER_OT8_Msk                               /*!< GPIO8 Output type */
#define GPIO_OTYPER_OT9_Pos                       (9U)
#define GPIO_OTYPER_OT9_Msk                       (0x1UL<<GPIO_OTYPER_OT9_Pos)                      /*!< 0x00000200 */
#define GPIO_OTYPER_OT9                           GPIO_OTYPER_OT9_Msk                               /*!< GPIO9 Output type */
#define GPIO_OTYPER_OT10_Pos                      (10U)
#define GPIO_OTYPER_OT10_Msk                      (0x1UL<<GPIO_OTYPER_OT10_Pos)                     /*!< 0x00000400 */
#define GPIO_OTYPER_OT10                          GPIO_OTYPER_OT10_Msk                              /*!< GPIO10 Output type */
#define GPIO_OTYPER_OT11_Pos                      (11U)
#define GPIO_OTYPER_OT11_Msk                      (0x1UL<<GPIO_OTYPER_OT11_Pos)                     /*!< 0x00000800 */
#define GPIO_OTYPER_OT11                          GPIO_OTYPER_OT11_Msk                              /*!< GPIO11 Output type */
#define GPIO_OTYPER_OT12_Pos                      (12U)
#define GPIO_OTYPER_OT12_Msk                      (0x1UL<<GPIO_OTYPER_OT12_Pos)                     /*!< 0x00001000 */
#define GPIO_OTYPER_OT12                          GPIO_OTYPER_OT12_Msk                              /*!< GPIO12 Output type */
#define GPIO_OTYPER_OT13_Pos                      (13U)
#define GPIO_OTYPER_OT13_Msk                      (0x1UL<<GPIO_OTYPER_OT13_Pos)                     /*!< 0x00002000 */
#define GPIO_OTYPER_OT13                          GPIO_OTYPER_OT13_Msk                              /*!< GPIO13 Output type */
#define GPIO_OTYPER_OT14_Pos                      (14U)
#define GPIO_OTYPER_OT14_Msk                      (0x1UL<<GPIO_OTYPER_OT14_Pos)                     /*!< 0x00004000 */
#define GPIO_OTYPER_OT14                          GPIO_OTYPER_OT14_Msk                              /*!< GPIO14 Output type */
#define GPIO_OTYPER_OT15_Pos                      (15U)
#define GPIO_OTYPER_OT15_Msk                      (0x1UL<<GPIO_OTYPER_OT15_Pos)                     /*!< 0x00008000 */
#define GPIO_OTYPER_OT15                          GPIO_OTYPER_OT15_Msk                              /*!< GPIO15 Output type */

/********************************* Bit definition for GPIO_OSPEEDR register *****************************************/
#define GPIO_OSPEEDR_OSPEED0_Pos                  (0U)
#define GPIO_OSPEEDR_OSPEED0_Msk                  (0x3UL<<GPIO_OSPEEDR_OSPEED0_Pos)                 /*!< 0x00000003 */
#define GPIO_OSPEEDR_OSPEED0                      GPIO_OSPEEDR_OSPEED0_Msk                          /*!< GPIO0 output speed */
#define GPIO_OSPEEDR_OSPEED0_0                    (0x1UL<<GPIO_OSPEEDR_OSPEED0_Pos)                 /*!< 0x00000001 */
#define GPIO_OSPEEDR_OSPEED0_1                    (0x2UL<<GPIO_OSPEEDR_OSPEED0_Pos)                 /*!< 0x00000002 */
#define GPIO_OSPEEDR_OSPEED1_Pos                  (2U)
#define GPIO_OSPEEDR_OSPEED1_Msk                  (0x3UL<<GPIO_OSPEEDR_OSPEED1_Pos)                 /*!< 0x0000000C */
#define GPIO_OSPEEDR_OSPEED1                      GPIO_OSPEEDR_OSPEED1_Msk                          /*!< GPIO1 output speed */
#define GPIO_OSPEEDR_OSPEED1_0                    (0x1UL<<GPIO_OSPEEDR_OSPEED1_Pos)                 /*!< 0x00000004 */
#define GPIO_OSPEEDR_OSPEED1_1                    (0x2UL<<GPIO_OSPEEDR_OSPEED1_Pos)                 /*!< 0x00000008 */
#define GPIO_OSPEEDR_OSPEED2_Pos                  (4U)
#define GPIO_OSPEEDR_OSPEED2_Msk                  (0x3UL<<GPIO_OSPEEDR_OSPEED2_Pos)                 /*!< 0x00000030 */
#define GPIO_OSPEEDR_OSPEED2                      GPIO_OSPEEDR_OSPEED2_Msk                          /*!< GPIO2 output speed */
#define GPIO_OSPEEDR_OSPEED2_0                    (0x1UL<<GPIO_OSPEEDR_OSPEED2_Pos)                 /*!< 0x00000010 */
#define GPIO_OSPEEDR_OSPEED2_1                    (0x2UL<<GPIO_OSPEEDR_OSPEED2_Pos)                 /*!< 0x00000020 */
#define GPIO_OSPEEDR_OSPEED3_Pos                  (6U)
#define GPIO_OSPEEDR_OSPEED3_Msk                  (0x3UL<<GPIO_OSPEEDR_OSPEED3_Pos)                 /*!< 0x000000C0 */
#define GPIO_OSPEEDR_OSPEED3                      GPIO_OSPEEDR_OSPEED3_Msk                          /*!< GPIO3 output speed */
#define GPIO_OSPEEDR_OSPEED3_0                    (0x1UL<<GPIO_OSPEEDR_OSPEED3_Pos)                 /*!< 0x00000040 */
#define GPIO_OSPEEDR_OSPEED3_1                    (0x2UL<<GPIO_OSPEEDR_OSPEED3_Pos)                 /*!< 0x00000080 */
#define GPIO_OSPEEDR_OSPEED4_Pos                  (8U)
#define GPIO_OSPEEDR_OSPEED4_Msk                  (0x3UL<<GPIO_OSPEEDR_OSPEED4_Pos)                 /*!< 0x00000300 */
#define GPIO_OSPEEDR_OSPEED4                      GPIO_OSPEEDR_OSPEED4_Msk                          /*!< GPIO4 output speed */
#define GPIO_OSPEEDR_OSPEED4_0                    (0x1UL<<GPIO_OSPEEDR_OSPEED4_Pos)                 /*!< 0x00000100 */
#define GPIO_OSPEEDR_OSPEED4_1                    (0x2UL<<GPIO_OSPEEDR_OSPEED4_Pos)                 /*!< 0x00000200 */
#define GPIO_OSPEEDR_OSPEED5_Pos                  (10U)
#define GPIO_OSPEEDR_OSPEED5_Msk                  (0x3UL<<GPIO_OSPEEDR_OSPEED5_Pos)                 /*!< 0x00000C00 */
#define GPIO_OSPEEDR_OSPEED5                      GPIO_OSPEEDR_OSPEED5_Msk                          /*!< GPIO5 output speed */
#define GPIO_OSPEEDR_OSPEED5_0                    (0x1UL<<GPIO_OSPEEDR_OSPEED5_Pos)                 /*!< 0x00000400 */
#define GPIO_OSPEEDR_OSPEED5_1                    (0x2UL<<GPIO_OSPEEDR_OSPEED5_Pos)                 /*!< 0x00000800 */
#define GPIO_OSPEEDR_OSPEED6_Pos                  (12U)
#define GPIO_OSPEEDR_OSPEED6_Msk                  (0x3UL<<GPIO_OSPEEDR_OSPEED6_Pos)                 /*!< 0x00003000 */
#define GPIO_OSPEEDR_OSPEED6                      GPIO_OSPEEDR_OSPEED6_Msk                          /*!< GPIO6 output speed */
#define GPIO_OSPEEDR_OSPEED6_0                    (0x1UL<<GPIO_OSPEEDR_OSPEED6_Pos)                 /*!< 0x00001000 */
#define GPIO_OSPEEDR_OSPEED6_1                    (0x2UL<<GPIO_OSPEEDR_OSPEED6_Pos)                 /*!< 0x00002000 */
#define GPIO_OSPEEDR_OSPEED7_Pos                  (14U)
#define GPIO_OSPEEDR_OSPEED7_Msk                  (0x3UL<<GPIO_OSPEEDR_OSPEED7_Pos)                 /*!< 0x0000C000 */
#define GPIO_OSPEEDR_OSPEED7                      GPIO_OSPEEDR_OSPEED7_Msk                          /*!< GPIO7 output speed */
#define GPIO_OSPEEDR_OSPEED7_0                    (0x1UL<<GPIO_OSPEEDR_OSPEED7_Pos)                 /*!< 0x00004000 */
#define GPIO_OSPEEDR_OSPEED7_1                    (0x2UL<<GPIO_OSPEEDR_OSPEED7_Pos)                 /*!< 0x00008000 */
#define GPIO_OSPEEDR_OSPEED8_Pos                  (16U)
#define GPIO_OSPEEDR_OSPEED8_Msk                  (0x3UL<<GPIO_OSPEEDR_OSPEED8_Pos)                 /*!< 0x00030000 */
#define GPIO_OSPEEDR_OSPEED8                      GPIO_OSPEEDR_OSPEED8_Msk                          /*!< GPIO8 output speed */
#define GPIO_OSPEEDR_OSPEED8_0                    (0x1UL<<GPIO_OSPEEDR_OSPEED8_Pos)                 /*!< 0x00010000 */
#define GPIO_OSPEEDR_OSPEED8_1                    (0x2UL<<GPIO_OSPEEDR_OSPEED8_Pos)                 /*!< 0x00020000 */
#define GPIO_OSPEEDR_OSPEED9_Pos                  (18U)
#define GPIO_OSPEEDR_OSPEED9_Msk                  (0x3UL<<GPIO_OSPEEDR_OSPEED9_Pos)                 /*!< 0x000C0000 */
#define GPIO_OSPEEDR_OSPEED9                      GPIO_OSPEEDR_OSPEED9_Msk                          /*!< GPIO9 output speed */
#define GPIO_OSPEEDR_OSPEED9_0                    (0x1UL<<GPIO_OSPEEDR_OSPEED9_Pos)                 /*!< 0x00040000 */
#define GPIO_OSPEEDR_OSPEED9_1                    (0x2UL<<GPIO_OSPEEDR_OSPEED9_Pos)                 /*!< 0x00080000 */
#define GPIO_OSPEEDR_OSPEED10_Pos                 (20U)
#define GPIO_OSPEEDR_OSPEED10_Msk                 (0x3UL<<GPIO_OSPEEDR_OSPEED10_Pos)                /*!< 0x00300000 */
#define GPIO_OSPEEDR_OSPEED10                     GPIO_OSPEEDR_OSPEED10_Msk                         /*!< GPIO10 output speed */
#define GPIO_OSPEEDR_OSPEED10_0                   (0x1UL<<GPIO_OSPEEDR_OSPEED10_Pos)                /*!< 0x00100000 */
#define GPIO_OSPEEDR_OSPEED10_1                   (0x2UL<<GPIO_OSPEEDR_OSPEED10_Pos)                /*!< 0x00200000 */
#define GPIO_OSPEEDR_OSPEED11_Pos                 (22U)
#define GPIO_OSPEEDR_OSPEED11_Msk                 (0x3UL<<GPIO_OSPEEDR_OSPEED11_Pos)                /*!< 0x00C00000 */
#define GPIO_OSPEEDR_OSPEED11                     GPIO_OSPEEDR_OSPEED11_Msk                         /*!< GPIO11 output speed */
#define GPIO_OSPEEDR_OSPEED11_0                   (0x1UL<<GPIO_OSPEEDR_OSPEED11_Pos)                /*!< 0x00400000 */
#define GPIO_OSPEEDR_OSPEED11_1                   (0x2UL<<GPIO_OSPEEDR_OSPEED11_Pos)                /*!< 0x00800000 */
#define GPIO_OSPEEDR_OSPEED12_Pos                 (24U)
#define GPIO_OSPEEDR_OSPEED12_Msk                 (0x3UL<<GPIO_OSPEEDR_OSPEED12_Pos)                /*!< 0x03000000 */
#define GPIO_OSPEEDR_OSPEED12                     GPIO_OSPEEDR_OSPEED12_Msk                         /*!< GPIO12 output speed */
#define GPIO_OSPEEDR_OSPEED12_0                   (0x1UL<<GPIO_OSPEEDR_OSPEED12_Pos)                /*!< 0x01000000 */
#define GPIO_OSPEEDR_OSPEED12_1                   (0x2UL<<GPIO_OSPEEDR_OSPEED12_Pos)                /*!< 0x02000000 */
#define GPIO_OSPEEDR_OSPEED13_Pos                 (26U)
#define GPIO_OSPEEDR_OSPEED13_Msk                 (0x3UL<<GPIO_OSPEEDR_OSPEED13_Pos)                /*!< 0x0C000000 */
#define GPIO_OSPEEDR_OSPEED13                     GPIO_OSPEEDR_OSPEED13_Msk                         /*!< GPIO13 output speed */
#define GPIO_OSPEEDR_OSPEED13_0                   (0x1UL<<GPIO_OSPEEDR_OSPEED13_Pos)                /*!< 0x04000000 */
#define GPIO_OSPEEDR_OSPEED13_1                   (0x2UL<<GPIO_OSPEEDR_OSPEED13_Pos)                /*!< 0x08000000 */
#define GPIO_OSPEEDR_OSPEED14_Pos                 (28U)
#define GPIO_OSPEEDR_OSPEED14_Msk                 (0x3UL<<GPIO_OSPEEDR_OSPEED14_Pos)                /*!< 0x30000000 */
#define GPIO_OSPEEDR_OSPEED14                     GPIO_OSPEEDR_OSPEED14_Msk                         /*!< GPIO14 output speed */
#define GPIO_OSPEEDR_OSPEED14_0                   (0x1UL<<GPIO_OSPEEDR_OSPEED14_Pos)                /*!< 0x10000000 */
#define GPIO_OSPEEDR_OSPEED14_1                   (0x2UL<<GPIO_OSPEEDR_OSPEED14_Pos)                /*!< 0x20000000 */
#define GPIO_OSPEEDR_OSPEED15_Pos                 (30U)
#define GPIO_OSPEEDR_OSPEED15_Msk                 (0x3UL<<GPIO_OSPEEDR_OSPEED15_Pos)                /*!< 0xC0000000 */
#define GPIO_OSPEEDR_OSPEED15                     GPIO_OSPEEDR_OSPEED15_Msk                         /*!< GPIO15 output speed */
#define GPIO_OSPEEDR_OSPEED15_0                   (0x1UL<<GPIO_OSPEEDR_OSPEED15_Pos)                /*!< 0x40000000 */
#define GPIO_OSPEEDR_OSPEED15_1                   (0x2UL<<GPIO_OSPEEDR_OSPEED15_Pos)                /*!< 0x80000000 */

/********************************* Bit definition for GPIO_PUPDR register *******************************************/
#define GPIO_PUPDR_PUPD0_Pos                      (0U)
#define GPIO_PUPDR_PUPD0_Msk                      (0x3UL<<GPIO_PUPDR_PUPD0_Pos)                     /*!< 0x00000003 */
#define GPIO_PUPDR_PUPD0                          GPIO_PUPDR_PUPD0_Msk                              /*!< GPIO0 pull up/pull down */
#define GPIO_PUPDR_PUPD0_0                        (0x1UL<<GPIO_PUPDR_PUPD0_Pos)                     /*!< 0x00000001 */
#define GPIO_PUPDR_PUPD0_1                        (0x2UL<<GPIO_PUPDR_PUPD0_Pos)                     /*!< 0x00000002 */
#define GPIO_PUPDR_PUPD1_Pos                      (2U)
#define GPIO_PUPDR_PUPD1_Msk                      (0x3UL<<GPIO_PUPDR_PUPD1_Pos)                     /*!< 0x0000000C */
#define GPIO_PUPDR_PUPD1                          GPIO_PUPDR_PUPD1_Msk                              /*!< GPIO1 pull up/pull down */
#define GPIO_PUPDR_PUPD1_0                        (0x1UL<<GPIO_PUPDR_PUPD1_Pos)                     /*!< 0x00000004 */
#define GPIO_PUPDR_PUPD1_1                        (0x2UL<<GPIO_PUPDR_PUPD1_Pos)                     /*!< 0x00000008 */
#define GPIO_PUPDR_PUPD2_Pos                      (4U)
#define GPIO_PUPDR_PUPD2_Msk                      (0x3UL<<GPIO_PUPDR_PUPD2_Pos)                     /*!< 0x00000030 */
#define GPIO_PUPDR_PUPD2                          GPIO_PUPDR_PUPD2_Msk                              /*!< GPIO2 pull up/pull down */
#define GPIO_PUPDR_PUPD2_0                        (0x1UL<<GPIO_PUPDR_PUPD2_Pos)                     /*!< 0x00000010 */
#define GPIO_PUPDR_PUPD2_1                        (0x2UL<<GPIO_PUPDR_PUPD2_Pos)                     /*!< 0x00000020 */
#define GPIO_PUPDR_PUPD3_Pos                      (6U)
#define GPIO_PUPDR_PUPD3_Msk                      (0x3UL<<GPIO_PUPDR_PUPD3_Pos)                     /*!< 0x000000C0 */
#define GPIO_PUPDR_PUPD3                          GPIO_PUPDR_PUPD3_Msk                              /*!< GPIO3 pull up/pull down */
#define GPIO_PUPDR_PUPD3_0                        (0x1UL<<GPIO_PUPDR_PUPD3_Pos)                     /*!< 0x00000040 */
#define GPIO_PUPDR_PUPD3_1                        (0x2UL<<GPIO_PUPDR_PUPD3_Pos)                     /*!< 0x00000080 */
#define GPIO_PUPDR_PUPD4_Pos                      (8U)
#define GPIO_PUPDR_PUPD4_Msk                      (0x3UL<<GPIO_PUPDR_PUPD4_Pos)                     /*!< 0x00000300 */
#define GPIO_PUPDR_PUPD4                          GPIO_PUPDR_PUPD4_Msk                              /*!< GPIO4 pull up/pull down */
#define GPIO_PUPDR_PUPD4_0                        (0x1UL<<GPIO_PUPDR_PUPD4_Pos)                     /*!< 0x00000100 */
#define GPIO_PUPDR_PUPD4_1                        (0x2UL<<GPIO_PUPDR_PUPD4_Pos)                     /*!< 0x00000200 */
#define GPIO_PUPDR_PUPD5_Pos                      (10U)
#define GPIO_PUPDR_PUPD5_Msk                      (0x3UL<<GPIO_PUPDR_PUPD5_Pos)                     /*!< 0x00000C00 */
#define GPIO_PUPDR_PUPD5                          GPIO_PUPDR_PUPD5_Msk                              /*!< GPIO5 pull up/pull down */
#define GPIO_PUPDR_PUPD5_0                        (0x1UL<<GPIO_PUPDR_PUPD5_Pos)                     /*!< 0x00000400 */
#define GPIO_PUPDR_PUPD5_1                        (0x2UL<<GPIO_PUPDR_PUPD5_Pos)                     /*!< 0x00000800 */
#define GPIO_PUPDR_PUPD6_Pos                      (12U)
#define GPIO_PUPDR_PUPD6_Msk                      (0x3UL<<GPIO_PUPDR_PUPD6_Pos)                     /*!< 0x00003000 */
#define GPIO_PUPDR_PUPD6                          GPIO_PUPDR_PUPD6_Msk                              /*!< GPIO6 pull up/pull down */
#define GPIO_PUPDR_PUPD6_0                        (0x1UL<<GPIO_PUPDR_PUPD6_Pos)                     /*!< 0x00001000 */
#define GPIO_PUPDR_PUPD6_1                        (0x2UL<<GPIO_PUPDR_PUPD6_Pos)                     /*!< 0x00002000 */
#define GPIO_PUPDR_PUPD7_Pos                      (14U)
#define GPIO_PUPDR_PUPD7_Msk                      (0x3UL<<GPIO_PUPDR_PUPD7_Pos)                     /*!< 0x0000C000 */
#define GPIO_PUPDR_PUPD7                          GPIO_PUPDR_PUPD7_Msk                              /*!< GPIO7 pull up/pull down */
#define GPIO_PUPDR_PUPD7_0                        (0x1UL<<GPIO_PUPDR_PUPD7_Pos)                     /*!< 0x00004000 */
#define GPIO_PUPDR_PUPD7_1                        (0x2UL<<GPIO_PUPDR_PUPD7_Pos)                     /*!< 0x00008000 */
#define GPIO_PUPDR_PUPD8_Pos                      (16U)
#define GPIO_PUPDR_PUPD8_Msk                      (0x3UL<<GPIO_PUPDR_PUPD8_Pos)                     /*!< 0x00030000 */
#define GPIO_PUPDR_PUPD8                          GPIO_PUPDR_PUPD8_Msk                              /*!< GPIO8 pull up/pull down */
#define GPIO_PUPDR_PUPD8_0                        (0x1UL<<GPIO_PUPDR_PUPD8_Pos)                     /*!< 0x00010000 */
#define GPIO_PUPDR_PUPD8_1                        (0x2UL<<GPIO_PUPDR_PUPD8_Pos)                     /*!< 0x00020000 */
#define GPIO_PUPDR_PUPD9_Pos                      (18U)
#define GPIO_PUPDR_PUPD9_Msk                      (0x3UL<<GPIO_PUPDR_PUPD9_Pos)                     /*!< 0x000C0000 */
#define GPIO_PUPDR_PUPD9                          GPIO_PUPDR_PUPD9_Msk                              /*!< GPIO9 pull up/pull down */
#define GPIO_PUPDR_PUPD9_0                        (0x1UL<<GPIO_PUPDR_PUPD9_Pos)                     /*!< 0x00040000 */
#define GPIO_PUPDR_PUPD9_1                        (0x2UL<<GPIO_PUPDR_PUPD9_Pos)                     /*!< 0x00080000 */
#define GPIO_PUPDR_PUPD10_Pos                     (20U)
#define GPIO_PUPDR_PUPD10_Msk                     (0x3UL<<GPIO_PUPDR_PUPD10_Pos)                    /*!< 0x00300000 */
#define GPIO_PUPDR_PUPD10                         GPIO_PUPDR_PUPD10_Msk                             /*!< GPIO10 pull up/pull down */
#define GPIO_PUPDR_PUPD10_0                       (0x1UL<<GPIO_PUPDR_PUPD10_Pos)                    /*!< 0x00100000 */
#define GPIO_PUPDR_PUPD10_1                       (0x2UL<<GPIO_PUPDR_PUPD10_Pos)                    /*!< 0x00200000 */
#define GPIO_PUPDR_PUPD11_Pos                     (22U)
#define GPIO_PUPDR_PUPD11_Msk                     (0x3UL<<GPIO_PUPDR_PUPD11_Pos)                    /*!< 0x00C00000 */
#define GPIO_PUPDR_PUPD11                         GPIO_PUPDR_PUPD11_Msk                             /*!< GPIO11 pull up/pull down */
#define GPIO_PUPDR_PUPD11_0                       (0x1UL<<GPIO_PUPDR_PUPD11_Pos)                    /*!< 0x00400000 */
#define GPIO_PUPDR_PUPD11_1                       (0x2UL<<GPIO_PUPDR_PUPD11_Pos)                    /*!< 0x00800000 */
#define GPIO_PUPDR_PUPD12_Pos                     (24U)
#define GPIO_PUPDR_PUPD12_Msk                     (0x3UL<<GPIO_PUPDR_PUPD12_Pos)                    /*!< 0x03000000 */
#define GPIO_PUPDR_PUPD12                         GPIO_PUPDR_PUPD12_Msk                             /*!< GPIO12 pull up/pull down */
#define GPIO_PUPDR_PUPD12_0                       (0x1UL<<GPIO_PUPDR_PUPD12_Pos)                    /*!< 0x01000000 */
#define GPIO_PUPDR_PUPD12_1                       (0x2UL<<GPIO_PUPDR_PUPD12_Pos)                    /*!< 0x02000000 */
#define GPIO_PUPDR_PUPD13_Pos                     (26U)
#define GPIO_PUPDR_PUPD13_Msk                     (0x3UL<<GPIO_PUPDR_PUPD13_Pos)                    /*!< 0x0C000000 */
#define GPIO_PUPDR_PUPD13                         GPIO_PUPDR_PUPD13_Msk                             /*!< GPIO13 pull up/pull down */
#define GPIO_PUPDR_PUPD13_0                       (0x1UL<<GPIO_PUPDR_PUPD13_Pos)                    /*!< 0x04000000 */
#define GPIO_PUPDR_PUPD13_1                       (0x2UL<<GPIO_PUPDR_PUPD13_Pos)                    /*!< 0x08000000 */
#define GPIO_PUPDR_PUPD14_Pos                     (28U)
#define GPIO_PUPDR_PUPD14_Msk                     (0x3UL<<GPIO_PUPDR_PUPD14_Pos)                    /*!< 0x30000000 */
#define GPIO_PUPDR_PUPD14                         GPIO_PUPDR_PUPD14_Msk                             /*!< GPIO14 pull up/pull down */
#define GPIO_PUPDR_PUPD14_0                       (0x1UL<<GPIO_PUPDR_PUPD14_Pos)                    /*!< 0x10000000 */
#define GPIO_PUPDR_PUPD14_1                       (0x2UL<<GPIO_PUPDR_PUPD14_Pos)                    /*!< 0x20000000 */
#define GPIO_PUPDR_PUPD15_Pos                     (30U)
#define GPIO_PUPDR_PUPD15_Msk                     (0x3UL<<GPIO_PUPDR_PUPD15_Pos)                    /*!< 0xC0000000 */
#define GPIO_PUPDR_PUPD15                         GPIO_PUPDR_PUPD15_Msk                             /*!< GPIO15 pull up/pull down */
#define GPIO_PUPDR_PUPD15_0                       (0x1UL<<GPIO_PUPDR_PUPD15_Pos)                    /*!< 0x40000000 */
#define GPIO_PUPDR_PUPD15_1                       (0x2UL<<GPIO_PUPDR_PUPD15_Pos)                    /*!< 0x80000000 */

/********************************* Bit definition for GPIO_IDR register *********************************************/
#define GPIO_IDR_ID0_Pos                          (0U)
#define GPIO_IDR_ID0_Msk                          (0x1UL<<GPIO_IDR_ID0_Pos)                         /*!< 0x00000001 */
#define GPIO_IDR_ID0                              GPIO_IDR_ID0_Msk                                  /*!< GPIO0 input data */
#define GPIO_IDR_ID1_Pos                          (1U)
#define GPIO_IDR_ID1_Msk                          (0x1UL<<GPIO_IDR_ID1_Pos)                         /*!< 0x00000002 */
#define GPIO_IDR_ID1                              GPIO_IDR_ID1_Msk                                  /*!< GPIO1 input data */
#define GPIO_IDR_ID2_Pos                          (2U)
#define GPIO_IDR_ID2_Msk                          (0x1UL<<GPIO_IDR_ID2_Pos)                         /*!< 0x00000004 */
#define GPIO_IDR_ID2                              GPIO_IDR_ID2_Msk                                  /*!< GPIO2 input data */
#define GPIO_IDR_ID3_Pos                          (3U)
#define GPIO_IDR_ID3_Msk                          (0x1UL<<GPIO_IDR_ID3_Pos)                         /*!< 0x00000008 */
#define GPIO_IDR_ID3                              GPIO_IDR_ID3_Msk                                  /*!< GPIO3 input data */
#define GPIO_IDR_ID4_Pos                          (4U)
#define GPIO_IDR_ID4_Msk                          (0x1UL<<GPIO_IDR_ID4_Pos)                         /*!< 0x00000010 */
#define GPIO_IDR_ID4                              GPIO_IDR_ID4_Msk                                  /*!< GPIO4 input data */
#define GPIO_IDR_ID5_Pos                          (5U)
#define GPIO_IDR_ID5_Msk                          (0x1UL<<GPIO_IDR_ID5_Pos)                         /*!< 0x00000020 */
#define GPIO_IDR_ID5                              GPIO_IDR_ID5_Msk                                  /*!< GPIO5 input data */
#define GPIO_IDR_ID6_Pos                          (6U)
#define GPIO_IDR_ID6_Msk                          (0x1UL<<GPIO_IDR_ID6_Pos)                         /*!< 0x00000040 */
#define GPIO_IDR_ID6                              GPIO_IDR_ID6_Msk                                  /*!< GPIO6 input data */
#define GPIO_IDR_ID7_Pos                          (7U)
#define GPIO_IDR_ID7_Msk                          (0x1UL<<GPIO_IDR_ID7_Pos)                         /*!< 0x00000080 */
#define GPIO_IDR_ID7                              GPIO_IDR_ID7_Msk                                  /*!< GPIO7 input data */
#define GPIO_IDR_ID8_Pos                          (8U)
#define GPIO_IDR_ID8_Msk                          (0x1UL<<GPIO_IDR_ID8_Pos)                         /*!< 0x00000100 */
#define GPIO_IDR_ID8                              GPIO_IDR_ID8_Msk                                  /*!< GPIO8 input data */
#define GPIO_IDR_ID9_Pos                          (9U)
#define GPIO_IDR_ID9_Msk                          (0x1UL<<GPIO_IDR_ID9_Pos)                         /*!< 0x00000200 */
#define GPIO_IDR_ID9                              GPIO_IDR_ID9_Msk                                  /*!< GPIO9 input data */
#define GPIO_IDR_ID10_Pos                         (10U)
#define GPIO_IDR_ID10_Msk                         (0x1UL<<GPIO_IDR_ID10_Pos)                        /*!< 0x00000400 */
#define GPIO_IDR_ID10                             GPIO_IDR_ID10_Msk                                 /*!< GPIO10 input data */
#define GPIO_IDR_ID11_Pos                         (11U)
#define GPIO_IDR_ID11_Msk                         (0x1UL<<GPIO_IDR_ID11_Pos)                        /*!< 0x00000800 */
#define GPIO_IDR_ID11                             GPIO_IDR_ID11_Msk                                 /*!< GPIO11 input data */
#define GPIO_IDR_ID12_Pos                         (12U)
#define GPIO_IDR_ID12_Msk                         (0x1UL<<GPIO_IDR_ID12_Pos)                        /*!< 0x00001000 */
#define GPIO_IDR_ID12                             GPIO_IDR_ID12_Msk                                 /*!< GPIO12 input data */
#define GPIO_IDR_ID13_Pos                         (13U)
#define GPIO_IDR_ID13_Msk                         (0x1UL<<GPIO_IDR_ID13_Pos)                        /*!< 0x00002000 */
#define GPIO_IDR_ID13                             GPIO_IDR_ID13_Msk                                 /*!< GPIO13 input data */
#define GPIO_IDR_ID14_Pos                         (14U)
#define GPIO_IDR_ID14_Msk                         (0x1UL<<GPIO_IDR_ID14_Pos)                        /*!< 0x00004000 */
#define GPIO_IDR_ID14                             GPIO_IDR_ID14_Msk                                 /*!< GPIO14 input data */
#define GPIO_IDR_ID15_Pos                         (15U)
#define GPIO_IDR_ID15_Msk                         (0x1UL<<GPIO_IDR_ID15_Pos)                        /*!< 0x00008000 */
#define GPIO_IDR_ID15                             GPIO_IDR_ID15_Msk                                 /*!< GPIO15 input data */

/********************************* Bit definition for GPIO_ODR register *********************************************/
#define GPIO_ODR_OD0_Pos                          (0U)
#define GPIO_ODR_OD0_Msk                          (0x1UL<<GPIO_ODR_OD0_Pos)                         /*!< 0x00000001 */
#define GPIO_ODR_OD0                              GPIO_ODR_OD0_Msk                                  /*!< GPIO0 output data */
#define GPIO_ODR_OD1_Pos                          (1U)
#define GPIO_ODR_OD1_Msk                          (0x1UL<<GPIO_ODR_OD1_Pos)                         /*!< 0x00000002 */
#define GPIO_ODR_OD1                              GPIO_ODR_OD1_Msk                                  /*!< GPIO1 output data */
#define GPIO_ODR_OD2_Pos                          (2U)
#define GPIO_ODR_OD2_Msk                          (0x1UL<<GPIO_ODR_OD2_Pos)                         /*!< 0x00000004 */
#define GPIO_ODR_OD2                              GPIO_ODR_OD2_Msk                                  /*!< GPIO2 output data */
#define GPIO_ODR_OD3_Pos                          (3U)
#define GPIO_ODR_OD3_Msk                          (0x1UL<<GPIO_ODR_OD3_Pos)                         /*!< 0x00000008 */
#define GPIO_ODR_OD3                              GPIO_ODR_OD3_Msk                                  /*!< GPIO3 output data */
#define GPIO_ODR_OD4_Pos                          (4U)
#define GPIO_ODR_OD4_Msk                          (0x1UL<<GPIO_ODR_OD4_Pos)                         /*!< 0x00000010 */
#define GPIO_ODR_OD4                              GPIO_ODR_OD4_Msk                                  /*!< GPIO4 output data */
#define GPIO_ODR_OD5_Pos                          (5U)
#define GPIO_ODR_OD5_Msk                          (0x1UL<<GPIO_ODR_OD5_Pos)                         /*!< 0x00000020 */
#define GPIO_ODR_OD5                              GPIO_ODR_OD5_Msk                                  /*!< GPIO5 output data */
#define GPIO_ODR_OD6_Pos                          (6U)
#define GPIO_ODR_OD6_Msk                          (0x1UL<<GPIO_ODR_OD6_Pos)                         /*!< 0x00000040 */
#define GPIO_ODR_OD6                              GPIO_ODR_OD6_Msk                                  /*!< GPIO6 output data */
#define GPIO_ODR_OD7_Pos                          (7U)
#define GPIO_ODR_OD7_Msk                          (0x1UL<<GPIO_ODR_OD7_Pos)                         /*!< 0x00000080 */
#define GPIO_ODR_OD7                              GPIO_ODR_OD7_Msk                                  /*!< GPIO7 output data */
#define GPIO_ODR_OD8_Pos                          (8U)
#define GPIO_ODR_OD8_Msk                          (0x1UL<<GPIO_ODR_OD8_Pos)                         /*!< 0x00000100 */
#define GPIO_ODR_OD8                              GPIO_ODR_OD8_Msk                                  /*!< GPIO8 output data */
#define GPIO_ODR_OD9_Pos                          (9U)
#define GPIO_ODR_OD9_Msk                          (0x1UL<<GPIO_ODR_OD9_Pos)                         /*!< 0x00000200 */
#define GPIO_ODR_OD9                              GPIO_ODR_OD9_Msk                                  /*!< GPIO9 output data */
#define GPIO_ODR_OD10_Pos                         (10U)
#define GPIO_ODR_OD10_Msk                         (0x1UL<<GPIO_ODR_OD10_Pos)                        /*!< 0x00000400 */
#define GPIO_ODR_OD10                             GPIO_ODR_OD10_Msk                                 /*!< GPIO10 output data */
#define GPIO_ODR_OD11_Pos                         (11U)
#define GPIO_ODR_OD11_Msk                         (0x1UL<<GPIO_ODR_OD11_Pos)                        /*!< 0x00000800 */
#define GPIO_ODR_OD11                             GPIO_ODR_OD11_Msk                                 /*!< GPIO11 output data */
#define GPIO_ODR_OD12_Pos                         (12U)
#define GPIO_ODR_OD12_Msk                         (0x1UL<<GPIO_ODR_OD12_Pos)                        /*!< 0x00001000 */
#define GPIO_ODR_OD12                             GPIO_ODR_OD12_Msk                                 /*!< GPIO12 output data */
#define GPIO_ODR_OD13_Pos                         (13U)
#define GPIO_ODR_OD13_Msk                         (0x1UL<<GPIO_ODR_OD13_Pos)                        /*!< 0x00002000 */
#define GPIO_ODR_OD13                             GPIO_ODR_OD13_Msk                                 /*!< GPIO13 output data */
#define GPIO_ODR_OD14_Pos                         (14U)
#define GPIO_ODR_OD14_Msk                         (0x1UL<<GPIO_ODR_OD14_Pos)                        /*!< 0x00004000 */
#define GPIO_ODR_OD14                             GPIO_ODR_OD14_Msk                                 /*!< GPIO14 output data */
#define GPIO_ODR_OD15_Pos                         (15U)
#define GPIO_ODR_OD15_Msk                         (0x1UL<<GPIO_ODR_OD15_Pos)                        /*!< 0x00008000 */
#define GPIO_ODR_OD15                             GPIO_ODR_OD15_Msk                                 /*!< GPIO15 output data */

/********************************* Bit definition for GPIO_BSRR register ********************************************/
#define GPIO_BSRR_BS0_Pos                         (0U)
#define GPIO_BSRR_BS0_Msk                         (0x1UL<<GPIO_BSRR_BS0_Pos)                        /*!< 0x00000001 */
#define GPIO_BSRR_BS0                             GPIO_BSRR_BS0_Msk                                 /*!< GPIO0 output set */
#define GPIO_BSRR_BS1_Pos                         (1U)
#define GPIO_BSRR_BS1_Msk                         (0x1UL<<GPIO_BSRR_BS1_Pos)                        /*!< 0x00000002 */
#define GPIO_BSRR_BS1                             GPIO_BSRR_BS1_Msk                                 /*!< GPIO1 output set */
#define GPIO_BSRR_BS2_Pos                         (2U)
#define GPIO_BSRR_BS2_Msk                         (0x1UL<<GPIO_BSRR_BS2_Pos)                        /*!< 0x00000004 */
#define GPIO_BSRR_BS2                             GPIO_BSRR_BS2_Msk                                 /*!< GPIO2 output set */
#define GPIO_BSRR_BS3_Pos                         (3U)
#define GPIO_BSRR_BS3_Msk                         (0x1UL<<GPIO_BSRR_BS3_Pos)                        /*!< 0x00000008 */
#define GPIO_BSRR_BS3                             GPIO_BSRR_BS3_Msk                                 /*!< GPIO3 output set */
#define GPIO_BSRR_BS4_Pos                         (4U)
#define GPIO_BSRR_BS4_Msk                         (0x1UL<<GPIO_BSRR_BS4_Pos)                        /*!< 0x00000010 */
#define GPIO_BSRR_BS4                             GPIO_BSRR_BS4_Msk                                 /*!< GPIO4 output set */
#define GPIO_BSRR_BS5_Pos                         (5U)
#define GPIO_BSRR_BS5_Msk                         (0x1UL<<GPIO_BSRR_BS5_Pos)                        /*!< 0x00000020 */
#define GPIO_BSRR_BS5                             GPIO_BSRR_BS5_Msk                                 /*!< GPIO5 output set */
#define GPIO_BSRR_BS6_Pos                         (6U)
#define GPIO_BSRR_BS6_Msk                         (0x1UL<<GPIO_BSRR_BS6_Pos)                        /*!< 0x00000040 */
#define GPIO_BSRR_BS6                             GPIO_BSRR_BS6_Msk                                 /*!< GPIO6 output set */
#define GPIO_BSRR_BS7_Pos                         (7U)
#define GPIO_BSRR_BS7_Msk                         (0x1UL<<GPIO_BSRR_BS7_Pos)                        /*!< 0x00000080 */
#define GPIO_BSRR_BS7                             GPIO_BSRR_BS7_Msk                                 /*!< GPIO7 output set */
#define GPIO_BSRR_BS8_Pos                         (8U)
#define GPIO_BSRR_BS8_Msk                         (0x1UL<<GPIO_BSRR_BS8_Pos)                        /*!< 0x00000100 */
#define GPIO_BSRR_BS8                             GPIO_BSRR_BS8_Msk                                 /*!< GPIO8 output set */
#define GPIO_BSRR_BS9_Pos                         (9U)
#define GPIO_BSRR_BS9_Msk                         (0x1UL<<GPIO_BSRR_BS9_Pos)                        /*!< 0x00000200 */
#define GPIO_BSRR_BS9                             GPIO_BSRR_BS9_Msk                                 /*!< GPIO9 output set */
#define GPIO_BSRR_BS10_Pos                        (10U)
#define GPIO_BSRR_BS10_Msk                        (0x1UL<<GPIO_BSRR_BS10_Pos)                       /*!< 0x00000400 */
#define GPIO_BSRR_BS10                            GPIO_BSRR_BS10_Msk                                /*!< GPIO10 output set */
#define GPIO_BSRR_BS11_Pos                        (11U)
#define GPIO_BSRR_BS11_Msk                        (0x1UL<<GPIO_BSRR_BS11_Pos)                       /*!< 0x00000800 */
#define GPIO_BSRR_BS11                            GPIO_BSRR_BS11_Msk                                /*!< GPIO11 output set */
#define GPIO_BSRR_BS12_Pos                        (12U)
#define GPIO_BSRR_BS12_Msk                        (0x1UL<<GPIO_BSRR_BS12_Pos)                       /*!< 0x00001000 */
#define GPIO_BSRR_BS12                            GPIO_BSRR_BS12_Msk                                /*!< GPIO12 output set */
#define GPIO_BSRR_BS13_Pos                        (13U)
#define GPIO_BSRR_BS13_Msk                        (0x1UL<<GPIO_BSRR_BS13_Pos)                       /*!< 0x00002000 */
#define GPIO_BSRR_BS13                            GPIO_BSRR_BS13_Msk                                /*!< GPIO13 output set */
#define GPIO_BSRR_BS14_Pos                        (14U)
#define GPIO_BSRR_BS14_Msk                        (0x1UL<<GPIO_BSRR_BS14_Pos)                       /*!< 0x00004000 */
#define GPIO_BSRR_BS14                            GPIO_BSRR_BS14_Msk                                /*!< GPIO14 output set */
#define GPIO_BSRR_BS15_Pos                        (15U)
#define GPIO_BSRR_BS15_Msk                        (0x1UL<<GPIO_BSRR_BS15_Pos)                       /*!< 0x00008000 */
#define GPIO_BSRR_BS15                            GPIO_BSRR_BS15_Msk                                /*!< GPIO15 output set */
#define GPIO_BSRR_BR0_Pos                         (16U)
#define GPIO_BSRR_BR0_Msk                         (0x1UL<<GPIO_BSRR_BR0_Pos)                        /*!< 0x00010000 */
#define GPIO_BSRR_BR0                             GPIO_BSRR_BR0_Msk                                 /*!< GPIO0 outut reset */
#define GPIO_BSRR_BR1_Pos                         (17U)
#define GPIO_BSRR_BR1_Msk                         (0x1UL<<GPIO_BSRR_BR1_Pos)                        /*!< 0x00020000 */
#define GPIO_BSRR_BR1                             GPIO_BSRR_BR1_Msk                                 /*!< GPIO1 outut reset */
#define GPIO_BSRR_BR2_Pos                         (18U)
#define GPIO_BSRR_BR2_Msk                         (0x1UL<<GPIO_BSRR_BR2_Pos)                        /*!< 0x00040000 */
#define GPIO_BSRR_BR2                             GPIO_BSRR_BR2_Msk                                 /*!< GPIO2 outut reset */
#define GPIO_BSRR_BR3_Pos                         (19U)
#define GPIO_BSRR_BR3_Msk                         (0x1UL<<GPIO_BSRR_BR3_Pos)                        /*!< 0x00080000 */
#define GPIO_BSRR_BR3                             GPIO_BSRR_BR3_Msk                                 /*!< GPIO3 outut reset */
#define GPIO_BSRR_BR4_Pos                         (20U)
#define GPIO_BSRR_BR4_Msk                         (0x1UL<<GPIO_BSRR_BR4_Pos)                        /*!< 0x00100000 */
#define GPIO_BSRR_BR4                             GPIO_BSRR_BR4_Msk                                 /*!< GPIO4 outut reset */
#define GPIO_BSRR_BR5_Pos                         (21U)
#define GPIO_BSRR_BR5_Msk                         (0x1UL<<GPIO_BSRR_BR5_Pos)                        /*!< 0x00200000 */
#define GPIO_BSRR_BR5                             GPIO_BSRR_BR5_Msk                                 /*!< GPIO5 outut reset */
#define GPIO_BSRR_BR6_Pos                         (22U)
#define GPIO_BSRR_BR6_Msk                         (0x1UL<<GPIO_BSRR_BR6_Pos)                        /*!< 0x00400000 */
#define GPIO_BSRR_BR6                             GPIO_BSRR_BR6_Msk                                 /*!< GPIO6 outut reset */
#define GPIO_BSRR_BR7_Pos                         (23U)
#define GPIO_BSRR_BR7_Msk                         (0x1UL<<GPIO_BSRR_BR7_Pos)                        /*!< 0x00800000 */
#define GPIO_BSRR_BR7                             GPIO_BSRR_BR7_Msk                                 /*!< GPIO7 outut reset */
#define GPIO_BSRR_BR8_Pos                         (24U)
#define GPIO_BSRR_BR8_Msk                         (0x1UL<<GPIO_BSRR_BR8_Pos)                        /*!< 0x01000000 */
#define GPIO_BSRR_BR8                             GPIO_BSRR_BR8_Msk                                 /*!< GPIO8 outut reset */
#define GPIO_BSRR_BR9_Pos                         (25U)
#define GPIO_BSRR_BR9_Msk                         (0x1UL<<GPIO_BSRR_BR9_Pos)                        /*!< 0x02000000 */
#define GPIO_BSRR_BR9                             GPIO_BSRR_BR9_Msk                                 /*!< GPIO9 outut reset */
#define GPIO_BSRR_BR10_Pos                        (26U)
#define GPIO_BSRR_BR10_Msk                        (0x1UL<<GPIO_BSRR_BR10_Pos)                       /*!< 0x04000000 */
#define GPIO_BSRR_BR10                            GPIO_BSRR_BR10_Msk                                /*!< GPIO10 outut reset */
#define GPIO_BSRR_BR11_Pos                        (27U)
#define GPIO_BSRR_BR11_Msk                        (0x1UL<<GPIO_BSRR_BR11_Pos)                       /*!< 0x08000000 */
#define GPIO_BSRR_BR11                            GPIO_BSRR_BR11_Msk                                /*!< GPIO11 outut reset */
#define GPIO_BSRR_BR12_Pos                        (28U)
#define GPIO_BSRR_BR12_Msk                        (0x1UL<<GPIO_BSRR_BR12_Pos)                       /*!< 0x10000000 */
#define GPIO_BSRR_BR12                            GPIO_BSRR_BR12_Msk                                /*!< GPIO12 outut reset */
#define GPIO_BSRR_BR13_Pos                        (29U)
#define GPIO_BSRR_BR13_Msk                        (0x1UL<<GPIO_BSRR_BR13_Pos)                       /*!< 0x20000000 */
#define GPIO_BSRR_BR13                            GPIO_BSRR_BR13_Msk                                /*!< GPIO13 outut reset */
#define GPIO_BSRR_BR14_Pos                        (30U)
#define GPIO_BSRR_BR14_Msk                        (0x1UL<<GPIO_BSRR_BR14_Pos)                       /*!< 0x40000000 */
#define GPIO_BSRR_BR14                            GPIO_BSRR_BR14_Msk                                /*!< GPIO14 outut reset */
#define GPIO_BSRR_BR15_Pos                        (31U)
#define GPIO_BSRR_BR15_Msk                        (0x1UL<<GPIO_BSRR_BR15_Pos)                       /*!< 0x80000000 */
#define GPIO_BSRR_BR15                            GPIO_BSRR_BR15_Msk                                /*!< GPIO15 outut reset */

/********************************* Bit definition for GPIO_LCKR register ********************************************/
#define GPIO_LCKR_LCK0_Pos                        (0U)
#define GPIO_LCKR_LCK0_Msk                        (0x1UL<<GPIO_LCKR_LCK0_Pos)                       /*!< 0x00000001 */
#define GPIO_LCKR_LCK0                            GPIO_LCKR_LCK0_Msk                                /*!< GPIO lock(bit0) */
#define GPIO_LCKR_LCK1_Pos                        (1U)
#define GPIO_LCKR_LCK1_Msk                        (0x1UL<<GPIO_LCKR_LCK1_Pos)                       /*!< 0x00000002 */
#define GPIO_LCKR_LCK1                            GPIO_LCKR_LCK1_Msk                                /*!< GPIO lock(bit1) */
#define GPIO_LCKR_LCK2_Pos                        (2U)
#define GPIO_LCKR_LCK2_Msk                        (0x1UL<<GPIO_LCKR_LCK2_Pos)                       /*!< 0x00000004 */
#define GPIO_LCKR_LCK2                            GPIO_LCKR_LCK2_Msk                                /*!< GPIO lock(bit2) */
#define GPIO_LCKR_LCK3_Pos                        (3U)
#define GPIO_LCKR_LCK3_Msk                        (0x1UL<<GPIO_LCKR_LCK3_Pos)                       /*!< 0x00000008 */
#define GPIO_LCKR_LCK3                            GPIO_LCKR_LCK3_Msk                                /*!< GPIO lock(bit3) */
#define GPIO_LCKR_LCK4_Pos                        (4U)
#define GPIO_LCKR_LCK4_Msk                        (0x1UL<<GPIO_LCKR_LCK4_Pos)                       /*!< 0x00000010 */
#define GPIO_LCKR_LCK4                            GPIO_LCKR_LCK4_Msk                                /*!< GPIO lock(bit4) */
#define GPIO_LCKR_LCK5_Pos                        (5U)
#define GPIO_LCKR_LCK5_Msk                        (0x1UL<<GPIO_LCKR_LCK5_Pos)                       /*!< 0x00000020 */
#define GPIO_LCKR_LCK5                            GPIO_LCKR_LCK5_Msk                                /*!< GPIO lock(bit5) */
#define GPIO_LCKR_LCK6_Pos                        (6U)
#define GPIO_LCKR_LCK6_Msk                        (0x1UL<<GPIO_LCKR_LCK6_Pos)                       /*!< 0x00000040 */
#define GPIO_LCKR_LCK6                            GPIO_LCKR_LCK6_Msk                                /*!< GPIO lock(bit6) */
#define GPIO_LCKR_LCK7_Pos                        (7U)
#define GPIO_LCKR_LCK7_Msk                        (0x1UL<<GPIO_LCKR_LCK7_Pos)                       /*!< 0x00000080 */
#define GPIO_LCKR_LCK7                            GPIO_LCKR_LCK7_Msk                                /*!< GPIO lock(bit7) */
#define GPIO_LCKR_LCK8_Pos                        (8U)
#define GPIO_LCKR_LCK8_Msk                        (0x1UL<<GPIO_LCKR_LCK8_Pos)                       /*!< 0x00000100 */
#define GPIO_LCKR_LCK8                            GPIO_LCKR_LCK8_Msk                                /*!< GPIO lock(bit8) */
#define GPIO_LCKR_LCK9_Pos                        (9U)
#define GPIO_LCKR_LCK9_Msk                        (0x1UL<<GPIO_LCKR_LCK9_Pos)                       /*!< 0x00000200 */
#define GPIO_LCKR_LCK9                            GPIO_LCKR_LCK9_Msk                                /*!< GPIO lock(bit9) */
#define GPIO_LCKR_LCK10_Pos                       (10U)
#define GPIO_LCKR_LCK10_Msk                       (0x1UL<<GPIO_LCKR_LCK10_Pos)                      /*!< 0x00000400 */
#define GPIO_LCKR_LCK10                           GPIO_LCKR_LCK10_Msk                               /*!< GPIO lock(bit10) */
#define GPIO_LCKR_LCK11_Pos                       (11U)
#define GPIO_LCKR_LCK11_Msk                       (0x1UL<<GPIO_LCKR_LCK11_Pos)                      /*!< 0x00000800 */
#define GPIO_LCKR_LCK11                           GPIO_LCKR_LCK11_Msk                               /*!< GPIO lock(bit11) */
#define GPIO_LCKR_LCK12_Pos                       (12U)
#define GPIO_LCKR_LCK12_Msk                       (0x1UL<<GPIO_LCKR_LCK12_Pos)                      /*!< 0x00001000 */
#define GPIO_LCKR_LCK12                           GPIO_LCKR_LCK12_Msk                               /*!< GPIO lock(bit12) */
#define GPIO_LCKR_LCK13_Pos                       (13U)
#define GPIO_LCKR_LCK13_Msk                       (0x1UL<<GPIO_LCKR_LCK13_Pos)                      /*!< 0x00002000 */
#define GPIO_LCKR_LCK13                           GPIO_LCKR_LCK13_Msk                               /*!< GPIO lock(bit13) */
#define GPIO_LCKR_LCK14_Pos                       (14U)
#define GPIO_LCKR_LCK14_Msk                       (0x1UL<<GPIO_LCKR_LCK14_Pos)                      /*!< 0x00004000 */
#define GPIO_LCKR_LCK14                           GPIO_LCKR_LCK14_Msk                               /*!< GPIO lock(bit14) */
#define GPIO_LCKR_LCK15_Pos                       (15U)
#define GPIO_LCKR_LCK15_Msk                       (0x1UL<<GPIO_LCKR_LCK15_Pos)                      /*!< 0x00008000 */
#define GPIO_LCKR_LCK15                           GPIO_LCKR_LCK15_Msk                               /*!< GPIO lock(bit15) */
#define GPIO_LCKR_LCKK_Pos                        (16U)
#define GPIO_LCKR_LCKK_Msk                        (0x1UL<<GPIO_LCKR_LCKK_Pos)                       /*!< 0x00010000 */
#define GPIO_LCKR_LCKK                            GPIO_LCKR_LCKK_Msk                                /*!< GPIO lock key */

/********************************* Bit definition for GPIO_AFRL register ********************************************/
#define GPIO_AFRL_AFSEL0_Pos                      (0U)
#define GPIO_AFRL_AFSEL0_Msk                      (0xFUL<<GPIO_AFRL_AFSEL0_Pos)                     /*!< 0x0000000F */
#define GPIO_AFRL_AFSEL0                          GPIO_AFRL_AFSEL0_Msk                              /*!< GPIO0 AF select */
#define GPIO_AFRL_AFSEL0_0                        (0x1UL<<GPIO_AFRL_AFSEL0_Pos)                     /*!< 0x00000001 */
#define GPIO_AFRL_AFSEL0_1                        (0x2UL<<GPIO_AFRL_AFSEL0_Pos)                     /*!< 0x00000002 */
#define GPIO_AFRL_AFSEL0_2                        (0x4UL<<GPIO_AFRL_AFSEL0_Pos)                     /*!< 0x00000004 */
#define GPIO_AFRL_AFSEL0_3                        (0x8UL<<GPIO_AFRL_AFSEL0_Pos)                     /*!< 0x00000008 */
#define GPIO_AFRL_AFSEL1_Pos                      (4U)
#define GPIO_AFRL_AFSEL1_Msk                      (0xFUL<<GPIO_AFRL_AFSEL1_Pos)                     /*!< 0x000000F0 */
#define GPIO_AFRL_AFSEL1                          GPIO_AFRL_AFSEL1_Msk                              /*!< GPIO1 AF select */
#define GPIO_AFRL_AFSEL1_0                        (0x1UL<<GPIO_AFRL_AFSEL1_Pos)                     /*!< 0x00000010 */
#define GPIO_AFRL_AFSEL1_1                        (0x2UL<<GPIO_AFRL_AFSEL1_Pos)                     /*!< 0x00000020 */
#define GPIO_AFRL_AFSEL1_2                        (0x4UL<<GPIO_AFRL_AFSEL1_Pos)                     /*!< 0x00000040 */
#define GPIO_AFRL_AFSEL1_3                        (0x8UL<<GPIO_AFRL_AFSEL1_Pos)                     /*!< 0x00000080 */
#define GPIO_AFRL_AFSEL2_Pos                      (8U)
#define GPIO_AFRL_AFSEL2_Msk                      (0xFUL<<GPIO_AFRL_AFSEL2_Pos)                     /*!< 0x00000F00 */
#define GPIO_AFRL_AFSEL2                          GPIO_AFRL_AFSEL2_Msk                              /*!< GPIO2 AF select */
#define GPIO_AFRL_AFSEL2_0                        (0x1UL<<GPIO_AFRL_AFSEL2_Pos)                     /*!< 0x00000100 */
#define GPIO_AFRL_AFSEL2_1                        (0x2UL<<GPIO_AFRL_AFSEL2_Pos)                     /*!< 0x00000200 */
#define GPIO_AFRL_AFSEL2_2                        (0x4UL<<GPIO_AFRL_AFSEL2_Pos)                     /*!< 0x00000400 */
#define GPIO_AFRL_AFSEL2_3                        (0x8UL<<GPIO_AFRL_AFSEL2_Pos)                     /*!< 0x00000800 */
#define GPIO_AFRL_AFSEL3_Pos                      (12U)
#define GPIO_AFRL_AFSEL3_Msk                      (0xFUL<<GPIO_AFRL_AFSEL3_Pos)                     /*!< 0x0000F000 */
#define GPIO_AFRL_AFSEL3                          GPIO_AFRL_AFSEL3_Msk                              /*!< GPIO3 AF select */
#define GPIO_AFRL_AFSEL3_0                        (0x1UL<<GPIO_AFRL_AFSEL3_Pos)                     /*!< 0x00001000 */
#define GPIO_AFRL_AFSEL3_1                        (0x2UL<<GPIO_AFRL_AFSEL3_Pos)                     /*!< 0x00002000 */
#define GPIO_AFRL_AFSEL3_2                        (0x4UL<<GPIO_AFRL_AFSEL3_Pos)                     /*!< 0x00004000 */
#define GPIO_AFRL_AFSEL3_3                        (0x8UL<<GPIO_AFRL_AFSEL3_Pos)                     /*!< 0x00008000 */
#define GPIO_AFRL_AFSEL4_Pos                      (16U)
#define GPIO_AFRL_AFSEL4_Msk                      (0xFUL<<GPIO_AFRL_AFSEL4_Pos)                     /*!< 0x000F0000 */
#define GPIO_AFRL_AFSEL4                          GPIO_AFRL_AFSEL4_Msk                              /*!< GPIO4 AF select */
#define GPIO_AFRL_AFSEL4_0                        (0x1UL<<GPIO_AFRL_AFSEL4_Pos)                     /*!< 0x00010000 */
#define GPIO_AFRL_AFSEL4_1                        (0x2UL<<GPIO_AFRL_AFSEL4_Pos)                     /*!< 0x00020000 */
#define GPIO_AFRL_AFSEL4_2                        (0x4UL<<GPIO_AFRL_AFSEL4_Pos)                     /*!< 0x00040000 */
#define GPIO_AFRL_AFSEL4_3                        (0x8UL<<GPIO_AFRL_AFSEL4_Pos)                     /*!< 0x00080000 */
#define GPIO_AFRL_AFSEL5_Pos                      (20U)
#define GPIO_AFRL_AFSEL5_Msk                      (0xFUL<<GPIO_AFRL_AFSEL5_Pos)                     /*!< 0x00F00000 */
#define GPIO_AFRL_AFSEL5                          GPIO_AFRL_AFSEL5_Msk                              /*!< GPIO5 AF select */
#define GPIO_AFRL_AFSEL5_0                        (0x1UL<<GPIO_AFRL_AFSEL5_Pos)                     /*!< 0x00100000 */
#define GPIO_AFRL_AFSEL5_1                        (0x2UL<<GPIO_AFRL_AFSEL5_Pos)                     /*!< 0x00200000 */
#define GPIO_AFRL_AFSEL5_2                        (0x4UL<<GPIO_AFRL_AFSEL5_Pos)                     /*!< 0x00400000 */
#define GPIO_AFRL_AFSEL5_3                        (0x8UL<<GPIO_AFRL_AFSEL5_Pos)                     /*!< 0x00800000 */
#define GPIO_AFRL_AFSEL6_Pos                      (24U)
#define GPIO_AFRL_AFSEL6_Msk                      (0xFUL<<GPIO_AFRL_AFSEL6_Pos)                     /*!< 0x0F000000 */
#define GPIO_AFRL_AFSEL6                          GPIO_AFRL_AFSEL6_Msk                              /*!< GPIO6 AF select */
#define GPIO_AFRL_AFSEL6_0                        (0x1UL<<GPIO_AFRL_AFSEL6_Pos)                     /*!< 0x01000000 */
#define GPIO_AFRL_AFSEL6_1                        (0x2UL<<GPIO_AFRL_AFSEL6_Pos)                     /*!< 0x02000000 */
#define GPIO_AFRL_AFSEL6_2                        (0x4UL<<GPIO_AFRL_AFSEL6_Pos)                     /*!< 0x04000000 */
#define GPIO_AFRL_AFSEL6_3                        (0x8UL<<GPIO_AFRL_AFSEL6_Pos)                     /*!< 0x08000000 */
#define GPIO_AFRL_AFSEL7_Pos                      (28U)
#define GPIO_AFRL_AFSEL7_Msk                      (0xFUL<<GPIO_AFRL_AFSEL7_Pos)                     /*!< 0xF0000000 */
#define GPIO_AFRL_AFSEL7                          GPIO_AFRL_AFSEL7_Msk                              /*!< GPIO7 AF select */
#define GPIO_AFRL_AFSEL7_0                        (0x1UL<<GPIO_AFRL_AFSEL7_Pos)                     /*!< 0x10000000 */
#define GPIO_AFRL_AFSEL7_1                        (0x2UL<<GPIO_AFRL_AFSEL7_Pos)                     /*!< 0x20000000 */
#define GPIO_AFRL_AFSEL7_2                        (0x4UL<<GPIO_AFRL_AFSEL7_Pos)                     /*!< 0x40000000 */
#define GPIO_AFRL_AFSEL7_3                        (0x8UL<<GPIO_AFRL_AFSEL7_Pos)                     /*!< 0x80000000 */

/********************************* Bit definition for GPIO_AFRH register ********************************************/
#define GPIO_AFRH_AFSEL8_Pos                      (0U)
#define GPIO_AFRH_AFSEL8_Msk                      (0xFUL<<GPIO_AFRH_AFSEL8_Pos)                     /*!< 0x0000000F */
#define GPIO_AFRH_AFSEL8                          GPIO_AFRH_AFSEL8_Msk                              /*!< GPIO8 AF select */
#define GPIO_AFRH_AFSEL8_0                        (0x1UL<<GPIO_AFRH_AFSEL8_Pos)                     /*!< 0x00000001 */
#define GPIO_AFRH_AFSEL8_1                        (0x2UL<<GPIO_AFRH_AFSEL8_Pos)                     /*!< 0x00000002 */
#define GPIO_AFRH_AFSEL8_2                        (0x4UL<<GPIO_AFRH_AFSEL8_Pos)                     /*!< 0x00000004 */
#define GPIO_AFRH_AFSEL8_3                        (0x8UL<<GPIO_AFRH_AFSEL8_Pos)                     /*!< 0x00000008 */
#define GPIO_AFRH_AFSEL9_Pos                      (4U)
#define GPIO_AFRH_AFSEL9_Msk                      (0xFUL<<GPIO_AFRH_AFSEL9_Pos)                     /*!< 0x000000F0 */
#define GPIO_AFRH_AFSEL9                          GPIO_AFRH_AFSEL9_Msk                              /*!< GPIO9 AF select */
#define GPIO_AFRH_AFSEL9_0                        (0x1UL<<GPIO_AFRH_AFSEL9_Pos)                     /*!< 0x00000010 */
#define GPIO_AFRH_AFSEL9_1                        (0x2UL<<GPIO_AFRH_AFSEL9_Pos)                     /*!< 0x00000020 */
#define GPIO_AFRH_AFSEL9_2                        (0x4UL<<GPIO_AFRH_AFSEL9_Pos)                     /*!< 0x00000040 */
#define GPIO_AFRH_AFSEL9_3                        (0x8UL<<GPIO_AFRH_AFSEL9_Pos)                     /*!< 0x00000080 */
#define GPIO_AFRH_AFSEL10_Pos                     (8U)
#define GPIO_AFRH_AFSEL10_Msk                     (0xFUL<<GPIO_AFRH_AFSEL10_Pos)                    /*!< 0x00000F00 */
#define GPIO_AFRH_AFSEL10                         GPIO_AFRH_AFSEL10_Msk                             /*!< GPIO10 AF select */
#define GPIO_AFRH_AFSEL10_0                       (0x1UL<<GPIO_AFRH_AFSEL10_Pos)                    /*!< 0x00000100 */
#define GPIO_AFRH_AFSEL10_1                       (0x2UL<<GPIO_AFRH_AFSEL10_Pos)                    /*!< 0x00000200 */
#define GPIO_AFRH_AFSEL10_2                       (0x4UL<<GPIO_AFRH_AFSEL10_Pos)                    /*!< 0x00000400 */
#define GPIO_AFRH_AFSEL10_3                       (0x8UL<<GPIO_AFRH_AFSEL10_Pos)                    /*!< 0x00000800 */
#define GPIO_AFRH_AFSEL11_Pos                     (12U)
#define GPIO_AFRH_AFSEL11_Msk                     (0xFUL<<GPIO_AFRH_AFSEL11_Pos)                    /*!< 0x0000F000 */
#define GPIO_AFRH_AFSEL11                         GPIO_AFRH_AFSEL11_Msk                             /*!< GPIO11 AF select */
#define GPIO_AFRH_AFSEL11_0                       (0x1UL<<GPIO_AFRH_AFSEL11_Pos)                    /*!< 0x00001000 */
#define GPIO_AFRH_AFSEL11_1                       (0x2UL<<GPIO_AFRH_AFSEL11_Pos)                    /*!< 0x00002000 */
#define GPIO_AFRH_AFSEL11_2                       (0x4UL<<GPIO_AFRH_AFSEL11_Pos)                    /*!< 0x00004000 */
#define GPIO_AFRH_AFSEL11_3                       (0x8UL<<GPIO_AFRH_AFSEL11_Pos)                    /*!< 0x00008000 */
#define GPIO_AFRH_AFSEL12_Pos                     (16U)
#define GPIO_AFRH_AFSEL12_Msk                     (0xFUL<<GPIO_AFRH_AFSEL12_Pos)                    /*!< 0x000F0000 */
#define GPIO_AFRH_AFSEL12                         GPIO_AFRH_AFSEL12_Msk                             /*!< GPIO12 AF select */
#define GPIO_AFRH_AFSEL12_0                       (0x1UL<<GPIO_AFRH_AFSEL12_Pos)                    /*!< 0x00010000 */
#define GPIO_AFRH_AFSEL12_1                       (0x2UL<<GPIO_AFRH_AFSEL12_Pos)                    /*!< 0x00020000 */
#define GPIO_AFRH_AFSEL12_2                       (0x4UL<<GPIO_AFRH_AFSEL12_Pos)                    /*!< 0x00040000 */
#define GPIO_AFRH_AFSEL12_3                       (0x8UL<<GPIO_AFRH_AFSEL12_Pos)                    /*!< 0x00080000 */
#define GPIO_AFRH_AFSEL13_Pos                     (20U)
#define GPIO_AFRH_AFSEL13_Msk                     (0xFUL<<GPIO_AFRH_AFSEL13_Pos)                    /*!< 0x00F00000 */
#define GPIO_AFRH_AFSEL13                         GPIO_AFRH_AFSEL13_Msk                             /*!< GPIO13 AF select */
#define GPIO_AFRH_AFSEL13_0                       (0x1UL<<GPIO_AFRH_AFSEL13_Pos)                    /*!< 0x00100000 */
#define GPIO_AFRH_AFSEL13_1                       (0x2UL<<GPIO_AFRH_AFSEL13_Pos)                    /*!< 0x00200000 */
#define GPIO_AFRH_AFSEL13_2                       (0x4UL<<GPIO_AFRH_AFSEL13_Pos)                    /*!< 0x00400000 */
#define GPIO_AFRH_AFSEL13_3                       (0x8UL<<GPIO_AFRH_AFSEL13_Pos)                    /*!< 0x00800000 */
#define GPIO_AFRH_AFSEL14_Pos                     (24U)
#define GPIO_AFRH_AFSEL14_Msk                     (0xFUL<<GPIO_AFRH_AFSEL14_Pos)                    /*!< 0x0F000000 */
#define GPIO_AFRH_AFSEL14                         GPIO_AFRH_AFSEL14_Msk                             /*!< GPIO14 AF select */
#define GPIO_AFRH_AFSEL14_0                       (0x1UL<<GPIO_AFRH_AFSEL14_Pos)                    /*!< 0x01000000 */
#define GPIO_AFRH_AFSEL14_1                       (0x2UL<<GPIO_AFRH_AFSEL14_Pos)                    /*!< 0x02000000 */
#define GPIO_AFRH_AFSEL14_2                       (0x4UL<<GPIO_AFRH_AFSEL14_Pos)                    /*!< 0x04000000 */
#define GPIO_AFRH_AFSEL14_3                       (0x8UL<<GPIO_AFRH_AFSEL14_Pos)                    /*!< 0x08000000 */
#define GPIO_AFRH_AFSEL15_Pos                     (28U)
#define GPIO_AFRH_AFSEL15_Msk                     (0xFUL<<GPIO_AFRH_AFSEL15_Pos)                    /*!< 0xF0000000 */
#define GPIO_AFRH_AFSEL15                         GPIO_AFRH_AFSEL15_Msk                             /*!< GPIO15 AF select */
#define GPIO_AFRH_AFSEL15_0                       (0x1UL<<GPIO_AFRH_AFSEL15_Pos)                    /*!< 0x10000000 */
#define GPIO_AFRH_AFSEL15_1                       (0x2UL<<GPIO_AFRH_AFSEL15_Pos)                    /*!< 0x20000000 */
#define GPIO_AFRH_AFSEL15_2                       (0x4UL<<GPIO_AFRH_AFSEL15_Pos)                    /*!< 0x40000000 */
#define GPIO_AFRH_AFSEL15_3                       (0x8UL<<GPIO_AFRH_AFSEL15_Pos)                    /*!< 0x80000000 */

/********************************* Bit definition for GPIO_BRR register *********************************************/
#define GPIO_BRR_BR0_Pos                          (0U)
#define GPIO_BRR_BR0_Msk                          (0x1UL<<GPIO_BRR_BR0_Pos)                         /*!< 0x00000001 */
#define GPIO_BRR_BR0                              GPIO_BRR_BR0_Msk                                  /*!< GPIO 0 output pin reset */
#define GPIO_BRR_BR1_Pos                          (1U)
#define GPIO_BRR_BR1_Msk                          (0x1UL<<GPIO_BRR_BR1_Pos)                         /*!< 0x00000002 */
#define GPIO_BRR_BR1                              GPIO_BRR_BR1_Msk                                  /*!< GPIO 1 output pin reset */
#define GPIO_BRR_BR2_Pos                          (2U)
#define GPIO_BRR_BR2_Msk                          (0x1UL<<GPIO_BRR_BR2_Pos)                         /*!< 0x00000004 */
#define GPIO_BRR_BR2                              GPIO_BRR_BR2_Msk                                  /*!< GPIO 2 output pin reset */
#define GPIO_BRR_BR3_Pos                          (3U)
#define GPIO_BRR_BR3_Msk                          (0x1UL<<GPIO_BRR_BR3_Pos)                         /*!< 0x00000008 */
#define GPIO_BRR_BR3                              GPIO_BRR_BR3_Msk                                  /*!< GPIO 3 output pin reset */
#define GPIO_BRR_BR4_Pos                          (4U)
#define GPIO_BRR_BR4_Msk                          (0x1UL<<GPIO_BRR_BR4_Pos)                         /*!< 0x00000010 */
#define GPIO_BRR_BR4                              GPIO_BRR_BR4_Msk                                  /*!< GPIO 4 output pin reset */
#define GPIO_BRR_BR5_Pos                          (5U)
#define GPIO_BRR_BR5_Msk                          (0x1UL<<GPIO_BRR_BR5_Pos)                         /*!< 0x00000020 */
#define GPIO_BRR_BR5                              GPIO_BRR_BR5_Msk                                  /*!< GPIO 5 output pin reset */
#define GPIO_BRR_BR6_Pos                          (6U)
#define GPIO_BRR_BR6_Msk                          (0x1UL<<GPIO_BRR_BR6_Pos)                         /*!< 0x00000040 */
#define GPIO_BRR_BR6                              GPIO_BRR_BR6_Msk                                  /*!< GPIO 6 output pin reset */
#define GPIO_BRR_BR7_Pos                          (7U)
#define GPIO_BRR_BR7_Msk                          (0x1UL<<GPIO_BRR_BR7_Pos)                         /*!< 0x00000080 */
#define GPIO_BRR_BR7                              GPIO_BRR_BR7_Msk                                  /*!< GPIO 7 output pin reset */
#define GPIO_BRR_BR8_Pos                          (8U)
#define GPIO_BRR_BR8_Msk                          (0x1UL<<GPIO_BRR_BR8_Pos)                         /*!< 0x00000100 */
#define GPIO_BRR_BR8                              GPIO_BRR_BR8_Msk                                  /*!< GPIO 8 output pin reset */
#define GPIO_BRR_BR9_Pos                          (9U)
#define GPIO_BRR_BR9_Msk                          (0x1UL<<GPIO_BRR_BR9_Pos)                         /*!< 0x00000200 */
#define GPIO_BRR_BR9                              GPIO_BRR_BR9_Msk                                  /*!< GPIO 9 output pin reset */
#define GPIO_BRR_BR10_Pos                         (10U)
#define GPIO_BRR_BR10_Msk                         (0x1UL<<GPIO_BRR_BR10_Pos)                        /*!< 0x00000400 */
#define GPIO_BRR_BR10                             GPIO_BRR_BR10_Msk                                 /*!< GPIO 10 output pin reset */
#define GPIO_BRR_BR11_Pos                         (11U)
#define GPIO_BRR_BR11_Msk                         (0x1UL<<GPIO_BRR_BR11_Pos)                        /*!< 0x00000800 */
#define GPIO_BRR_BR11                             GPIO_BRR_BR11_Msk                                 /*!< GPIO 11 output pin reset */
#define GPIO_BRR_BR12_Pos                         (12U)
#define GPIO_BRR_BR12_Msk                         (0x1UL<<GPIO_BRR_BR12_Pos)                        /*!< 0x00001000 */
#define GPIO_BRR_BR12                             GPIO_BRR_BR12_Msk                                 /*!< GPIO 12 output pin reset */
#define GPIO_BRR_BR13_Pos                         (13U)
#define GPIO_BRR_BR13_Msk                         (0x1UL<<GPIO_BRR_BR13_Pos)                        /*!< 0x00002000 */
#define GPIO_BRR_BR13                             GPIO_BRR_BR13_Msk                                 /*!< GPIO 13 output pin reset */
#define GPIO_BRR_BR14_Pos                         (14U)
#define GPIO_BRR_BR14_Msk                         (0x1UL<<GPIO_BRR_BR14_Pos)                        /*!< 0x00004000 */
#define GPIO_BRR_BR14                             GPIO_BRR_BR14_Msk                                 /*!< GPIO 14 output pin reset */
#define GPIO_BRR_BR15_Pos                         (15U)
#define GPIO_BRR_BR15_Msk                         (0x1UL<<GPIO_BRR_BR15_Pos)                        /*!< 0x00008000 */
#define GPIO_BRR_BR15                             GPIO_BRR_BR15_Msk                                 /*!< GPIO 15 output pin reset */

/********************************************************************************************************************/
/********************************* SYSCFG ***************************************************************************/
/********************************************************************************************************************/

/********************************* Bit definition for SYSCFG_CFGR1 register *****************************************/
#define SYSCFG_CFGR1_MEM_MODE_Pos                 (0U)
#define SYSCFG_CFGR1_MEM_MODE_Msk                 (0x3UL<<SYSCFG_CFGR1_MEM_MODE_Pos)                /*!< 0x00000003 */
#define SYSCFG_CFGR1_MEM_MODE                     SYSCFG_CFGR1_MEM_MODE_Msk
#define SYSCFG_CFGR1_MEM_MODE_0                   (0x1UL<<SYSCFG_CFGR1_MEM_MODE_Pos)                /*!< 0x00000001 */
#define SYSCFG_CFGR1_MEM_MODE_1                   (0x2UL<<SYSCFG_CFGR1_MEM_MODE_Pos)                /*!< 0x00000002 */
#define SYSCFG_CFGR1_I2C1_FMP_Pos                 (2U)
#define SYSCFG_CFGR1_I2C1_FMP_Msk                 (0x1UL<<SYSCFG_CFGR1_I2C1_FMP_Pos)                /*!< 0x00000004 */
#define SYSCFG_CFGR1_I2C1_FMP                     SYSCFG_CFGR1_I2C1_FMP_Msk                         
#define SYSCFG_CFGR1_I2C2_FMP_Pos                 (3U)
#define SYSCFG_CFGR1_I2C2_FMP_Msk                 (0x1UL<<SYSCFG_CFGR1_I2C2_FMP_Pos)                /*!< 0x00000008 */
#define SYSCFG_CFGR1_I2C2_FMP                     SYSCFG_CFGR1_I2C2_FMP_Msk                         
#define SYSCFG_CFGR1_I2C1_FLTEN_Pos               (4U)
#define SYSCFG_CFGR1_I2C1_FLTEN_Msk               (0x1UL<<SYSCFG_CFGR1_I2C1_FLTEN_Pos)              /*!< 0x00000010 */
#define SYSCFG_CFGR1_I2C1_FLTEN                   SYSCFG_CFGR1_I2C1_FLTEN_Msk                       
#define SYSCFG_CFGR1_I2C2_FLTEN_Pos               (5U)
#define SYSCFG_CFGR1_I2C2_FLTEN_Msk               (0x1UL<<SYSCFG_CFGR1_I2C2_FLTEN_Pos)              /*!< 0x00000020 */
#define SYSCFG_CFGR1_I2C2_FLTEN                   SYSCFG_CFGR1_I2C2_FLTEN_Msk                       

/********************************* Bit definition for SYSCFG_CFGR2 register *****************************************/
#define SYSCFG_CFGR2_CLL_Pos                      (0U)
#define SYSCFG_CFGR2_CLL_Msk                      (0x1UL<<SYSCFG_CFGR2_CLL_Pos)                     /*!< 0x00000001 */
#define SYSCFG_CFGR2_CLL                          SYSCFG_CFGR2_CLL_Msk                              
#define SYSCFG_CFGR2_PVDL_Pos                     (2U)
#define SYSCFG_CFGR2_PVDL_Msk                     (0x1UL<<SYSCFG_CFGR2_PVDL_Pos)                    /*!< 0x00000004 */
#define SYSCFG_CFGR2_PVDL                         SYSCFG_CFGR2_PVDL_Msk                             

/********************************* Bit definition for SYSCFG_CFGR3 register *****************************************/
#define SYSCFG_CFGR3_DMA_MAP1_Pos                 (0U)
#define SYSCFG_CFGR3_DMA_MAP1_Msk                 (0x7FUL<<SYSCFG_CFGR3_DMA_MAP1_Pos)               /*!< 0x0000007F */
#define SYSCFG_CFGR3_DMA_MAP1                     SYSCFG_CFGR3_DMA_MAP1_Msk
#define SYSCFG_CFGR3_DMA_MAP2_Pos                 (8U)
#define SYSCFG_CFGR3_DMA_MAP2_Msk                 (0x7FUL<<SYSCFG_CFGR3_DMA_MAP2_Pos)               /*!< 0x00007F00 */
#define SYSCFG_CFGR3_DMA_MAP2                     SYSCFG_CFGR3_DMA_MAP2_Msk
#define SYSCFG_CFGR3_DMA_MAP3_Pos                 (16U)
#define SYSCFG_CFGR3_DMA_MAP3_Msk                 (0x7FUL<<SYSCFG_CFGR3_DMA_MAP3_Pos)               /*!< 0x007F0000 */
#define SYSCFG_CFGR3_DMA_MAP3                     SYSCFG_CFGR3_DMA_MAP3_Msk
#define SYSCFG_CFGR3_DMA_MAP4_Pos                 (24U)
#define SYSCFG_CFGR3_DMA_MAP4_Msk                 (0x7FUL<<SYSCFG_CFGR3_DMA_MAP4_Pos)               /*!< 0x7F000000 */
#define SYSCFG_CFGR3_DMA_MAP4                     SYSCFG_CFGR3_DMA_MAP4_Msk

/********************************* Bit definition for SYSCFG_CFGR4 register *****************************************/
#define SYSCFG_CFGR4_DMA_MAP5_Pos                 (0U)
#define SYSCFG_CFGR4_DMA_MAP5_Msk                 (0x7FUL<<SYSCFG_CFGR4_DMA_MAP5_Pos)               /*!< 0x0000007F */
#define SYSCFG_CFGR4_DMA_MAP5                     SYSCFG_CFGR4_DMA_MAP5_Msk

/********************************* Bit definition for SYSCFG_EXTICR1 register ***************************************/
#define SYSCFG_EXTICR1_EXTI0_Pos                  (0U)
#define SYSCFG_EXTICR1_EXTI0_Msk                  (0x3UL<<SYSCFG_EXTICR1_EXTI0_Pos)                 /*!< 0x00000003 */
#define SYSCFG_EXTICR1_EXTI0                      SYSCFG_EXTICR1_EXTI0_Msk
#define SYSCFG_EXTICR1_EXTI0_0                    (0x1UL<<SYSCFG_EXTICR1_EXTI0_Pos)                 /*!< 0x00000001 */
#define SYSCFG_EXTICR1_EXTI0_1                    (0x2UL<<SYSCFG_EXTICR1_EXTI0_Pos)                 /*!< 0x00000002 */
#define SYSCFG_EXTICR1_EXTI1_Pos                  (4U)
#define SYSCFG_EXTICR1_EXTI1_Msk                  (0x3UL<<SYSCFG_EXTICR1_EXTI1_Pos)                 /*!< 0x00000030 */
#define SYSCFG_EXTICR1_EXTI1                      SYSCFG_EXTICR1_EXTI1_Msk
#define SYSCFG_EXTICR1_EXTI1_0                    (0x1UL<<SYSCFG_EXTICR1_EXTI1_Pos)                 /*!< 0x00000010 */
#define SYSCFG_EXTICR1_EXTI1_1                    (0x2UL<<SYSCFG_EXTICR1_EXTI1_Pos)                 /*!< 0x00000020 */
#define SYSCFG_EXTICR1_EXTI2_Pos                  (8U)
#define SYSCFG_EXTICR1_EXTI2_Msk                  (0x3UL<<SYSCFG_EXTICR1_EXTI2_Pos)                 /*!< 0x00000300 */
#define SYSCFG_EXTICR1_EXTI2                      SYSCFG_EXTICR1_EXTI2_Msk
#define SYSCFG_EXTICR1_EXTI2_0                    (0x1UL<<SYSCFG_EXTICR1_EXTI2_Pos)                 /*!< 0x00000100 */
#define SYSCFG_EXTICR1_EXTI2_1                    (0x2UL<<SYSCFG_EXTICR1_EXTI2_Pos)                 /*!< 0x00000200 */
#define SYSCFG_EXTICR1_EXTI3_Pos                  (12U)
#define SYSCFG_EXTICR1_EXTI3_Msk                  (0x3UL<<SYSCFG_EXTICR1_EXTI3_Pos)                 /*!< 0x00003000 */
#define SYSCFG_EXTICR1_EXTI3                      SYSCFG_EXTICR1_EXTI3_Msk
#define SYSCFG_EXTICR1_EXTI3_0                    (0x1UL<<SYSCFG_EXTICR1_EXTI3_Pos)                 /*!< 0x00001000 */
#define SYSCFG_EXTICR1_EXTI3_1                    (0x2UL<<SYSCFG_EXTICR1_EXTI3_Pos)                 /*!< 0x00002000 */

/********************************* Bit definition for SYSCFG_EXTICR2 register ***************************************/
#define SYSCFG_EXTICR2_EXTI4_Pos                  (0U)
#define SYSCFG_EXTICR2_EXTI4_Msk                  (0x3UL<<SYSCFG_EXTICR2_EXTI4_Pos)                 /*!< 0x00000003 */
#define SYSCFG_EXTICR2_EXTI4                      SYSCFG_EXTICR2_EXTI4_Msk
#define SYSCFG_EXTICR2_EXTI4_0                    (0x1UL<<SYSCFG_EXTICR2_EXTI4_Pos)                 /*!< 0x00000001 */
#define SYSCFG_EXTICR2_EXTI4_1                    (0x2UL<<SYSCFG_EXTICR2_EXTI4_Pos)                 /*!< 0x00000002 */
#define SYSCFG_EXTICR2_EXTI5_Pos                  (4U)
#define SYSCFG_EXTICR2_EXTI5_Msk                  (0x3UL<<SYSCFG_EXTICR2_EXTI5_Pos)                 /*!< 0x00000030 */
#define SYSCFG_EXTICR2_EXTI5                      SYSCFG_EXTICR2_EXTI5_Msk
#define SYSCFG_EXTICR2_EXTI5_0                    (0x1UL<<SYSCFG_EXTICR2_EXTI5_Pos)                 /*!< 0x00000010 */
#define SYSCFG_EXTICR2_EXTI5_1                    (0x2UL<<SYSCFG_EXTICR2_EXTI5_Pos)                 /*!< 0x00000020 */
#define SYSCFG_EXTICR2_EXTI6_Pos                  (8U)
#define SYSCFG_EXTICR2_EXTI6_Msk                  (0x3UL<<SYSCFG_EXTICR2_EXTI6_Pos)                 /*!< 0x00000300 */
#define SYSCFG_EXTICR2_EXTI6                      SYSCFG_EXTICR2_EXTI6_Msk
#define SYSCFG_EXTICR2_EXTI6_0                    (0x1UL<<SYSCFG_EXTICR2_EXTI6_Pos)                 /*!< 0x00000100 */
#define SYSCFG_EXTICR2_EXTI6_1                    (0x2UL<<SYSCFG_EXTICR2_EXTI6_Pos)                 /*!< 0x00000200 */
#define SYSCFG_EXTICR2_EXTI7_Pos                  (12U)
#define SYSCFG_EXTICR2_EXTI7_Msk                  (0x3UL<<SYSCFG_EXTICR2_EXTI7_Pos)                 /*!< 0x00003000 */
#define SYSCFG_EXTICR2_EXTI7                      SYSCFG_EXTICR2_EXTI7_Msk
#define SYSCFG_EXTICR2_EXTI7_0                    (0x1UL<<SYSCFG_EXTICR2_EXTI7_Pos)                 /*!< 0x00001000 */
#define SYSCFG_EXTICR2_EXTI7_1                    (0x2UL<<SYSCFG_EXTICR2_EXTI7_Pos)                 /*!< 0x00002000 */

/********************************* Bit definition for SYSCFG_EXTICR3 register ***************************************/
#define SYSCFG_EXTICR3_EXTI8_Pos                  (0U)
#define SYSCFG_EXTICR3_EXTI8_Msk                  (0x3UL<<SYSCFG_EXTICR3_EXTI8_Pos)                 /*!< 0x00000003 */
#define SYSCFG_EXTICR3_EXTI8                      SYSCFG_EXTICR3_EXTI8_Msk
#define SYSCFG_EXTICR3_EXTI8_0                    (0x1UL<<SYSCFG_EXTICR3_EXTI8_Pos)                 /*!< 0x00000001 */
#define SYSCFG_EXTICR3_EXTI8_1                    (0x2UL<<SYSCFG_EXTICR3_EXTI8_Pos)                 /*!< 0x00000002 */
#define SYSCFG_EXTICR3_EXTI9_Pos                  (4U)
#define SYSCFG_EXTICR3_EXTI9_Msk                  (0x3UL<<SYSCFG_EXTICR3_EXTI9_Pos)                 /*!< 0x00000030 */
#define SYSCFG_EXTICR3_EXTI9                      SYSCFG_EXTICR3_EXTI9_Msk
#define SYSCFG_EXTICR3_EXTI9_0                    (0x1UL<<SYSCFG_EXTICR3_EXTI9_Pos)                 /*!< 0x00000010 */
#define SYSCFG_EXTICR3_EXTI9_1                    (0x2UL<<SYSCFG_EXTICR3_EXTI9_Pos)                 /*!< 0x00000020 */
#define SYSCFG_EXTICR3_EXTI10_Pos                 (8U)
#define SYSCFG_EXTICR3_EXTI10_Msk                 (0x3UL<<SYSCFG_EXTICR3_EXTI10_Pos)                /*!< 0x00000300 */
#define SYSCFG_EXTICR3_EXTI10                     SYSCFG_EXTICR3_EXTI10_Msk
#define SYSCFG_EXTICR3_EXTI10_0                   (0x1UL<<SYSCFG_EXTICR3_EXTI10_Pos)                /*!< 0x00000100 */
#define SYSCFG_EXTICR3_EXTI10_1                   (0x2UL<<SYSCFG_EXTICR3_EXTI10_Pos)                /*!< 0x00000200 */
#define SYSCFG_EXTICR3_EXTI11_Pos                 (12U)
#define SYSCFG_EXTICR3_EXTI11_Msk                 (0x3UL<<SYSCFG_EXTICR3_EXTI11_Pos)                /*!< 0x00003000 */
#define SYSCFG_EXTICR3_EXTI11                     SYSCFG_EXTICR3_EXTI11_Msk
#define SYSCFG_EXTICR3_EXTI11_0                   (0x1UL<<SYSCFG_EXTICR3_EXTI11_Pos)                /*!< 0x00001000 */
#define SYSCFG_EXTICR3_EXTI11_1                   (0x2UL<<SYSCFG_EXTICR3_EXTI11_Pos)                /*!< 0x00002000 */

/********************************* Bit definition for SYSCFG_EXTICR4 register ***************************************/
#define SYSCFG_EXTICR4_EXTI12_Pos                 (0U)
#define SYSCFG_EXTICR4_EXTI12_Msk                 (0x3UL<<SYSCFG_EXTICR4_EXTI12_Pos)                /*!< 0x00000003 */
#define SYSCFG_EXTICR4_EXTI12                     SYSCFG_EXTICR4_EXTI12_Msk
#define SYSCFG_EXTICR4_EXTI12_0                   (0x1UL<<SYSCFG_EXTICR4_EXTI12_Pos)                /*!< 0x00000001 */
#define SYSCFG_EXTICR4_EXTI12_1                   (0x2UL<<SYSCFG_EXTICR4_EXTI12_Pos)                /*!< 0x00000002 */
#define SYSCFG_EXTICR4_EXTI13_Pos                 (4U)
#define SYSCFG_EXTICR4_EXTI13_Msk                 (0x3UL<<SYSCFG_EXTICR4_EXTI13_Pos)                /*!< 0x00000030 */
#define SYSCFG_EXTICR4_EXTI13                     SYSCFG_EXTICR4_EXTI13_Msk
#define SYSCFG_EXTICR4_EXTI13_0                   (0x1UL<<SYSCFG_EXTICR4_EXTI13_Pos)                /*!< 0x00000010 */
#define SYSCFG_EXTICR4_EXTI13_1                   (0x2UL<<SYSCFG_EXTICR4_EXTI13_Pos)                /*!< 0x00000020 */
#define SYSCFG_EXTICR4_EXTI14_Pos                 (8U)
#define SYSCFG_EXTICR4_EXTI14_Msk                 (0x3UL<<SYSCFG_EXTICR4_EXTI14_Pos)                /*!< 0x00000300 */
#define SYSCFG_EXTICR4_EXTI14                     SYSCFG_EXTICR4_EXTI14_Msk
#define SYSCFG_EXTICR4_EXTI14_0                   (0x1UL<<SYSCFG_EXTICR4_EXTI14_Pos)                /*!< 0x00000100 */
#define SYSCFG_EXTICR4_EXTI14_1                   (0x2UL<<SYSCFG_EXTICR4_EXTI14_Pos)                /*!< 0x00000200 */
#define SYSCFG_EXTICR4_EXTI15_Pos                 (12U)
#define SYSCFG_EXTICR4_EXTI15_Msk                 (0x3UL<<SYSCFG_EXTICR4_EXTI15_Pos)                /*!< 0x00003000 */
#define SYSCFG_EXTICR4_EXTI15                     SYSCFG_EXTICR4_EXTI15_Msk
#define SYSCFG_EXTICR4_EXTI15_0                   (0x1UL<<SYSCFG_EXTICR4_EXTI15_Pos)                /*!< 0x00001000 */
#define SYSCFG_EXTICR4_EXTI15_1                   (0x2UL<<SYSCFG_EXTICR4_EXTI15_Pos)                /*!< 0x00002000 */

/********************************* Bit definition for SYSCFG_PAENS register *****************************************/
#define SYSCFG_PAENS_PA_ENS_Pos                   (0U)
#define SYSCFG_PAENS_PA_ENS_Msk                   (0xFFFFUL<<SYSCFG_PAENS_PA_ENS_Pos)               /*!< 0x0000FFFF */
#define SYSCFG_PAENS_PA_ENS                       SYSCFG_PAENS_PA_ENS_Msk

/********************************* Bit definition for SYSCFG_PBENS register *****************************************/
#define SYSCFG_PBENS_PB_ENS_Pos                   (0U)
#define SYSCFG_PBENS_PB_ENS_Msk                   (0xFFFFUL<<SYSCFG_PBENS_PB_ENS_Pos)               /*!< 0x0000FFFF */
#define SYSCFG_PBENS_PB_ENS                       SYSCFG_PBENS_PB_ENS_Msk

/********************************* Bit definition for SYSCFG_PCENS register *****************************************/
#define SYSCFG_PCENS_PC_ENS_Pos                   (0U)
#define SYSCFG_PCENS_PC_ENS_Msk                   (0xFFFFUL<<SYSCFG_PCENS_PC_ENS_Pos)               /*!< 0x0000FFFF */
#define SYSCFG_PCENS_PC_ENS                       SYSCFG_PCENS_PC_ENS_Msk

/********************************* Bit definition for SYSCFG_PDENS register *****************************************/
#define SYSCFG_PDENS_PD_ENS_Pos                   (0U)
#define SYSCFG_PDENS_PD_ENS_Msk                   (0xFFFUL<<SYSCFG_PDENS_PD_ENS_Pos)                /*!< 0x00000FFF */
#define SYSCFG_PDENS_PD_ENS                       SYSCFG_PDENS_PD_ENS_Msk

/********************************************************************************************************************/
/********************************* BKP ******************************************************************************/
/********************************************************************************************************************/

/********************************* Bit definition for BKP_DR0 register **********************************************/
#define BKP_DR0_D_Pos                             (0U)
#define BKP_DR0_D_Msk                             (0xFFFFFFFFUL<<BKP_DR0_D_Pos)                     /*!< 0xFFFFFFFF */
#define BKP_DR0_D                                 BKP_DR0_D_Msk

/********************************* Bit definition for BKP_DR1 register **********************************************/
#define BKP_DR1_D_Pos                             (0U)
#define BKP_DR1_D_Msk                             (0xFFFFFFFFUL<<BKP_DR1_D_Pos)                     /*!< 0xFFFFFFFF */
#define BKP_DR1_D                                 BKP_DR1_D_Msk

/********************************* Bit definition for BKP_DR2 register **********************************************/
#define BKP_DR2_D_Pos                             (0U)
#define BKP_DR2_D_Msk                             (0xFFFFFFFFUL<<BKP_DR2_D_Pos)                     /*!< 0xFFFFFFFF */
#define BKP_DR2_D                                 BKP_DR2_D_Msk

/********************************* Bit definition for BKP_DR3 register **********************************************/
#define BKP_DR3_D_Pos                             (0U)
#define BKP_DR3_D_Msk                             (0xFFFFFFFFUL<<BKP_DR3_D_Pos)                     /*!< 0xFFFFFFFF */
#define BKP_DR3_D                                 BKP_DR3_D_Msk

/********************************* Bit definition for BKP_DR4 register **********************************************/
#define BKP_DR4_D_Pos                             (0U)
#define BKP_DR4_D_Msk                             (0xFFFFFFFFUL<<BKP_DR4_D_Pos)                     /*!< 0xFFFFFFFF */
#define BKP_DR4_D                                 BKP_DR4_D_Msk

/********************************************************************************************************************/
/********************************* DMA ******************************************************************************/
/********************************************************************************************************************/

/********************************* Bit definition for DMA_ISR register **********************************************/
#define DMA_ISR_TCIF1_Pos                         (0U)
#define DMA_ISR_TCIF1_Msk                         (0x1UL<<DMA_ISR_TCIF1_Pos)                        /*!< 0x00000001 */
#define DMA_ISR_TCIF1                             DMA_ISR_TCIF1_Msk                                 
#define DMA_ISR_BTCIF1_Pos                        (1U)
#define DMA_ISR_BTCIF1_Msk                        (0x1UL<<DMA_ISR_BTCIF1_Pos)                       /*!< 0x00000002 */
#define DMA_ISR_BTCIF1                            DMA_ISR_BTCIF1_Msk                                
#define DMA_ISR_HBTIF1_Pos                        (2U)
#define DMA_ISR_HBTIF1_Msk                        (0x1UL<<DMA_ISR_HBTIF1_Pos)                       /*!< 0x00000004 */
#define DMA_ISR_HBTIF1                            DMA_ISR_HBTIF1_Msk                                
#define DMA_ISR_TEIF1_Pos                         (3U)
#define DMA_ISR_TEIF1_Msk                         (0x1UL<<DMA_ISR_TEIF1_Pos)                        /*!< 0x00000008 */
#define DMA_ISR_TEIF1                             DMA_ISR_TEIF1_Msk                                 
#define DMA_ISR_TCIF2_Pos                         (4U)
#define DMA_ISR_TCIF2_Msk                         (0x1UL<<DMA_ISR_TCIF2_Pos)                        /*!< 0x00000010 */
#define DMA_ISR_TCIF2                             DMA_ISR_TCIF2_Msk                                 
#define DMA_ISR_BTCIF2_Pos                        (5U)
#define DMA_ISR_BTCIF2_Msk                        (0x1UL<<DMA_ISR_BTCIF2_Pos)                       /*!< 0x00000020 */
#define DMA_ISR_BTCIF2                            DMA_ISR_BTCIF2_Msk                                
#define DMA_ISR_HBTIF2_Pos                        (6U)
#define DMA_ISR_HBTIF2_Msk                        (0x1UL<<DMA_ISR_HBTIF2_Pos)                       /*!< 0x00000040 */
#define DMA_ISR_HBTIF2                            DMA_ISR_HBTIF2_Msk                                
#define DMA_ISR_TEIF2_Pos                         (7U)
#define DMA_ISR_TEIF2_Msk                         (0x1UL<<DMA_ISR_TEIF2_Pos)                        /*!< 0x00000080 */
#define DMA_ISR_TEIF2                             DMA_ISR_TEIF2_Msk                                 
#define DMA_ISR_TCIF3_Pos                         (8U)
#define DMA_ISR_TCIF3_Msk                         (0x1UL<<DMA_ISR_TCIF3_Pos)                        /*!< 0x00000100 */
#define DMA_ISR_TCIF3                             DMA_ISR_TCIF3_Msk                                 
#define DMA_ISR_BTCIF3_Pos                        (9U)
#define DMA_ISR_BTCIF3_Msk                        (0x1UL<<DMA_ISR_BTCIF3_Pos)                       /*!< 0x00000200 */
#define DMA_ISR_BTCIF3                            DMA_ISR_BTCIF3_Msk                                
#define DMA_ISR_HBTIF3_Pos                        (10U)
#define DMA_ISR_HBTIF3_Msk                        (0x1UL<<DMA_ISR_HBTIF3_Pos)                       /*!< 0x00000400 */
#define DMA_ISR_HBTIF3                            DMA_ISR_HBTIF3_Msk                                
#define DMA_ISR_TEIF3_Pos                         (11U)
#define DMA_ISR_TEIF3_Msk                         (0x1UL<<DMA_ISR_TEIF3_Pos)                        /*!< 0x00000800 */
#define DMA_ISR_TEIF3                             DMA_ISR_TEIF3_Msk                                 
#define DMA_ISR_TCIF4_Pos                         (12U)
#define DMA_ISR_TCIF4_Msk                         (0x1UL<<DMA_ISR_TCIF4_Pos)                        /*!< 0x00001000 */
#define DMA_ISR_TCIF4                             DMA_ISR_TCIF4_Msk                                 
#define DMA_ISR_BTCIF4_Pos                        (13U)
#define DMA_ISR_BTCIF4_Msk                        (0x1UL<<DMA_ISR_BTCIF4_Pos)                       /*!< 0x00002000 */
#define DMA_ISR_BTCIF4                            DMA_ISR_BTCIF4_Msk                                
#define DMA_ISR_HBTIF4_Pos                        (14U)
#define DMA_ISR_HBTIF4_Msk                        (0x1UL<<DMA_ISR_HBTIF4_Pos)                       /*!< 0x00004000 */
#define DMA_ISR_HBTIF4                            DMA_ISR_HBTIF4_Msk                                
#define DMA_ISR_TEIF4_Pos                         (15U)
#define DMA_ISR_TEIF4_Msk                         (0x1UL<<DMA_ISR_TEIF4_Pos)                        /*!< 0x00008000 */
#define DMA_ISR_TEIF4                             DMA_ISR_TEIF4_Msk                                 
#define DMA_ISR_TCIF5_Pos                         (16U)
#define DMA_ISR_TCIF5_Msk                         (0x1UL<<DMA_ISR_TCIF5_Pos)                        /*!< 0x00010000 */
#define DMA_ISR_TCIF5                             DMA_ISR_TCIF5_Msk                                 
#define DMA_ISR_BTCIF5_Pos                        (17U)
#define DMA_ISR_BTCIF5_Msk                        (0x1UL<<DMA_ISR_BTCIF5_Pos)                       /*!< 0x00020000 */
#define DMA_ISR_BTCIF5                            DMA_ISR_BTCIF5_Msk                                
#define DMA_ISR_HBTIF5_Pos                        (18U)
#define DMA_ISR_HBTIF5_Msk                        (0x1UL<<DMA_ISR_HBTIF5_Pos)                       /*!< 0x00040000 */
#define DMA_ISR_HBTIF5                            DMA_ISR_HBTIF5_Msk                                
#define DMA_ISR_TEIF5_Pos                         (19U)
#define DMA_ISR_TEIF5_Msk                         (0x1UL<<DMA_ISR_TEIF5_Pos)                        /*!< 0x00080000 */
#define DMA_ISR_TEIF5                             DMA_ISR_TEIF5_Msk                                 

/********************************* Bit definition for DMA_IFCR register *********************************************/
#define DMA_IFCR_CTCIF1_Pos                       (0U)
#define DMA_IFCR_CTCIF1_Msk                       (0x1UL<<DMA_IFCR_CTCIF1_Pos)                      /*!< 0x00000001 */
#define DMA_IFCR_CTCIF1                           DMA_IFCR_CTCIF1_Msk                               
#define DMA_IFCR_CBTCIF1_Pos                      (1U)
#define DMA_IFCR_CBTCIF1_Msk                      (0x1UL<<DMA_IFCR_CBTCIF1_Pos)                     /*!< 0x00000002 */
#define DMA_IFCR_CBTCIF1                          DMA_IFCR_CBTCIF1_Msk                              
#define DMA_IFCR_CHBTIF1_Pos                      (2U)
#define DMA_IFCR_CHBTIF1_Msk                      (0x1UL<<DMA_IFCR_CHBTIF1_Pos)                     /*!< 0x00000004 */
#define DMA_IFCR_CHBTIF1                          DMA_IFCR_CHBTIF1_Msk                              
#define DMA_IFCR_CTEIF1_Pos                       (3U)
#define DMA_IFCR_CTEIF1_Msk                       (0x1UL<<DMA_IFCR_CTEIF1_Pos)                      /*!< 0x00000008 */
#define DMA_IFCR_CTEIF1                           DMA_IFCR_CTEIF1_Msk                               
#define DMA_IFCR_CTCIF2_Pos                       (4U)
#define DMA_IFCR_CTCIF2_Msk                       (0x1UL<<DMA_IFCR_CTCIF2_Pos)                      /*!< 0x00000010 */
#define DMA_IFCR_CTCIF2                           DMA_IFCR_CTCIF2_Msk                               
#define DMA_IFCR_CBTCIF2_Pos                      (5U)
#define DMA_IFCR_CBTCIF2_Msk                      (0x1UL<<DMA_IFCR_CBTCIF2_Pos)                     /*!< 0x00000020 */
#define DMA_IFCR_CBTCIF2                          DMA_IFCR_CBTCIF2_Msk                              
#define DMA_IFCR_CHBTIF2_Pos                      (6U)
#define DMA_IFCR_CHBTIF2_Msk                      (0x1UL<<DMA_IFCR_CHBTIF2_Pos)                     /*!< 0x00000040 */
#define DMA_IFCR_CHBTIF2                          DMA_IFCR_CHBTIF2_Msk                              
#define DMA_IFCR_CTEIF2_Pos                       (7U)
#define DMA_IFCR_CTEIF2_Msk                       (0x1UL<<DMA_IFCR_CTEIF2_Pos)                      /*!< 0x00000080 */
#define DMA_IFCR_CTEIF2                           DMA_IFCR_CTEIF2_Msk                               
#define DMA_IFCR_CTCIF3_Pos                       (8U)
#define DMA_IFCR_CTCIF3_Msk                       (0x1UL<<DMA_IFCR_CTCIF3_Pos)                      /*!< 0x00000100 */
#define DMA_IFCR_CTCIF3                           DMA_IFCR_CTCIF3_Msk                               
#define DMA_IFCR_CBTCIF3_Pos                      (9U)
#define DMA_IFCR_CBTCIF3_Msk                      (0x1UL<<DMA_IFCR_CBTCIF3_Pos)                     /*!< 0x00000200 */
#define DMA_IFCR_CBTCIF3                          DMA_IFCR_CBTCIF3_Msk                              
#define DMA_IFCR_CHBTIF3_Pos                      (10U)
#define DMA_IFCR_CHBTIF3_Msk                      (0x1UL<<DMA_IFCR_CHBTIF3_Pos)                     /*!< 0x00000400 */
#define DMA_IFCR_CHBTIF3                          DMA_IFCR_CHBTIF3_Msk                              
#define DMA_IFCR_CTEIF3_Pos                       (11U)
#define DMA_IFCR_CTEIF3_Msk                       (0x1UL<<DMA_IFCR_CTEIF3_Pos)                      /*!< 0x00000800 */
#define DMA_IFCR_CTEIF3                           DMA_IFCR_CTEIF3_Msk                               
#define DMA_IFCR_CTCIF4_Pos                       (12U)
#define DMA_IFCR_CTCIF4_Msk                       (0x1UL<<DMA_IFCR_CTCIF4_Pos)                      /*!< 0x00001000 */
#define DMA_IFCR_CTCIF4                           DMA_IFCR_CTCIF4_Msk                               
#define DMA_IFCR_CBTCIF4_Pos                      (13U)
#define DMA_IFCR_CBTCIF4_Msk                      (0x1UL<<DMA_IFCR_CBTCIF4_Pos)                     /*!< 0x00002000 */
#define DMA_IFCR_CBTCIF4                          DMA_IFCR_CBTCIF4_Msk                              
#define DMA_IFCR_CHBTIF4_Pos                      (14U)
#define DMA_IFCR_CHBTIF4_Msk                      (0x1UL<<DMA_IFCR_CHBTIF4_Pos)                     /*!< 0x00004000 */
#define DMA_IFCR_CHBTIF4                          DMA_IFCR_CHBTIF4_Msk                              
#define DMA_IFCR_CTEIF4_Pos                       (15U)
#define DMA_IFCR_CTEIF4_Msk                       (0x1UL<<DMA_IFCR_CTEIF4_Pos)                      /*!< 0x00008000 */
#define DMA_IFCR_CTEIF4                           DMA_IFCR_CTEIF4_Msk                               
#define DMA_IFCR_CTCIF5_Pos                       (16U)
#define DMA_IFCR_CTCIF5_Msk                       (0x1UL<<DMA_IFCR_CTCIF5_Pos)                      /*!< 0x00010000 */
#define DMA_IFCR_CTCIF5                           DMA_IFCR_CTCIF5_Msk                               
#define DMA_IFCR_CBTCIF5_Pos                      (17U)
#define DMA_IFCR_CBTCIF5_Msk                      (0x1UL<<DMA_IFCR_CBTCIF5_Pos)                     /*!< 0x00020000 */
#define DMA_IFCR_CBTCIF5                          DMA_IFCR_CBTCIF5_Msk                              
#define DMA_IFCR_CHBTIF5_Pos                      (18U)
#define DMA_IFCR_CHBTIF5_Msk                      (0x1UL<<DMA_IFCR_CHBTIF5_Pos)                     /*!< 0x00040000 */
#define DMA_IFCR_CHBTIF5                          DMA_IFCR_CHBTIF5_Msk                              
#define DMA_IFCR_CTEIF5_Pos                       (19U)
#define DMA_IFCR_CTEIF5_Msk                       (0x1UL<<DMA_IFCR_CTEIF5_Pos)                      /*!< 0x00080000 */
#define DMA_IFCR_CTEIF5                           DMA_IFCR_CTEIF5_Msk                               

/********************************* Bit definition for DMA_CCR1 register *********************************************/
#define DMA_CCR1_EN_Pos                           (0U)
#define DMA_CCR1_EN_Msk                           (0x1UL<<DMA_CCR1_EN_Pos)                          /*!< 0x00000001 */
#define DMA_CCR1_EN                               DMA_CCR1_EN_Msk                                   
#define DMA_CCR1_TCIE_Pos                         (1U)
#define DMA_CCR1_TCIE_Msk                         (0x1UL<<DMA_CCR1_TCIE_Pos)                        /*!< 0x00000002 */
#define DMA_CCR1_TCIE                             DMA_CCR1_TCIE_Msk                                 
#define DMA_CCR1_BTCIE_Pos                        (2U)
#define DMA_CCR1_BTCIE_Msk                        (0x1UL<<DMA_CCR1_BTCIE_Pos)                       /*!< 0x00000004 */
#define DMA_CCR1_BTCIE                            DMA_CCR1_BTCIE_Msk                                
#define DMA_CCR1_HBTIE_Pos                        (3U)
#define DMA_CCR1_HBTIE_Msk                        (0x1UL<<DMA_CCR1_HBTIE_Pos)                       /*!< 0x00000008 */
#define DMA_CCR1_HBTIE                            DMA_CCR1_HBTIE_Msk                                
#define DMA_CCR1_TEIE_Pos                         (4U)
#define DMA_CCR1_TEIE_Msk                         (0x1UL<<DMA_CCR1_TEIE_Pos)                        /*!< 0x00000010 */
#define DMA_CCR1_TEIE                             DMA_CCR1_TEIE_Msk                                 
#define DMA_CCR1_DIR_Pos                          (5U)
#define DMA_CCR1_DIR_Msk                          (0x1UL<<DMA_CCR1_DIR_Pos)                         /*!< 0x00000020 */
#define DMA_CCR1_DIR                              DMA_CCR1_DIR_Msk                                  
#define DMA_CCR1_CIRC_Pos                         (6U)
#define DMA_CCR1_CIRC_Msk                         (0x1UL<<DMA_CCR1_CIRC_Pos)                        /*!< 0x00000040 */
#define DMA_CCR1_CIRC                             DMA_CCR1_CIRC_Msk                                 
#define DMA_CCR1_TRANST_Pos                       (7U)
#define DMA_CCR1_TRANST_Msk                       (0x1UL<<DMA_CCR1_TRANST_Pos)                      /*!< 0x00000080 */
#define DMA_CCR1_TRANST                           DMA_CCR1_TRANST_Msk                               
#define DMA_CCR1_PINC_Pos                         (8U)
#define DMA_CCR1_PINC_Msk                         (0x3UL<<DMA_CCR1_PINC_Pos)                        /*!< 0x00000300 */
#define DMA_CCR1_PINC                             DMA_CCR1_PINC_Msk
#define DMA_CCR1_PINC_0                           (0x1UL<<DMA_CCR1_PINC_Pos)                        /*!< 0x00000100 */
#define DMA_CCR1_PINC_1                           (0x2UL<<DMA_CCR1_PINC_Pos)                        /*!< 0x00000200 */
#define DMA_CCR1_MINC_Pos                         (10U)
#define DMA_CCR1_MINC_Msk                         (0x3UL<<DMA_CCR1_MINC_Pos)                        /*!< 0x00000C00 */
#define DMA_CCR1_MINC                             DMA_CCR1_MINC_Msk
#define DMA_CCR1_MINC_0                           (0x1UL<<DMA_CCR1_MINC_Pos)                        /*!< 0x00000400 */
#define DMA_CCR1_MINC_1                           (0x2UL<<DMA_CCR1_MINC_Pos)                        /*!< 0x00000800 */
#define DMA_CCR1_PSIZE_Pos                        (12U)
#define DMA_CCR1_PSIZE_Msk                        (0x3UL<<DMA_CCR1_PSIZE_Pos)                       /*!< 0x00003000 */
#define DMA_CCR1_PSIZE                            DMA_CCR1_PSIZE_Msk
#define DMA_CCR1_PSIZE_0                          (0x1UL<<DMA_CCR1_PSIZE_Pos)                       /*!< 0x00001000 */
#define DMA_CCR1_PSIZE_1                          (0x2UL<<DMA_CCR1_PSIZE_Pos)                       /*!< 0x00002000 */
#define DMA_CCR1_MSIZE_Pos                        (14U)
#define DMA_CCR1_MSIZE_Msk                        (0x3UL<<DMA_CCR1_MSIZE_Pos)                       /*!< 0x0000C000 */
#define DMA_CCR1_MSIZE                            DMA_CCR1_MSIZE_Msk
#define DMA_CCR1_MSIZE_0                          (0x1UL<<DMA_CCR1_MSIZE_Pos)                       /*!< 0x00004000 */
#define DMA_CCR1_MSIZE_1                          (0x2UL<<DMA_CCR1_MSIZE_Pos)                       /*!< 0x00008000 */
#define DMA_CCR1_PL_Pos                           (16U)
#define DMA_CCR1_PL_Msk                           (0x7UL<<DMA_CCR1_PL_Pos)                          /*!< 0x00070000 */
#define DMA_CCR1_PL                               DMA_CCR1_PL_Msk
#define DMA_CCR1_PL_0                             (0x1UL<<DMA_CCR1_PL_Pos)                          /*!< 0x00010000 */
#define DMA_CCR1_PL_1                             (0x2UL<<DMA_CCR1_PL_Pos)                          /*!< 0x00020000 */
#define DMA_CCR1_PL_2                             (0x4UL<<DMA_CCR1_PL_Pos)                          /*!< 0x00040000 */
#define DMA_CCR1_MEM2MEM_Pos                      (19U)
#define DMA_CCR1_MEM2MEM_Msk                      (0x1UL<<DMA_CCR1_MEM2MEM_Pos)                     /*!< 0x00080000 */
#define DMA_CCR1_MEM2MEM                          DMA_CCR1_MEM2MEM_Msk                              
#define DMA_CCR1_PNORLD_Pos                       (20U)
#define DMA_CCR1_PNORLD_Msk                       (0x1UL<<DMA_CCR1_PNORLD_Pos)                      /*!< 0x00100000 */
#define DMA_CCR1_PNORLD                           DMA_CCR1_PNORLD_Msk                               
#define DMA_CCR1_MNORLD_Pos                       (21U)
#define DMA_CCR1_MNORLD_Msk                       (0x1UL<<DMA_CCR1_MNORLD_Pos)                      /*!< 0x00200000 */
#define DMA_CCR1_MNORLD                           DMA_CCR1_MNORLD_Msk                               
#define DMA_CCR1_BTCSUSP_Pos                      (22U)
#define DMA_CCR1_BTCSUSP_Msk                      (0x1UL<<DMA_CCR1_BTCSUSP_Pos)                     /*!< 0x00400000 */
#define DMA_CCR1_BTCSUSP                          DMA_CCR1_BTCSUSP_Msk                              
#define DMA_CCR1_M2MARB_Pos                       (23U)
#define DMA_CCR1_M2MARB_Msk                       (0x1UL<<DMA_CCR1_M2MARB_Pos)                      /*!< 0x00800000 */
#define DMA_CCR1_M2MARB                           DMA_CCR1_M2MARB_Msk                               

/********************************* Bit definition for DMA_CNDTR1 register *******************************************/
#define DMA_CNDTR1_NDT_Pos                        (0U)
#define DMA_CNDTR1_NDT_Msk                        (0xFFFFUL<<DMA_CNDTR1_NDT_Pos)                    /*!< 0x0000FFFF */
#define DMA_CNDTR1_NDT                            DMA_CNDTR1_NDT_Msk

/********************************* Bit definition for DMA_CPAR1 register ********************************************/
#define DMA_CPAR1_PA_Pos                          (0U)
#define DMA_CPAR1_PA_Msk                          (0xFFFFFFFFUL<<DMA_CPAR1_PA_Pos)                  /*!< 0xFFFFFFFF */
#define DMA_CPAR1_PA                              DMA_CPAR1_PA_Msk

/********************************* Bit definition for DMA_CMAR1 register ********************************************/
#define DMA_CMAR1_MA_Pos                          (0U)
#define DMA_CMAR1_MA_Msk                          (0xFFFFFFFFUL<<DMA_CMAR1_MA_Pos)                  /*!< 0xFFFFFFFF */
#define DMA_CMAR1_MA                              DMA_CMAR1_MA_Msk

/********************************* Bit definition for DMA_CCCFGR1 register ******************************************/
#define DMA_CCCFGR1_NBT_Pos                       (0U)
#define DMA_CCCFGR1_NBT_Msk                       (0xFFUL<<DMA_CCCFGR1_NBT_Pos)                     /*!< 0x000000FF */
#define DMA_CCCFGR1_NBT                           DMA_CCCFGR1_NBT_Msk
#define DMA_CCCFGR1_NDTL_Pos                      (16U)
#define DMA_CCCFGR1_NDTL_Msk                      (0xFFFFUL<<DMA_CCCFGR1_NDTL_Pos)                  /*!< 0xFFFF0000 */
#define DMA_CCCFGR1_NDTL                          DMA_CCCFGR1_NDTL_Msk

/********************************* Bit definition for DMA_CCR2 register *********************************************/
#define DMA_CCR2_EN_Pos                           (0U)
#define DMA_CCR2_EN_Msk                           (0x1UL<<DMA_CCR2_EN_Pos)                          /*!< 0x00000001 */
#define DMA_CCR2_EN                               DMA_CCR2_EN_Msk                                   
#define DMA_CCR2_TCIE_Pos                         (1U)
#define DMA_CCR2_TCIE_Msk                         (0x1UL<<DMA_CCR2_TCIE_Pos)                        /*!< 0x00000002 */
#define DMA_CCR2_TCIE                             DMA_CCR2_TCIE_Msk                                 
#define DMA_CCR2_BTCIE_Pos                        (2U)
#define DMA_CCR2_BTCIE_Msk                        (0x1UL<<DMA_CCR2_BTCIE_Pos)                       /*!< 0x00000004 */
#define DMA_CCR2_BTCIE                            DMA_CCR2_BTCIE_Msk                                
#define DMA_CCR2_HBTIE_Pos                        (3U)
#define DMA_CCR2_HBTIE_Msk                        (0x1UL<<DMA_CCR2_HBTIE_Pos)                       /*!< 0x00000008 */
#define DMA_CCR2_HBTIE                            DMA_CCR2_HBTIE_Msk                                
#define DMA_CCR2_TEIE_Pos                         (4U)
#define DMA_CCR2_TEIE_Msk                         (0x1UL<<DMA_CCR2_TEIE_Pos)                        /*!< 0x00000010 */
#define DMA_CCR2_TEIE                             DMA_CCR2_TEIE_Msk                                 
#define DMA_CCR2_DIR_Pos                          (5U)
#define DMA_CCR2_DIR_Msk                          (0x1UL<<DMA_CCR2_DIR_Pos)                         /*!< 0x00000020 */
#define DMA_CCR2_DIR                              DMA_CCR2_DIR_Msk                                  
#define DMA_CCR2_CIRC_Pos                         (6U)
#define DMA_CCR2_CIRC_Msk                         (0x1UL<<DMA_CCR2_CIRC_Pos)                        /*!< 0x00000040 */
#define DMA_CCR2_CIRC                             DMA_CCR2_CIRC_Msk                                 
#define DMA_CCR2_TRANST_Pos                       (7U)
#define DMA_CCR2_TRANST_Msk                       (0x1UL<<DMA_CCR2_TRANST_Pos)                      /*!< 0x00000080 */
#define DMA_CCR2_TRANST                           DMA_CCR2_TRANST_Msk                               
#define DMA_CCR2_PINC_Pos                         (8U)
#define DMA_CCR2_PINC_Msk                         (0x3UL<<DMA_CCR2_PINC_Pos)                        /*!< 0x00000300 */
#define DMA_CCR2_PINC                             DMA_CCR2_PINC_Msk
#define DMA_CCR2_PINC_0                           (0x1UL<<DMA_CCR2_PINC_Pos)                        /*!< 0x00000100 */
#define DMA_CCR2_PINC_1                           (0x2UL<<DMA_CCR2_PINC_Pos)                        /*!< 0x00000200 */
#define DMA_CCR2_MINC_Pos                         (10U)
#define DMA_CCR2_MINC_Msk                         (0x3UL<<DMA_CCR2_MINC_Pos)                        /*!< 0x00000C00 */
#define DMA_CCR2_MINC                             DMA_CCR2_MINC_Msk
#define DMA_CCR2_MINC_0                           (0x1UL<<DMA_CCR2_MINC_Pos)                        /*!< 0x00000400 */
#define DMA_CCR2_MINC_1                           (0x2UL<<DMA_CCR2_MINC_Pos)                        /*!< 0x00000800 */
#define DMA_CCR2_PSIZE_Pos                        (12U)
#define DMA_CCR2_PSIZE_Msk                        (0x3UL<<DMA_CCR2_PSIZE_Pos)                       /*!< 0x00003000 */
#define DMA_CCR2_PSIZE                            DMA_CCR2_PSIZE_Msk
#define DMA_CCR2_PSIZE_0                          (0x1UL<<DMA_CCR2_PSIZE_Pos)                       /*!< 0x00001000 */
#define DMA_CCR2_PSIZE_1                          (0x2UL<<DMA_CCR2_PSIZE_Pos)                       /*!< 0x00002000 */
#define DMA_CCR2_MSIZE_Pos                        (14U)
#define DMA_CCR2_MSIZE_Msk                        (0x3UL<<DMA_CCR2_MSIZE_Pos)                       /*!< 0x0000C000 */
#define DMA_CCR2_MSIZE                            DMA_CCR2_MSIZE_Msk
#define DMA_CCR2_MSIZE_0                          (0x1UL<<DMA_CCR2_MSIZE_Pos)                       /*!< 0x00004000 */
#define DMA_CCR2_MSIZE_1                          (0x2UL<<DMA_CCR2_MSIZE_Pos)                       /*!< 0x00008000 */
#define DMA_CCR2_PL_Pos                           (16U)
#define DMA_CCR2_PL_Msk                           (0x7UL<<DMA_CCR2_PL_Pos)                          /*!< 0x00070000 */
#define DMA_CCR2_PL                               DMA_CCR2_PL_Msk
#define DMA_CCR2_PL_0                             (0x1UL<<DMA_CCR2_PL_Pos)                          /*!< 0x00010000 */
#define DMA_CCR2_PL_1                             (0x2UL<<DMA_CCR2_PL_Pos)                          /*!< 0x00020000 */
#define DMA_CCR2_PL_2                             (0x4UL<<DMA_CCR2_PL_Pos)                          /*!< 0x00040000 */
#define DMA_CCR2_MEM2MEM_Pos                      (19U)
#define DMA_CCR2_MEM2MEM_Msk                      (0x1UL<<DMA_CCR2_MEM2MEM_Pos)                     /*!< 0x00080000 */
#define DMA_CCR2_MEM2MEM                          DMA_CCR2_MEM2MEM_Msk                              
#define DMA_CCR2_PNORLD_Pos                       (20U)
#define DMA_CCR2_PNORLD_Msk                       (0x1UL<<DMA_CCR2_PNORLD_Pos)                      /*!< 0x00100000 */
#define DMA_CCR2_PNORLD                           DMA_CCR2_PNORLD_Msk                               
#define DMA_CCR2_MNORLD_Pos                       (21U)
#define DMA_CCR2_MNORLD_Msk                       (0x1UL<<DMA_CCR2_MNORLD_Pos)                      /*!< 0x00200000 */
#define DMA_CCR2_MNORLD                           DMA_CCR2_MNORLD_Msk                               
#define DMA_CCR2_BTCSUSP_Pos                      (22U)
#define DMA_CCR2_BTCSUSP_Msk                      (0x1UL<<DMA_CCR2_BTCSUSP_Pos)                     /*!< 0x00400000 */
#define DMA_CCR2_BTCSUSP                          DMA_CCR2_BTCSUSP_Msk                              
#define DMA_CCR2_M2MARB_Pos                       (23U)
#define DMA_CCR2_M2MARB_Msk                       (0x1UL<<DMA_CCR2_M2MARB_Pos)                      /*!< 0x00800000 */
#define DMA_CCR2_M2MARB                           DMA_CCR2_M2MARB_Msk                               

/********************************* Bit definition for DMA_CNDTR2 register *******************************************/
#define DMA_CNDTR2_NDT_Pos                        (0U)
#define DMA_CNDTR2_NDT_Msk                        (0xFFFFUL<<DMA_CNDTR2_NDT_Pos)                    /*!< 0x0000FFFF */
#define DMA_CNDTR2_NDT                            DMA_CNDTR2_NDT_Msk

/********************************* Bit definition for DMA_CPAR2 register ********************************************/
#define DMA_CPAR2_PA_Pos                          (0U)
#define DMA_CPAR2_PA_Msk                          (0xFFFFFFFFUL<<DMA_CPAR2_PA_Pos)                  /*!< 0xFFFFFFFF */
#define DMA_CPAR2_PA                              DMA_CPAR2_PA_Msk

/********************************* Bit definition for DMA_CMAR2 register ********************************************/
#define DMA_CMAR2_MA_Pos                          (0U)
#define DMA_CMAR2_MA_Msk                          (0xFFFFFFFFUL<<DMA_CMAR2_MA_Pos)                  /*!< 0xFFFFFFFF */
#define DMA_CMAR2_MA                              DMA_CMAR2_MA_Msk

/********************************* Bit definition for DMA_CCCFGR2 register ******************************************/
#define DMA_CCCFGR2_NBT_Pos                       (0U)
#define DMA_CCCFGR2_NBT_Msk                       (0xFFUL<<DMA_CCCFGR2_NBT_Pos)                     /*!< 0x000000FF */
#define DMA_CCCFGR2_NBT                           DMA_CCCFGR2_NBT_Msk
#define DMA_CCCFGR2_NDTL_Pos                      (16U)
#define DMA_CCCFGR2_NDTL_Msk                      (0xFFFFUL<<DMA_CCCFGR2_NDTL_Pos)                  /*!< 0xFFFF0000 */
#define DMA_CCCFGR2_NDTL                          DMA_CCCFGR2_NDTL_Msk

/********************************* Bit definition for DMA_CCR3 register *********************************************/
#define DMA_CCR3_EN_Pos                           (0U)
#define DMA_CCR3_EN_Msk                           (0x1UL<<DMA_CCR3_EN_Pos)                          /*!< 0x00000001 */
#define DMA_CCR3_EN                               DMA_CCR3_EN_Msk                                   
#define DMA_CCR3_TCIE_Pos                         (1U)
#define DMA_CCR3_TCIE_Msk                         (0x1UL<<DMA_CCR3_TCIE_Pos)                        /*!< 0x00000002 */
#define DMA_CCR3_TCIE                             DMA_CCR3_TCIE_Msk                                 
#define DMA_CCR3_BTCIE_Pos                        (2U)
#define DMA_CCR3_BTCIE_Msk                        (0x1UL<<DMA_CCR3_BTCIE_Pos)                       /*!< 0x00000004 */
#define DMA_CCR3_BTCIE                            DMA_CCR3_BTCIE_Msk                                
#define DMA_CCR3_HBTIE_Pos                        (3U)
#define DMA_CCR3_HBTIE_Msk                        (0x1UL<<DMA_CCR3_HBTIE_Pos)                       /*!< 0x00000008 */
#define DMA_CCR3_HBTIE                            DMA_CCR3_HBTIE_Msk                                
#define DMA_CCR3_TEIE_Pos                         (4U)
#define DMA_CCR3_TEIE_Msk                         (0x1UL<<DMA_CCR3_TEIE_Pos)                        /*!< 0x00000010 */
#define DMA_CCR3_TEIE                             DMA_CCR3_TEIE_Msk                                 
#define DMA_CCR3_DIR_Pos                          (5U)
#define DMA_CCR3_DIR_Msk                          (0x1UL<<DMA_CCR3_DIR_Pos)                         /*!< 0x00000020 */
#define DMA_CCR3_DIR                              DMA_CCR3_DIR_Msk                                  
#define DMA_CCR3_CIRC_Pos                         (6U)
#define DMA_CCR3_CIRC_Msk                         (0x1UL<<DMA_CCR3_CIRC_Pos)                        /*!< 0x00000040 */
#define DMA_CCR3_CIRC                             DMA_CCR3_CIRC_Msk                                 
#define DMA_CCR3_TRANST_Pos                       (7U)
#define DMA_CCR3_TRANST_Msk                       (0x1UL<<DMA_CCR3_TRANST_Pos)                      /*!< 0x00000080 */
#define DMA_CCR3_TRANST                           DMA_CCR3_TRANST_Msk                               
#define DMA_CCR3_PINC_Pos                         (8U)
#define DMA_CCR3_PINC_Msk                         (0x3UL<<DMA_CCR3_PINC_Pos)                        /*!< 0x00000300 */
#define DMA_CCR3_PINC                             DMA_CCR3_PINC_Msk
#define DMA_CCR3_PINC_0                           (0x1UL<<DMA_CCR3_PINC_Pos)                        /*!< 0x00000100 */
#define DMA_CCR3_PINC_1                           (0x2UL<<DMA_CCR3_PINC_Pos)                        /*!< 0x00000200 */
#define DMA_CCR3_MINC_Pos                         (10U)
#define DMA_CCR3_MINC_Msk                         (0x3UL<<DMA_CCR3_MINC_Pos)                        /*!< 0x00000C00 */
#define DMA_CCR3_MINC                             DMA_CCR3_MINC_Msk
#define DMA_CCR3_MINC_0                           (0x1UL<<DMA_CCR3_MINC_Pos)                        /*!< 0x00000400 */
#define DMA_CCR3_MINC_1                           (0x2UL<<DMA_CCR3_MINC_Pos)                        /*!< 0x00000800 */
#define DMA_CCR3_PSIZE_Pos                        (12U)
#define DMA_CCR3_PSIZE_Msk                        (0x3UL<<DMA_CCR3_PSIZE_Pos)                       /*!< 0x00003000 */
#define DMA_CCR3_PSIZE                            DMA_CCR3_PSIZE_Msk
#define DMA_CCR3_PSIZE_0                          (0x1UL<<DMA_CCR3_PSIZE_Pos)                       /*!< 0x00001000 */
#define DMA_CCR3_PSIZE_1                          (0x2UL<<DMA_CCR3_PSIZE_Pos)                       /*!< 0x00002000 */
#define DMA_CCR3_MSIZE_Pos                        (14U)
#define DMA_CCR3_MSIZE_Msk                        (0x3UL<<DMA_CCR3_MSIZE_Pos)                       /*!< 0x0000C000 */
#define DMA_CCR3_MSIZE                            DMA_CCR3_MSIZE_Msk
#define DMA_CCR3_MSIZE_0                          (0x1UL<<DMA_CCR3_MSIZE_Pos)                       /*!< 0x00004000 */
#define DMA_CCR3_MSIZE_1                          (0x2UL<<DMA_CCR3_MSIZE_Pos)                       /*!< 0x00008000 */
#define DMA_CCR3_PL_Pos                           (16U)
#define DMA_CCR3_PL_Msk                           (0x7UL<<DMA_CCR3_PL_Pos)                          /*!< 0x00070000 */
#define DMA_CCR3_PL                               DMA_CCR3_PL_Msk
#define DMA_CCR3_PL_0                             (0x1UL<<DMA_CCR3_PL_Pos)                          /*!< 0x00010000 */
#define DMA_CCR3_PL_1                             (0x2UL<<DMA_CCR3_PL_Pos)                          /*!< 0x00020000 */
#define DMA_CCR3_PL_2                             (0x4UL<<DMA_CCR3_PL_Pos)                          /*!< 0x00040000 */
#define DMA_CCR3_MEM2MEM_Pos                      (19U)
#define DMA_CCR3_MEM2MEM_Msk                      (0x1UL<<DMA_CCR3_MEM2MEM_Pos)                     /*!< 0x00080000 */
#define DMA_CCR3_MEM2MEM                          DMA_CCR3_MEM2MEM_Msk                              
#define DMA_CCR3_PNORLD_Pos                       (20U)
#define DMA_CCR3_PNORLD_Msk                       (0x1UL<<DMA_CCR3_PNORLD_Pos)                      /*!< 0x00100000 */
#define DMA_CCR3_PNORLD                           DMA_CCR3_PNORLD_Msk                               
#define DMA_CCR3_MNORLD_Pos                       (21U)
#define DMA_CCR3_MNORLD_Msk                       (0x1UL<<DMA_CCR3_MNORLD_Pos)                      /*!< 0x00200000 */
#define DMA_CCR3_MNORLD                           DMA_CCR3_MNORLD_Msk                               
#define DMA_CCR3_BTCSUSP_Pos                      (22U)
#define DMA_CCR3_BTCSUSP_Msk                      (0x1UL<<DMA_CCR3_BTCSUSP_Pos)                     /*!< 0x00400000 */
#define DMA_CCR3_BTCSUSP                          DMA_CCR3_BTCSUSP_Msk                              
#define DMA_CCR3_M2MARB_Pos                       (23U)
#define DMA_CCR3_M2MARB_Msk                       (0x1UL<<DMA_CCR3_M2MARB_Pos)                      /*!< 0x00800000 */
#define DMA_CCR3_M2MARB                           DMA_CCR3_M2MARB_Msk                               

/********************************* Bit definition for DMA_CNDTR3 register *******************************************/
#define DMA_CNDTR3_NDT_Pos                        (0U)
#define DMA_CNDTR3_NDT_Msk                        (0xFFFFUL<<DMA_CNDTR3_NDT_Pos)                    /*!< 0x0000FFFF */
#define DMA_CNDTR3_NDT                            DMA_CNDTR3_NDT_Msk

/********************************* Bit definition for DMA_CPAR3 register ********************************************/
#define DMA_CPAR3_PA_Pos                          (0U)
#define DMA_CPAR3_PA_Msk                          (0xFFFFFFFFUL<<DMA_CPAR3_PA_Pos)                  /*!< 0xFFFFFFFF */
#define DMA_CPAR3_PA                              DMA_CPAR3_PA_Msk

/********************************* Bit definition for DMA_CMAR3 register ********************************************/
#define DMA_CMAR3_MA_Pos                          (0U)
#define DMA_CMAR3_MA_Msk                          (0xFFFFFFFFUL<<DMA_CMAR3_MA_Pos)                  /*!< 0xFFFFFFFF */
#define DMA_CMAR3_MA                              DMA_CMAR3_MA_Msk

/********************************* Bit definition for DMA_CCCFGR3 register ******************************************/
#define DMA_CCCFGR3_NBT_Pos                       (0U)
#define DMA_CCCFGR3_NBT_Msk                       (0xFFUL<<DMA_CCCFGR3_NBT_Pos)                     /*!< 0x000000FF */
#define DMA_CCCFGR3_NBT                           DMA_CCCFGR3_NBT_Msk
#define DMA_CCCFGR3_NDTL_Pos                      (16U)
#define DMA_CCCFGR3_NDTL_Msk                      (0xFFFFUL<<DMA_CCCFGR3_NDTL_Pos)                  /*!< 0xFFFF0000 */
#define DMA_CCCFGR3_NDTL                          DMA_CCCFGR3_NDTL_Msk

/********************************* Bit definition for DMA_CCR4 register *********************************************/
#define DMA_CCR4_EN_Pos                           (0U)
#define DMA_CCR4_EN_Msk                           (0x1UL<<DMA_CCR4_EN_Pos)                          /*!< 0x00000001 */
#define DMA_CCR4_EN                               DMA_CCR4_EN_Msk                                   
#define DMA_CCR4_TCIE_Pos                         (1U)
#define DMA_CCR4_TCIE_Msk                         (0x1UL<<DMA_CCR4_TCIE_Pos)                        /*!< 0x00000002 */
#define DMA_CCR4_TCIE                             DMA_CCR4_TCIE_Msk                                 
#define DMA_CCR4_BTCIE_Pos                        (2U)
#define DMA_CCR4_BTCIE_Msk                        (0x1UL<<DMA_CCR4_BTCIE_Pos)                       /*!< 0x00000004 */
#define DMA_CCR4_BTCIE                            DMA_CCR4_BTCIE_Msk                                
#define DMA_CCR4_HBTIE_Pos                        (3U)
#define DMA_CCR4_HBTIE_Msk                        (0x1UL<<DMA_CCR4_HBTIE_Pos)                       /*!< 0x00000008 */
#define DMA_CCR4_HBTIE                            DMA_CCR4_HBTIE_Msk                                
#define DMA_CCR4_TEIE_Pos                         (4U)
#define DMA_CCR4_TEIE_Msk                         (0x1UL<<DMA_CCR4_TEIE_Pos)                        /*!< 0x00000010 */
#define DMA_CCR4_TEIE                             DMA_CCR4_TEIE_Msk                                 
#define DMA_CCR4_DIR_Pos                          (5U)
#define DMA_CCR4_DIR_Msk                          (0x1UL<<DMA_CCR4_DIR_Pos)                         /*!< 0x00000020 */
#define DMA_CCR4_DIR                              DMA_CCR4_DIR_Msk                                  
#define DMA_CCR4_CIRC_Pos                         (6U)
#define DMA_CCR4_CIRC_Msk                         (0x1UL<<DMA_CCR4_CIRC_Pos)                        /*!< 0x00000040 */
#define DMA_CCR4_CIRC                             DMA_CCR4_CIRC_Msk                                 
#define DMA_CCR4_TRANST_Pos                       (7U)
#define DMA_CCR4_TRANST_Msk                       (0x1UL<<DMA_CCR4_TRANST_Pos)                      /*!< 0x00000080 */
#define DMA_CCR4_TRANST                           DMA_CCR4_TRANST_Msk                               
#define DMA_CCR4_PINC_Pos                         (8U)
#define DMA_CCR4_PINC_Msk                         (0x3UL<<DMA_CCR4_PINC_Pos)                        /*!< 0x00000300 */
#define DMA_CCR4_PINC                             DMA_CCR4_PINC_Msk
#define DMA_CCR4_PINC_0                           (0x1UL<<DMA_CCR4_PINC_Pos)                        /*!< 0x00000100 */
#define DMA_CCR4_PINC_1                           (0x2UL<<DMA_CCR4_PINC_Pos)                        /*!< 0x00000200 */
#define DMA_CCR4_MINC_Pos                         (10U)
#define DMA_CCR4_MINC_Msk                         (0x3UL<<DMA_CCR4_MINC_Pos)                        /*!< 0x00000C00 */
#define DMA_CCR4_MINC                             DMA_CCR4_MINC_Msk
#define DMA_CCR4_MINC_0                           (0x1UL<<DMA_CCR4_MINC_Pos)                        /*!< 0x00000400 */
#define DMA_CCR4_MINC_1                           (0x2UL<<DMA_CCR4_MINC_Pos)                        /*!< 0x00000800 */
#define DMA_CCR4_PSIZE_Pos                        (12U)
#define DMA_CCR4_PSIZE_Msk                        (0x3UL<<DMA_CCR4_PSIZE_Pos)                       /*!< 0x00003000 */
#define DMA_CCR4_PSIZE                            DMA_CCR4_PSIZE_Msk
#define DMA_CCR4_PSIZE_0                          (0x1UL<<DMA_CCR4_PSIZE_Pos)                       /*!< 0x00001000 */
#define DMA_CCR4_PSIZE_1                          (0x2UL<<DMA_CCR4_PSIZE_Pos)                       /*!< 0x00002000 */
#define DMA_CCR4_MSIZE_Pos                        (14U)
#define DMA_CCR4_MSIZE_Msk                        (0x3UL<<DMA_CCR4_MSIZE_Pos)                       /*!< 0x0000C000 */
#define DMA_CCR4_MSIZE                            DMA_CCR4_MSIZE_Msk
#define DMA_CCR4_MSIZE_0                          (0x1UL<<DMA_CCR4_MSIZE_Pos)                       /*!< 0x00004000 */
#define DMA_CCR4_MSIZE_1                          (0x2UL<<DMA_CCR4_MSIZE_Pos)                       /*!< 0x00008000 */
#define DMA_CCR4_PL_Pos                           (16U)
#define DMA_CCR4_PL_Msk                           (0x7UL<<DMA_CCR4_PL_Pos)                          /*!< 0x00070000 */
#define DMA_CCR4_PL                               DMA_CCR4_PL_Msk
#define DMA_CCR4_PL_0                             (0x1UL<<DMA_CCR4_PL_Pos)                          /*!< 0x00010000 */
#define DMA_CCR4_PL_1                             (0x2UL<<DMA_CCR4_PL_Pos)                          /*!< 0x00020000 */
#define DMA_CCR4_PL_2                             (0x4UL<<DMA_CCR4_PL_Pos)                          /*!< 0x00040000 */
#define DMA_CCR4_MEM2MEM_Pos                      (19U)
#define DMA_CCR4_MEM2MEM_Msk                      (0x1UL<<DMA_CCR4_MEM2MEM_Pos)                     /*!< 0x00080000 */
#define DMA_CCR4_MEM2MEM                          DMA_CCR4_MEM2MEM_Msk                              
#define DMA_CCR4_PNORLD_Pos                       (20U)
#define DMA_CCR4_PNORLD_Msk                       (0x1UL<<DMA_CCR4_PNORLD_Pos)                      /*!< 0x00100000 */
#define DMA_CCR4_PNORLD                           DMA_CCR4_PNORLD_Msk                               
#define DMA_CCR4_MNORLD_Pos                       (21U)
#define DMA_CCR4_MNORLD_Msk                       (0x1UL<<DMA_CCR4_MNORLD_Pos)                      /*!< 0x00200000 */
#define DMA_CCR4_MNORLD                           DMA_CCR4_MNORLD_Msk                               
#define DMA_CCR4_BTCSUSP_Pos                      (22U)
#define DMA_CCR4_BTCSUSP_Msk                      (0x1UL<<DMA_CCR4_BTCSUSP_Pos)                     /*!< 0x00400000 */
#define DMA_CCR4_BTCSUSP                          DMA_CCR4_BTCSUSP_Msk                              
#define DMA_CCR4_M2MARB_Pos                       (23U)
#define DMA_CCR4_M2MARB_Msk                       (0x1UL<<DMA_CCR4_M2MARB_Pos)                      /*!< 0x00800000 */
#define DMA_CCR4_M2MARB                           DMA_CCR4_M2MARB_Msk                               

/********************************* Bit definition for DMA_CNDTR4 register *******************************************/
#define DMA_CNDTR4_NDT_Pos                        (0U)
#define DMA_CNDTR4_NDT_Msk                        (0xFFFFUL<<DMA_CNDTR4_NDT_Pos)                    /*!< 0x0000FFFF */
#define DMA_CNDTR4_NDT                            DMA_CNDTR4_NDT_Msk

/********************************* Bit definition for DMA_CPAR4 register ********************************************/
#define DMA_CPAR4_PA_Pos                          (0U)
#define DMA_CPAR4_PA_Msk                          (0xFFFFFFFFUL<<DMA_CPAR4_PA_Pos)                  /*!< 0xFFFFFFFF */
#define DMA_CPAR4_PA                              DMA_CPAR4_PA_Msk

/********************************* Bit definition for DMA_CMAR4 register ********************************************/
#define DMA_CMAR4_MA_Pos                          (0U)
#define DMA_CMAR4_MA_Msk                          (0xFFFFFFFFUL<<DMA_CMAR4_MA_Pos)                  /*!< 0xFFFFFFFF */
#define DMA_CMAR4_MA                              DMA_CMAR4_MA_Msk

/********************************* Bit definition for DMA_CCCFGR4 register ******************************************/
#define DMA_CCCFGR4_NBT_Pos                       (0U)
#define DMA_CCCFGR4_NBT_Msk                       (0xFFUL<<DMA_CCCFGR4_NBT_Pos)                     /*!< 0x000000FF */
#define DMA_CCCFGR4_NBT                           DMA_CCCFGR4_NBT_Msk
#define DMA_CCCFGR4_NDTL_Pos                      (16U)
#define DMA_CCCFGR4_NDTL_Msk                      (0xFFFFUL<<DMA_CCCFGR4_NDTL_Pos)                  /*!< 0xFFFF0000 */
#define DMA_CCCFGR4_NDTL                          DMA_CCCFGR4_NDTL_Msk

/********************************* Bit definition for DMA_CCR5 register *********************************************/
#define DMA_CCR5_EN_Pos                           (0U)
#define DMA_CCR5_EN_Msk                           (0x1UL<<DMA_CCR5_EN_Pos)                          /*!< 0x00000001 */
#define DMA_CCR5_EN                               DMA_CCR5_EN_Msk                                   
#define DMA_CCR5_TCIE_Pos                         (1U)
#define DMA_CCR5_TCIE_Msk                         (0x1UL<<DMA_CCR5_TCIE_Pos)                        /*!< 0x00000002 */
#define DMA_CCR5_TCIE                             DMA_CCR5_TCIE_Msk                                 
#define DMA_CCR5_BTCIE_Pos                        (2U)
#define DMA_CCR5_BTCIE_Msk                        (0x1UL<<DMA_CCR5_BTCIE_Pos)                       /*!< 0x00000004 */
#define DMA_CCR5_BTCIE                            DMA_CCR5_BTCIE_Msk                                
#define DMA_CCR5_HBTIE_Pos                        (3U)
#define DMA_CCR5_HBTIE_Msk                        (0x1UL<<DMA_CCR5_HBTIE_Pos)                       /*!< 0x00000008 */
#define DMA_CCR5_HBTIE                            DMA_CCR5_HBTIE_Msk                                
#define DMA_CCR5_TEIE_Pos                         (4U)
#define DMA_CCR5_TEIE_Msk                         (0x1UL<<DMA_CCR5_TEIE_Pos)                        /*!< 0x00000010 */
#define DMA_CCR5_TEIE                             DMA_CCR5_TEIE_Msk                                 
#define DMA_CCR5_DIR_Pos                          (5U)
#define DMA_CCR5_DIR_Msk                          (0x1UL<<DMA_CCR5_DIR_Pos)                         /*!< 0x00000020 */
#define DMA_CCR5_DIR                              DMA_CCR5_DIR_Msk                                  
#define DMA_CCR5_CIRC_Pos                         (6U)
#define DMA_CCR5_CIRC_Msk                         (0x1UL<<DMA_CCR5_CIRC_Pos)                        /*!< 0x00000040 */
#define DMA_CCR5_CIRC                             DMA_CCR5_CIRC_Msk                                 
#define DMA_CCR5_TRANST_Pos                       (7U)
#define DMA_CCR5_TRANST_Msk                       (0x1UL<<DMA_CCR5_TRANST_Pos)                      /*!< 0x00000080 */
#define DMA_CCR5_TRANST                           DMA_CCR5_TRANST_Msk                               
#define DMA_CCR5_PINC_Pos                         (8U)
#define DMA_CCR5_PINC_Msk                         (0x3UL<<DMA_CCR5_PINC_Pos)                        /*!< 0x00000300 */
#define DMA_CCR5_PINC                             DMA_CCR5_PINC_Msk
#define DMA_CCR5_PINC_0                           (0x1UL<<DMA_CCR5_PINC_Pos)                        /*!< 0x00000100 */
#define DMA_CCR5_PINC_1                           (0x2UL<<DMA_CCR5_PINC_Pos)                        /*!< 0x00000200 */
#define DMA_CCR5_MINC_Pos                         (10U)
#define DMA_CCR5_MINC_Msk                         (0x3UL<<DMA_CCR5_MINC_Pos)                        /*!< 0x00000C00 */
#define DMA_CCR5_MINC                             DMA_CCR5_MINC_Msk
#define DMA_CCR5_MINC_0                           (0x1UL<<DMA_CCR5_MINC_Pos)                        /*!< 0x00000400 */
#define DMA_CCR5_MINC_1                           (0x2UL<<DMA_CCR5_MINC_Pos)                        /*!< 0x00000800 */
#define DMA_CCR5_PSIZE_Pos                        (12U)
#define DMA_CCR5_PSIZE_Msk                        (0x3UL<<DMA_CCR5_PSIZE_Pos)                       /*!< 0x00003000 */
#define DMA_CCR5_PSIZE                            DMA_CCR5_PSIZE_Msk
#define DMA_CCR5_PSIZE_0                          (0x1UL<<DMA_CCR5_PSIZE_Pos)                       /*!< 0x00001000 */
#define DMA_CCR5_PSIZE_1                          (0x2UL<<DMA_CCR5_PSIZE_Pos)                       /*!< 0x00002000 */
#define DMA_CCR5_MSIZE_Pos                        (14U)
#define DMA_CCR5_MSIZE_Msk                        (0x3UL<<DMA_CCR5_MSIZE_Pos)                       /*!< 0x0000C000 */
#define DMA_CCR5_MSIZE                            DMA_CCR5_MSIZE_Msk
#define DMA_CCR5_MSIZE_0                          (0x1UL<<DMA_CCR5_MSIZE_Pos)                       /*!< 0x00004000 */
#define DMA_CCR5_MSIZE_1                          (0x2UL<<DMA_CCR5_MSIZE_Pos)                       /*!< 0x00008000 */
#define DMA_CCR5_PL_Pos                           (16U)
#define DMA_CCR5_PL_Msk                           (0x7UL<<DMA_CCR5_PL_Pos)                          /*!< 0x00070000 */
#define DMA_CCR5_PL                               DMA_CCR5_PL_Msk
#define DMA_CCR5_PL_0                             (0x1UL<<DMA_CCR5_PL_Pos)                          /*!< 0x00010000 */
#define DMA_CCR5_PL_1                             (0x2UL<<DMA_CCR5_PL_Pos)                          /*!< 0x00020000 */
#define DMA_CCR5_PL_2                             (0x4UL<<DMA_CCR5_PL_Pos)                          /*!< 0x00040000 */
#define DMA_CCR5_MEM2MEM_Pos                      (19U)
#define DMA_CCR5_MEM2MEM_Msk                      (0x1UL<<DMA_CCR5_MEM2MEM_Pos)                     /*!< 0x00080000 */
#define DMA_CCR5_MEM2MEM                          DMA_CCR5_MEM2MEM_Msk                              
#define DMA_CCR5_PNORLD_Pos                       (20U)
#define DMA_CCR5_PNORLD_Msk                       (0x1UL<<DMA_CCR5_PNORLD_Pos)                      /*!< 0x00100000 */
#define DMA_CCR5_PNORLD                           DMA_CCR5_PNORLD_Msk                               
#define DMA_CCR5_MNORLD_Pos                       (21U)
#define DMA_CCR5_MNORLD_Msk                       (0x1UL<<DMA_CCR5_MNORLD_Pos)                      /*!< 0x00200000 */
#define DMA_CCR5_MNORLD                           DMA_CCR5_MNORLD_Msk                               
#define DMA_CCR5_BTCSUSP_Pos                      (22U)
#define DMA_CCR5_BTCSUSP_Msk                      (0x1UL<<DMA_CCR5_BTCSUSP_Pos)                     /*!< 0x00400000 */
#define DMA_CCR5_BTCSUSP                          DMA_CCR5_BTCSUSP_Msk                              
#define DMA_CCR5_M2MARB_Pos                       (23U)
#define DMA_CCR5_M2MARB_Msk                       (0x1UL<<DMA_CCR5_M2MARB_Pos)                      /*!< 0x00800000 */
#define DMA_CCR5_M2MARB                           DMA_CCR5_M2MARB_Msk                               

/********************************* Bit definition for DMA_CNDTR5 register *******************************************/
#define DMA_CNDTR5_NDT_Pos                        (0U)
#define DMA_CNDTR5_NDT_Msk                        (0xFFFFUL<<DMA_CNDTR5_NDT_Pos)                    /*!< 0x0000FFFF */
#define DMA_CNDTR5_NDT                            DMA_CNDTR5_NDT_Msk

/********************************* Bit definition for DMA_CPAR5 register ********************************************/
#define DMA_CPAR5_PA_Pos                          (0U)
#define DMA_CPAR5_PA_Msk                          (0xFFFFFFFFUL<<DMA_CPAR5_PA_Pos)                  /*!< 0xFFFFFFFF */
#define DMA_CPAR5_PA                              DMA_CPAR5_PA_Msk

/********************************* Bit definition for DMA_CMAR5 register ********************************************/
#define DMA_CMAR5_MA_Pos                          (0U)
#define DMA_CMAR5_MA_Msk                          (0xFFFFFFFFUL<<DMA_CMAR5_MA_Pos)                  /*!< 0xFFFFFFFF */
#define DMA_CMAR5_MA                              DMA_CMAR5_MA_Msk

/********************************* Bit definition for DMA_CCCFGR5 register ******************************************/
#define DMA_CCCFGR5_NBT_Pos                       (0U)
#define DMA_CCCFGR5_NBT_Msk                       (0xFFUL<<DMA_CCCFGR5_NBT_Pos)                     /*!< 0x000000FF */
#define DMA_CCCFGR5_NBT                           DMA_CCCFGR5_NBT_Msk
#define DMA_CCCFGR5_NDTL_Pos                      (16U)
#define DMA_CCCFGR5_NDTL_Msk                      (0xFFFFUL<<DMA_CCCFGR5_NDTL_Pos)                  /*!< 0xFFFF0000 */
#define DMA_CCCFGR5_NDTL                          DMA_CCCFGR5_NDTL_Msk

/********************************************************************************************************************/
/********************************* EXTI *****************************************************************************/
/********************************************************************************************************************/

/********************************* Bit definition for EXTI_IMR register *********************************************/
#define EXTI_IMR_IMR0_Pos                         (0U)
#define EXTI_IMR_IMR0_Msk                         (0x1UL<<EXTI_IMR_IMR0_Pos)                        /*!< 0x00000001 */
#define EXTI_IMR_IMR0                             EXTI_IMR_IMR0_Msk                                 
#define EXTI_IMR_IMR1_Pos                         (1U)
#define EXTI_IMR_IMR1_Msk                         (0x1UL<<EXTI_IMR_IMR1_Pos)                        /*!< 0x00000002 */
#define EXTI_IMR_IMR1                             EXTI_IMR_IMR1_Msk                                 
#define EXTI_IMR_IMR2_Pos                         (2U)
#define EXTI_IMR_IMR2_Msk                         (0x1UL<<EXTI_IMR_IMR2_Pos)                        /*!< 0x00000004 */
#define EXTI_IMR_IMR2                             EXTI_IMR_IMR2_Msk                                 
#define EXTI_IMR_IMR3_Pos                         (3U)
#define EXTI_IMR_IMR3_Msk                         (0x1UL<<EXTI_IMR_IMR3_Pos)                        /*!< 0x00000008 */
#define EXTI_IMR_IMR3                             EXTI_IMR_IMR3_Msk                                 
#define EXTI_IMR_IMR4_Pos                         (4U)
#define EXTI_IMR_IMR4_Msk                         (0x1UL<<EXTI_IMR_IMR4_Pos)                        /*!< 0x00000010 */
#define EXTI_IMR_IMR4                             EXTI_IMR_IMR4_Msk                                 
#define EXTI_IMR_IMR5_Pos                         (5U)
#define EXTI_IMR_IMR5_Msk                         (0x1UL<<EXTI_IMR_IMR5_Pos)                        /*!< 0x00000020 */
#define EXTI_IMR_IMR5                             EXTI_IMR_IMR5_Msk                                 
#define EXTI_IMR_IMR6_Pos                         (6U)
#define EXTI_IMR_IMR6_Msk                         (0x1UL<<EXTI_IMR_IMR6_Pos)                        /*!< 0x00000040 */
#define EXTI_IMR_IMR6                             EXTI_IMR_IMR6_Msk                                 
#define EXTI_IMR_IMR7_Pos                         (7U)
#define EXTI_IMR_IMR7_Msk                         (0x1UL<<EXTI_IMR_IMR7_Pos)                        /*!< 0x00000080 */
#define EXTI_IMR_IMR7                             EXTI_IMR_IMR7_Msk                                 
#define EXTI_IMR_IMR8_Pos                         (8U)
#define EXTI_IMR_IMR8_Msk                         (0x1UL<<EXTI_IMR_IMR8_Pos)                        /*!< 0x00000100 */
#define EXTI_IMR_IMR8                             EXTI_IMR_IMR8_Msk                                 
#define EXTI_IMR_IMR9_Pos                         (9U)
#define EXTI_IMR_IMR9_Msk                         (0x1UL<<EXTI_IMR_IMR9_Pos)                        /*!< 0x00000200 */
#define EXTI_IMR_IMR9                             EXTI_IMR_IMR9_Msk                                 
#define EXTI_IMR_IMR10_Pos                        (10U)
#define EXTI_IMR_IMR10_Msk                        (0x1UL<<EXTI_IMR_IMR10_Pos)                       /*!< 0x00000400 */
#define EXTI_IMR_IMR10                            EXTI_IMR_IMR10_Msk                                
#define EXTI_IMR_IMR11_Pos                        (11U)
#define EXTI_IMR_IMR11_Msk                        (0x1UL<<EXTI_IMR_IMR11_Pos)                       /*!< 0x00000800 */
#define EXTI_IMR_IMR11                            EXTI_IMR_IMR11_Msk                                
#define EXTI_IMR_IMR12_Pos                        (12U)
#define EXTI_IMR_IMR12_Msk                        (0x1UL<<EXTI_IMR_IMR12_Pos)                       /*!< 0x00001000 */
#define EXTI_IMR_IMR12                            EXTI_IMR_IMR12_Msk                                
#define EXTI_IMR_IMR13_Pos                        (13U)
#define EXTI_IMR_IMR13_Msk                        (0x1UL<<EXTI_IMR_IMR13_Pos)                       /*!< 0x00002000 */
#define EXTI_IMR_IMR13                            EXTI_IMR_IMR13_Msk                                
#define EXTI_IMR_IMR14_Pos                        (14U)
#define EXTI_IMR_IMR14_Msk                        (0x1UL<<EXTI_IMR_IMR14_Pos)                       /*!< 0x00004000 */
#define EXTI_IMR_IMR14                            EXTI_IMR_IMR14_Msk                                
#define EXTI_IMR_IMR15_Pos                        (15U)
#define EXTI_IMR_IMR15_Msk                        (0x1UL<<EXTI_IMR_IMR15_Pos)                       /*!< 0x00008000 */
#define EXTI_IMR_IMR15                            EXTI_IMR_IMR15_Msk                                
#define EXTI_IMR_IMR16_Pos                        (16U)
#define EXTI_IMR_IMR16_Msk                        (0x1UL<<EXTI_IMR_IMR16_Pos)                       /*!< 0x00010000 */
#define EXTI_IMR_IMR16                            EXTI_IMR_IMR16_Msk                                
#define EXTI_IMR_IMR17_Pos                        (17U)
#define EXTI_IMR_IMR17_Msk                        (0x1UL<<EXTI_IMR_IMR17_Pos)                       /*!< 0x00020000 */
#define EXTI_IMR_IMR17                            EXTI_IMR_IMR17_Msk                                
#define EXTI_IMR_IMR18_Pos                        (18U)
#define EXTI_IMR_IMR18_Msk                        (0x1UL<<EXTI_IMR_IMR18_Pos)                       /*!< 0x00040000 */
#define EXTI_IMR_IMR18                            EXTI_IMR_IMR18_Msk                                
#define EXTI_IMR_IMR19_Pos                        (19U)
#define EXTI_IMR_IMR19_Msk                        (0x1UL<<EXTI_IMR_IMR19_Pos)                       /*!< 0x00080000 */
#define EXTI_IMR_IMR19                            EXTI_IMR_IMR19_Msk                                
#define EXTI_IMR_IMR20_Pos                        (20U)
#define EXTI_IMR_IMR20_Msk                        (0x1UL<<EXTI_IMR_IMR20_Pos)                       /*!< 0x00100000 */
#define EXTI_IMR_IMR20                            EXTI_IMR_IMR20_Msk                                
#define EXTI_IMR_IMR21_Pos                        (21U)
#define EXTI_IMR_IMR21_Msk                        (0x1UL<<EXTI_IMR_IMR21_Pos)                       /*!< 0x00200000 */
#define EXTI_IMR_IMR21                            EXTI_IMR_IMR21_Msk                                
#define EXTI_IMR_IMR22_Pos                        (22U)
#define EXTI_IMR_IMR22_Msk                        (0x1UL<<EXTI_IMR_IMR22_Pos)                       /*!< 0x00400000 */
#define EXTI_IMR_IMR22                            EXTI_IMR_IMR22_Msk                                
#define EXTI_IMR_IMR23_Pos                        (23U)
#define EXTI_IMR_IMR23_Msk                        (0x1UL<<EXTI_IMR_IMR23_Pos)                       /*!< 0x00800000 */
#define EXTI_IMR_IMR23                            EXTI_IMR_IMR23_Msk                                
#define EXTI_IMR_IMR24_Pos                        (24U)
#define EXTI_IMR_IMR24_Msk                        (0x1UL<<EXTI_IMR_IMR24_Pos)                       /*!< 0x01000000 */
#define EXTI_IMR_IMR24                            EXTI_IMR_IMR24_Msk                                
#define EXTI_IMR_IMR25_Pos                        (25U)
#define EXTI_IMR_IMR25_Msk                        (0x1UL<<EXTI_IMR_IMR25_Pos)                       /*!< 0x02000000 */
#define EXTI_IMR_IMR25                            EXTI_IMR_IMR25_Msk                                

/********************************* Bit definition for EXTI_EMR register *********************************************/
#define EXTI_EMR_EMR0_Pos                         (0U)
#define EXTI_EMR_EMR0_Msk                         (0x1UL<<EXTI_EMR_EMR0_Pos)                        /*!< 0x00000001 */
#define EXTI_EMR_EMR0                             EXTI_EMR_EMR0_Msk                                 
#define EXTI_EMR_EMR1_Pos                         (1U)
#define EXTI_EMR_EMR1_Msk                         (0x1UL<<EXTI_EMR_EMR1_Pos)                        /*!< 0x00000002 */
#define EXTI_EMR_EMR1                             EXTI_EMR_EMR1_Msk                                 
#define EXTI_EMR_EMR2_Pos                         (2U)
#define EXTI_EMR_EMR2_Msk                         (0x1UL<<EXTI_EMR_EMR2_Pos)                        /*!< 0x00000004 */
#define EXTI_EMR_EMR2                             EXTI_EMR_EMR2_Msk                                 
#define EXTI_EMR_EMR3_Pos                         (3U)
#define EXTI_EMR_EMR3_Msk                         (0x1UL<<EXTI_EMR_EMR3_Pos)                        /*!< 0x00000008 */
#define EXTI_EMR_EMR3                             EXTI_EMR_EMR3_Msk                                 
#define EXTI_EMR_EMR4_Pos                         (4U)
#define EXTI_EMR_EMR4_Msk                         (0x1UL<<EXTI_EMR_EMR4_Pos)                        /*!< 0x00000010 */
#define EXTI_EMR_EMR4                             EXTI_EMR_EMR4_Msk                                 
#define EXTI_EMR_EMR5_Pos                         (5U)
#define EXTI_EMR_EMR5_Msk                         (0x1UL<<EXTI_EMR_EMR5_Pos)                        /*!< 0x00000020 */
#define EXTI_EMR_EMR5                             EXTI_EMR_EMR5_Msk                                 
#define EXTI_EMR_EMR6_Pos                         (6U)
#define EXTI_EMR_EMR6_Msk                         (0x1UL<<EXTI_EMR_EMR6_Pos)                        /*!< 0x00000040 */
#define EXTI_EMR_EMR6                             EXTI_EMR_EMR6_Msk                                 
#define EXTI_EMR_EMR7_Pos                         (7U)
#define EXTI_EMR_EMR7_Msk                         (0x1UL<<EXTI_EMR_EMR7_Pos)                        /*!< 0x00000080 */
#define EXTI_EMR_EMR7                             EXTI_EMR_EMR7_Msk                                 
#define EXTI_EMR_EMR8_Pos                         (8U)
#define EXTI_EMR_EMR8_Msk                         (0x1UL<<EXTI_EMR_EMR8_Pos)                        /*!< 0x00000100 */
#define EXTI_EMR_EMR8                             EXTI_EMR_EMR8_Msk                                 
#define EXTI_EMR_EMR9_Pos                         (9U)
#define EXTI_EMR_EMR9_Msk                         (0x1UL<<EXTI_EMR_EMR9_Pos)                        /*!< 0x00000200 */
#define EXTI_EMR_EMR9                             EXTI_EMR_EMR9_Msk                                 
#define EXTI_EMR_EMR10_Pos                        (10U)
#define EXTI_EMR_EMR10_Msk                        (0x1UL<<EXTI_EMR_EMR10_Pos)                       /*!< 0x00000400 */
#define EXTI_EMR_EMR10                            EXTI_EMR_EMR10_Msk                                
#define EXTI_EMR_EMR11_Pos                        (11U)
#define EXTI_EMR_EMR11_Msk                        (0x1UL<<EXTI_EMR_EMR11_Pos)                       /*!< 0x00000800 */
#define EXTI_EMR_EMR11                            EXTI_EMR_EMR11_Msk                                
#define EXTI_EMR_EMR12_Pos                        (12U)
#define EXTI_EMR_EMR12_Msk                        (0x1UL<<EXTI_EMR_EMR12_Pos)                       /*!< 0x00001000 */
#define EXTI_EMR_EMR12                            EXTI_EMR_EMR12_Msk                                
#define EXTI_EMR_EMR13_Pos                        (13U)
#define EXTI_EMR_EMR13_Msk                        (0x1UL<<EXTI_EMR_EMR13_Pos)                       /*!< 0x00002000 */
#define EXTI_EMR_EMR13                            EXTI_EMR_EMR13_Msk                                
#define EXTI_EMR_EMR14_Pos                        (14U)
#define EXTI_EMR_EMR14_Msk                        (0x1UL<<EXTI_EMR_EMR14_Pos)                       /*!< 0x00004000 */
#define EXTI_EMR_EMR14                            EXTI_EMR_EMR14_Msk                                
#define EXTI_EMR_EMR15_Pos                        (15U)
#define EXTI_EMR_EMR15_Msk                        (0x1UL<<EXTI_EMR_EMR15_Pos)                       /*!< 0x00008000 */
#define EXTI_EMR_EMR15                            EXTI_EMR_EMR15_Msk                                
#define EXTI_EMR_EMR16_Pos                        (16U)
#define EXTI_EMR_EMR16_Msk                        (0x1UL<<EXTI_EMR_EMR16_Pos)                       /*!< 0x00010000 */
#define EXTI_EMR_EMR16                            EXTI_EMR_EMR16_Msk                                
#define EXTI_EMR_EMR17_Pos                        (17U)
#define EXTI_EMR_EMR17_Msk                        (0x1UL<<EXTI_EMR_EMR17_Pos)                       /*!< 0x00020000 */
#define EXTI_EMR_EMR17                            EXTI_EMR_EMR17_Msk                                
#define EXTI_EMR_EMR18_Pos                        (18U)
#define EXTI_EMR_EMR18_Msk                        (0x1UL<<EXTI_EMR_EMR18_Pos)                       /*!< 0x00040000 */
#define EXTI_EMR_EMR18                            EXTI_EMR_EMR18_Msk                                
#define EXTI_EMR_EMR19_Pos                        (19U)
#define EXTI_EMR_EMR19_Msk                        (0x1UL<<EXTI_EMR_EMR19_Pos)                       /*!< 0x00080000 */
#define EXTI_EMR_EMR19                            EXTI_EMR_EMR19_Msk                                
#define EXTI_EMR_EMR20_Pos                        (20U)
#define EXTI_EMR_EMR20_Msk                        (0x1UL<<EXTI_EMR_EMR20_Pos)                       /*!< 0x00100000 */
#define EXTI_EMR_EMR20                            EXTI_EMR_EMR20_Msk                                
#define EXTI_EMR_EMR21_Pos                        (21U)
#define EXTI_EMR_EMR21_Msk                        (0x1UL<<EXTI_EMR_EMR21_Pos)                       /*!< 0x00200000 */
#define EXTI_EMR_EMR21                            EXTI_EMR_EMR21_Msk                                
#define EXTI_EMR_EMR22_Pos                        (22U)
#define EXTI_EMR_EMR22_Msk                        (0x1UL<<EXTI_EMR_EMR22_Pos)                       /*!< 0x00400000 */
#define EXTI_EMR_EMR22                            EXTI_EMR_EMR22_Msk                                
#define EXTI_EMR_EMR23_Pos                        (23U)
#define EXTI_EMR_EMR23_Msk                        (0x1UL<<EXTI_EMR_EMR23_Pos)                       /*!< 0x00800000 */
#define EXTI_EMR_EMR23                            EXTI_EMR_EMR23_Msk                                
#define EXTI_EMR_EMR24_Pos                        (24U)
#define EXTI_EMR_EMR24_Msk                        (0x1UL<<EXTI_EMR_EMR24_Pos)                       /*!< 0x01000000 */
#define EXTI_EMR_EMR24                            EXTI_EMR_EMR24_Msk                                
#define EXTI_EMR_EMR25_Pos                        (25U)
#define EXTI_EMR_EMR25_Msk                        (0x1UL<<EXTI_EMR_EMR25_Pos)                       /*!< 0x02000000 */
#define EXTI_EMR_EMR25                            EXTI_EMR_EMR25_Msk                                

/********************************* Bit definition for EXTI_RTSR register ********************************************/
#define EXTI_RTSR_RTSR0_Pos                       (0U)
#define EXTI_RTSR_RTSR0_Msk                       (0x1UL<<EXTI_RTSR_RTSR0_Pos)                      /*!< 0x00000001 */
#define EXTI_RTSR_RTSR0                           EXTI_RTSR_RTSR0_Msk                               
#define EXTI_RTSR_RTSR1_Pos                       (1U)
#define EXTI_RTSR_RTSR1_Msk                       (0x1UL<<EXTI_RTSR_RTSR1_Pos)                      /*!< 0x00000002 */
#define EXTI_RTSR_RTSR1                           EXTI_RTSR_RTSR1_Msk                               
#define EXTI_RTSR_RTSR2_Pos                       (2U)
#define EXTI_RTSR_RTSR2_Msk                       (0x1UL<<EXTI_RTSR_RTSR2_Pos)                      /*!< 0x00000004 */
#define EXTI_RTSR_RTSR2                           EXTI_RTSR_RTSR2_Msk                               
#define EXTI_RTSR_RTSR3_Pos                       (3U)
#define EXTI_RTSR_RTSR3_Msk                       (0x1UL<<EXTI_RTSR_RTSR3_Pos)                      /*!< 0x00000008 */
#define EXTI_RTSR_RTSR3                           EXTI_RTSR_RTSR3_Msk                               
#define EXTI_RTSR_RTSR4_Pos                       (4U)
#define EXTI_RTSR_RTSR4_Msk                       (0x1UL<<EXTI_RTSR_RTSR4_Pos)                      /*!< 0x00000010 */
#define EXTI_RTSR_RTSR4                           EXTI_RTSR_RTSR4_Msk                               
#define EXTI_RTSR_RTSR5_Pos                       (5U)
#define EXTI_RTSR_RTSR5_Msk                       (0x1UL<<EXTI_RTSR_RTSR5_Pos)                      /*!< 0x00000020 */
#define EXTI_RTSR_RTSR5                           EXTI_RTSR_RTSR5_Msk                               
#define EXTI_RTSR_RTSR6_Pos                       (6U)
#define EXTI_RTSR_RTSR6_Msk                       (0x1UL<<EXTI_RTSR_RTSR6_Pos)                      /*!< 0x00000040 */
#define EXTI_RTSR_RTSR6                           EXTI_RTSR_RTSR6_Msk                               
#define EXTI_RTSR_RTSR7_Pos                       (7U)
#define EXTI_RTSR_RTSR7_Msk                       (0x1UL<<EXTI_RTSR_RTSR7_Pos)                      /*!< 0x00000080 */
#define EXTI_RTSR_RTSR7                           EXTI_RTSR_RTSR7_Msk                               
#define EXTI_RTSR_RTSR8_Pos                       (8U)
#define EXTI_RTSR_RTSR8_Msk                       (0x1UL<<EXTI_RTSR_RTSR8_Pos)                      /*!< 0x00000100 */
#define EXTI_RTSR_RTSR8                           EXTI_RTSR_RTSR8_Msk                               
#define EXTI_RTSR_RTSR9_Pos                       (9U)
#define EXTI_RTSR_RTSR9_Msk                       (0x1UL<<EXTI_RTSR_RTSR9_Pos)                      /*!< 0x00000200 */
#define EXTI_RTSR_RTSR9                           EXTI_RTSR_RTSR9_Msk                               
#define EXTI_RTSR_RTSR10_Pos                      (10U)
#define EXTI_RTSR_RTSR10_Msk                      (0x1UL<<EXTI_RTSR_RTSR10_Pos)                     /*!< 0x00000400 */
#define EXTI_RTSR_RTSR10                          EXTI_RTSR_RTSR10_Msk                              
#define EXTI_RTSR_RTSR11_Pos                      (11U)
#define EXTI_RTSR_RTSR11_Msk                      (0x1UL<<EXTI_RTSR_RTSR11_Pos)                     /*!< 0x00000800 */
#define EXTI_RTSR_RTSR11                          EXTI_RTSR_RTSR11_Msk                              
#define EXTI_RTSR_RTSR12_Pos                      (12U)
#define EXTI_RTSR_RTSR12_Msk                      (0x1UL<<EXTI_RTSR_RTSR12_Pos)                     /*!< 0x00001000 */
#define EXTI_RTSR_RTSR12                          EXTI_RTSR_RTSR12_Msk                              
#define EXTI_RTSR_RTSR13_Pos                      (13U)
#define EXTI_RTSR_RTSR13_Msk                      (0x1UL<<EXTI_RTSR_RTSR13_Pos)                     /*!< 0x00002000 */
#define EXTI_RTSR_RTSR13                          EXTI_RTSR_RTSR13_Msk                              
#define EXTI_RTSR_RTSR14_Pos                      (14U)
#define EXTI_RTSR_RTSR14_Msk                      (0x1UL<<EXTI_RTSR_RTSR14_Pos)                     /*!< 0x00004000 */
#define EXTI_RTSR_RTSR14                          EXTI_RTSR_RTSR14_Msk                              
#define EXTI_RTSR_RTSR15_Pos                      (15U)
#define EXTI_RTSR_RTSR15_Msk                      (0x1UL<<EXTI_RTSR_RTSR15_Pos)                     /*!< 0x00008000 */
#define EXTI_RTSR_RTSR15                          EXTI_RTSR_RTSR15_Msk                              
#define EXTI_RTSR_RTSR16_Pos                      (16U)
#define EXTI_RTSR_RTSR16_Msk                      (0x1UL<<EXTI_RTSR_RTSR16_Pos)                     /*!< 0x00010000 */
#define EXTI_RTSR_RTSR16                          EXTI_RTSR_RTSR16_Msk                              
#define EXTI_RTSR_RTSR17_Pos                      (17U)
#define EXTI_RTSR_RTSR17_Msk                      (0x1UL<<EXTI_RTSR_RTSR17_Pos)                     /*!< 0x00020000 */
#define EXTI_RTSR_RTSR17                          EXTI_RTSR_RTSR17_Msk                              
#define EXTI_RTSR_RTSR18_Pos                      (18U)
#define EXTI_RTSR_RTSR18_Msk                      (0x1UL<<EXTI_RTSR_RTSR18_Pos)                     /*!< 0x00040000 */
#define EXTI_RTSR_RTSR18                          EXTI_RTSR_RTSR18_Msk                              
#define EXTI_RTSR_RTSR19_Pos                      (19U)
#define EXTI_RTSR_RTSR19_Msk                      (0x1UL<<EXTI_RTSR_RTSR19_Pos)                     /*!< 0x00080000 */
#define EXTI_RTSR_RTSR19                          EXTI_RTSR_RTSR19_Msk                              
#define EXTI_RTSR_RTSR20_Pos                      (20U)
#define EXTI_RTSR_RTSR20_Msk                      (0x1UL<<EXTI_RTSR_RTSR20_Pos)                     /*!< 0x00100000 */
#define EXTI_RTSR_RTSR20                          EXTI_RTSR_RTSR20_Msk                              
#define EXTI_RTSR_RTSR21_Pos                      (21U)
#define EXTI_RTSR_RTSR21_Msk                      (0x1UL<<EXTI_RTSR_RTSR21_Pos)                     /*!< 0x00200000 */
#define EXTI_RTSR_RTSR21                          EXTI_RTSR_RTSR21_Msk                              

/********************************* Bit definition for EXTI_FTSR register ********************************************/
#define EXTI_FTSR_FTSR0_Pos                       (0U)
#define EXTI_FTSR_FTSR0_Msk                       (0x1UL<<EXTI_FTSR_FTSR0_Pos)                      /*!< 0x00000001 */
#define EXTI_FTSR_FTSR0                           EXTI_FTSR_FTSR0_Msk                               
#define EXTI_FTSR_FTSR1_Pos                       (1U)
#define EXTI_FTSR_FTSR1_Msk                       (0x1UL<<EXTI_FTSR_FTSR1_Pos)                      /*!< 0x00000002 */
#define EXTI_FTSR_FTSR1                           EXTI_FTSR_FTSR1_Msk                               
#define EXTI_FTSR_FTSR2_Pos                       (2U)
#define EXTI_FTSR_FTSR2_Msk                       (0x1UL<<EXTI_FTSR_FTSR2_Pos)                      /*!< 0x00000004 */
#define EXTI_FTSR_FTSR2                           EXTI_FTSR_FTSR2_Msk                               
#define EXTI_FTSR_FTSR3_Pos                       (3U)
#define EXTI_FTSR_FTSR3_Msk                       (0x1UL<<EXTI_FTSR_FTSR3_Pos)                      /*!< 0x00000008 */
#define EXTI_FTSR_FTSR3                           EXTI_FTSR_FTSR3_Msk                               
#define EXTI_FTSR_FTSR4_Pos                       (4U)
#define EXTI_FTSR_FTSR4_Msk                       (0x1UL<<EXTI_FTSR_FTSR4_Pos)                      /*!< 0x00000010 */
#define EXTI_FTSR_FTSR4                           EXTI_FTSR_FTSR4_Msk                               
#define EXTI_FTSR_FTSR5_Pos                       (5U)
#define EXTI_FTSR_FTSR5_Msk                       (0x1UL<<EXTI_FTSR_FTSR5_Pos)                      /*!< 0x00000020 */
#define EXTI_FTSR_FTSR5                           EXTI_FTSR_FTSR5_Msk                               
#define EXTI_FTSR_FTSR6_Pos                       (6U)
#define EXTI_FTSR_FTSR6_Msk                       (0x1UL<<EXTI_FTSR_FTSR6_Pos)                      /*!< 0x00000040 */
#define EXTI_FTSR_FTSR6                           EXTI_FTSR_FTSR6_Msk                               
#define EXTI_FTSR_FTSR7_Pos                       (7U)
#define EXTI_FTSR_FTSR7_Msk                       (0x1UL<<EXTI_FTSR_FTSR7_Pos)                      /*!< 0x00000080 */
#define EXTI_FTSR_FTSR7                           EXTI_FTSR_FTSR7_Msk                               
#define EXTI_FTSR_FTSR8_Pos                       (8U)
#define EXTI_FTSR_FTSR8_Msk                       (0x1UL<<EXTI_FTSR_FTSR8_Pos)                      /*!< 0x00000100 */
#define EXTI_FTSR_FTSR8                           EXTI_FTSR_FTSR8_Msk                               
#define EXTI_FTSR_FTSR9_Pos                       (9U)
#define EXTI_FTSR_FTSR9_Msk                       (0x1UL<<EXTI_FTSR_FTSR9_Pos)                      /*!< 0x00000200 */
#define EXTI_FTSR_FTSR9                           EXTI_FTSR_FTSR9_Msk                               
#define EXTI_FTSR_FTSR10_Pos                      (10U)
#define EXTI_FTSR_FTSR10_Msk                      (0x1UL<<EXTI_FTSR_FTSR10_Pos)                     /*!< 0x00000400 */
#define EXTI_FTSR_FTSR10                          EXTI_FTSR_FTSR10_Msk                              
#define EXTI_FTSR_FTSR11_Pos                      (11U)
#define EXTI_FTSR_FTSR11_Msk                      (0x1UL<<EXTI_FTSR_FTSR11_Pos)                     /*!< 0x00000800 */
#define EXTI_FTSR_FTSR11                          EXTI_FTSR_FTSR11_Msk                              
#define EXTI_FTSR_FTSR12_Pos                      (12U)
#define EXTI_FTSR_FTSR12_Msk                      (0x1UL<<EXTI_FTSR_FTSR12_Pos)                     /*!< 0x00001000 */
#define EXTI_FTSR_FTSR12                          EXTI_FTSR_FTSR12_Msk                              
#define EXTI_FTSR_FTSR13_Pos                      (13U)
#define EXTI_FTSR_FTSR13_Msk                      (0x1UL<<EXTI_FTSR_FTSR13_Pos)                     /*!< 0x00002000 */
#define EXTI_FTSR_FTSR13                          EXTI_FTSR_FTSR13_Msk                              
#define EXTI_FTSR_FTSR14_Pos                      (14U)
#define EXTI_FTSR_FTSR14_Msk                      (0x1UL<<EXTI_FTSR_FTSR14_Pos)                     /*!< 0x00004000 */
#define EXTI_FTSR_FTSR14                          EXTI_FTSR_FTSR14_Msk                              
#define EXTI_FTSR_FTSR15_Pos                      (15U)
#define EXTI_FTSR_FTSR15_Msk                      (0x1UL<<EXTI_FTSR_FTSR15_Pos)                     /*!< 0x00008000 */
#define EXTI_FTSR_FTSR15                          EXTI_FTSR_FTSR15_Msk                              
#define EXTI_FTSR_FTSR16_Pos                      (16U)
#define EXTI_FTSR_FTSR16_Msk                      (0x1UL<<EXTI_FTSR_FTSR16_Pos)                     /*!< 0x00010000 */
#define EXTI_FTSR_FTSR16                          EXTI_FTSR_FTSR16_Msk                              
#define EXTI_FTSR_FTSR17_Pos                      (17U)
#define EXTI_FTSR_FTSR17_Msk                      (0x1UL<<EXTI_FTSR_FTSR17_Pos)                     /*!< 0x00020000 */
#define EXTI_FTSR_FTSR17                          EXTI_FTSR_FTSR17_Msk                              
#define EXTI_FTSR_FTSR18_Pos                      (18U)
#define EXTI_FTSR_FTSR18_Msk                      (0x1UL<<EXTI_FTSR_FTSR18_Pos)                     /*!< 0x00040000 */
#define EXTI_FTSR_FTSR18                          EXTI_FTSR_FTSR18_Msk                              
#define EXTI_FTSR_FTSR19_Pos                      (19U)
#define EXTI_FTSR_FTSR19_Msk                      (0x1UL<<EXTI_FTSR_FTSR19_Pos)                     /*!< 0x00080000 */
#define EXTI_FTSR_FTSR19                          EXTI_FTSR_FTSR19_Msk                              
#define EXTI_FTSR_FTSR20_Pos                      (20U)
#define EXTI_FTSR_FTSR20_Msk                      (0x1UL<<EXTI_FTSR_FTSR20_Pos)                     /*!< 0x00100000 */
#define EXTI_FTSR_FTSR20                          EXTI_FTSR_FTSR20_Msk                              
#define EXTI_FTSR_FTSR21_Pos                      (21U)
#define EXTI_FTSR_FTSR21_Msk                      (0x1UL<<EXTI_FTSR_FTSR21_Pos)                     /*!< 0x00200000 */
#define EXTI_FTSR_FTSR21                          EXTI_FTSR_FTSR21_Msk                              

/********************************* Bit definition for EXTI_SWIER register *******************************************/
#define EXTI_SWIER_SWIER0_Pos                     (0U)
#define EXTI_SWIER_SWIER0_Msk                     (0x1UL<<EXTI_SWIER_SWIER0_Pos)                    /*!< 0x00000001 */
#define EXTI_SWIER_SWIER0                         EXTI_SWIER_SWIER0_Msk                             
#define EXTI_SWIER_SWIER1_Pos                     (1U)
#define EXTI_SWIER_SWIER1_Msk                     (0x1UL<<EXTI_SWIER_SWIER1_Pos)                    /*!< 0x00000002 */
#define EXTI_SWIER_SWIER1                         EXTI_SWIER_SWIER1_Msk                             
#define EXTI_SWIER_SWIER2_Pos                     (2U)
#define EXTI_SWIER_SWIER2_Msk                     (0x1UL<<EXTI_SWIER_SWIER2_Pos)                    /*!< 0x00000004 */
#define EXTI_SWIER_SWIER2                         EXTI_SWIER_SWIER2_Msk                             
#define EXTI_SWIER_SWIER3_Pos                     (3U)
#define EXTI_SWIER_SWIER3_Msk                     (0x1UL<<EXTI_SWIER_SWIER3_Pos)                    /*!< 0x00000008 */
#define EXTI_SWIER_SWIER3                         EXTI_SWIER_SWIER3_Msk                             
#define EXTI_SWIER_SWIER4_Pos                     (4U)
#define EXTI_SWIER_SWIER4_Msk                     (0x1UL<<EXTI_SWIER_SWIER4_Pos)                    /*!< 0x00000010 */
#define EXTI_SWIER_SWIER4                         EXTI_SWIER_SWIER4_Msk                             
#define EXTI_SWIER_SWIER5_Pos                     (5U)
#define EXTI_SWIER_SWIER5_Msk                     (0x1UL<<EXTI_SWIER_SWIER5_Pos)                    /*!< 0x00000020 */
#define EXTI_SWIER_SWIER5                         EXTI_SWIER_SWIER5_Msk                             
#define EXTI_SWIER_SWIER6_Pos                     (6U)
#define EXTI_SWIER_SWIER6_Msk                     (0x1UL<<EXTI_SWIER_SWIER6_Pos)                    /*!< 0x00000040 */
#define EXTI_SWIER_SWIER6                         EXTI_SWIER_SWIER6_Msk                             
#define EXTI_SWIER_SWIER7_Pos                     (7U)
#define EXTI_SWIER_SWIER7_Msk                     (0x1UL<<EXTI_SWIER_SWIER7_Pos)                    /*!< 0x00000080 */
#define EXTI_SWIER_SWIER7                         EXTI_SWIER_SWIER7_Msk                             
#define EXTI_SWIER_SWIER8_Pos                     (8U)
#define EXTI_SWIER_SWIER8_Msk                     (0x1UL<<EXTI_SWIER_SWIER8_Pos)                    /*!< 0x00000100 */
#define EXTI_SWIER_SWIER8                         EXTI_SWIER_SWIER8_Msk                             
#define EXTI_SWIER_SWIER9_Pos                     (9U)
#define EXTI_SWIER_SWIER9_Msk                     (0x1UL<<EXTI_SWIER_SWIER9_Pos)                    /*!< 0x00000200 */
#define EXTI_SWIER_SWIER9                         EXTI_SWIER_SWIER9_Msk                             
#define EXTI_SWIER_SWIER10_Pos                    (10U)
#define EXTI_SWIER_SWIER10_Msk                    (0x1UL<<EXTI_SWIER_SWIER10_Pos)                   /*!< 0x00000400 */
#define EXTI_SWIER_SWIER10                        EXTI_SWIER_SWIER10_Msk                            
#define EXTI_SWIER_SWIER11_Pos                    (11U)
#define EXTI_SWIER_SWIER11_Msk                    (0x1UL<<EXTI_SWIER_SWIER11_Pos)                   /*!< 0x00000800 */
#define EXTI_SWIER_SWIER11                        EXTI_SWIER_SWIER11_Msk                            
#define EXTI_SWIER_SWIER12_Pos                    (12U)
#define EXTI_SWIER_SWIER12_Msk                    (0x1UL<<EXTI_SWIER_SWIER12_Pos)                   /*!< 0x00001000 */
#define EXTI_SWIER_SWIER12                        EXTI_SWIER_SWIER12_Msk                            
#define EXTI_SWIER_SWIER13_Pos                    (13U)
#define EXTI_SWIER_SWIER13_Msk                    (0x1UL<<EXTI_SWIER_SWIER13_Pos)                   /*!< 0x00002000 */
#define EXTI_SWIER_SWIER13                        EXTI_SWIER_SWIER13_Msk                            
#define EXTI_SWIER_SWIER14_Pos                    (14U)
#define EXTI_SWIER_SWIER14_Msk                    (0x1UL<<EXTI_SWIER_SWIER14_Pos)                   /*!< 0x00004000 */
#define EXTI_SWIER_SWIER14                        EXTI_SWIER_SWIER14_Msk                            
#define EXTI_SWIER_SWIER15_Pos                    (15U)
#define EXTI_SWIER_SWIER15_Msk                    (0x1UL<<EXTI_SWIER_SWIER15_Pos)                   /*!< 0x00008000 */
#define EXTI_SWIER_SWIER15                        EXTI_SWIER_SWIER15_Msk                            
#define EXTI_SWIER_SWIER16_Pos                    (16U)
#define EXTI_SWIER_SWIER16_Msk                    (0x1UL<<EXTI_SWIER_SWIER16_Pos)                   /*!< 0x00010000 */
#define EXTI_SWIER_SWIER16                        EXTI_SWIER_SWIER16_Msk                            
#define EXTI_SWIER_SWIER17_Pos                    (17U)
#define EXTI_SWIER_SWIER17_Msk                    (0x1UL<<EXTI_SWIER_SWIER17_Pos)                   /*!< 0x00020000 */
#define EXTI_SWIER_SWIER17                        EXTI_SWIER_SWIER17_Msk                            
#define EXTI_SWIER_SWIER18_Pos                    (18U)
#define EXTI_SWIER_SWIER18_Msk                    (0x1UL<<EXTI_SWIER_SWIER18_Pos)                   /*!< 0x00040000 */
#define EXTI_SWIER_SWIER18                        EXTI_SWIER_SWIER18_Msk                            
#define EXTI_SWIER_SWIER19_Pos                    (19U)
#define EXTI_SWIER_SWIER19_Msk                    (0x1UL<<EXTI_SWIER_SWIER19_Pos)                   /*!< 0x00080000 */
#define EXTI_SWIER_SWIER19                        EXTI_SWIER_SWIER19_Msk                            
#define EXTI_SWIER_SWIER20_Pos                    (20U)
#define EXTI_SWIER_SWIER20_Msk                    (0x1UL<<EXTI_SWIER_SWIER20_Pos)                   /*!< 0x00100000 */
#define EXTI_SWIER_SWIER20                        EXTI_SWIER_SWIER20_Msk                            
#define EXTI_SWIER_SWIER21_Pos                    (21U)
#define EXTI_SWIER_SWIER21_Msk                    (0x1UL<<EXTI_SWIER_SWIER21_Pos)                   /*!< 0x00200000 */
#define EXTI_SWIER_SWIER21                        EXTI_SWIER_SWIER21_Msk                            

/********************************* Bit definition for EXTI_PR register **********************************************/
#define EXTI_PR_PR0_Pos                           (0U)
#define EXTI_PR_PR0_Msk                           (0x1UL<<EXTI_PR_PR0_Pos)                          /*!< 0x00000001 */
#define EXTI_PR_PR0                               EXTI_PR_PR0_Msk                                   
#define EXTI_PR_PR1_Pos                           (1U)
#define EXTI_PR_PR1_Msk                           (0x1UL<<EXTI_PR_PR1_Pos)                          /*!< 0x00000002 */
#define EXTI_PR_PR1                               EXTI_PR_PR1_Msk                                   
#define EXTI_PR_PR2_Pos                           (2U)
#define EXTI_PR_PR2_Msk                           (0x1UL<<EXTI_PR_PR2_Pos)                          /*!< 0x00000004 */
#define EXTI_PR_PR2                               EXTI_PR_PR2_Msk                                   
#define EXTI_PR_PR3_Pos                           (3U)
#define EXTI_PR_PR3_Msk                           (0x1UL<<EXTI_PR_PR3_Pos)                          /*!< 0x00000008 */
#define EXTI_PR_PR3                               EXTI_PR_PR3_Msk                                   
#define EXTI_PR_PR4_Pos                           (4U)
#define EXTI_PR_PR4_Msk                           (0x1UL<<EXTI_PR_PR4_Pos)                          /*!< 0x00000010 */
#define EXTI_PR_PR4                               EXTI_PR_PR4_Msk                                   
#define EXTI_PR_PR5_Pos                           (5U)
#define EXTI_PR_PR5_Msk                           (0x1UL<<EXTI_PR_PR5_Pos)                          /*!< 0x00000020 */
#define EXTI_PR_PR5                               EXTI_PR_PR5_Msk                                   
#define EXTI_PR_PR6_Pos                           (6U)
#define EXTI_PR_PR6_Msk                           (0x1UL<<EXTI_PR_PR6_Pos)                          /*!< 0x00000040 */
#define EXTI_PR_PR6                               EXTI_PR_PR6_Msk                                   
#define EXTI_PR_PR7_Pos                           (7U)
#define EXTI_PR_PR7_Msk                           (0x1UL<<EXTI_PR_PR7_Pos)                          /*!< 0x00000080 */
#define EXTI_PR_PR7                               EXTI_PR_PR7_Msk                                   
#define EXTI_PR_PR8_Pos                           (8U)
#define EXTI_PR_PR8_Msk                           (0x1UL<<EXTI_PR_PR8_Pos)                          /*!< 0x00000100 */
#define EXTI_PR_PR8                               EXTI_PR_PR8_Msk                                   
#define EXTI_PR_PR9_Pos                           (9U)
#define EXTI_PR_PR9_Msk                           (0x1UL<<EXTI_PR_PR9_Pos)                          /*!< 0x00000200 */
#define EXTI_PR_PR9                               EXTI_PR_PR9_Msk                                   
#define EXTI_PR_PR10_Pos                          (10U)
#define EXTI_PR_PR10_Msk                          (0x1UL<<EXTI_PR_PR10_Pos)                         /*!< 0x00000400 */
#define EXTI_PR_PR10                              EXTI_PR_PR10_Msk                                  
#define EXTI_PR_PR11_Pos                          (11U)
#define EXTI_PR_PR11_Msk                          (0x1UL<<EXTI_PR_PR11_Pos)                         /*!< 0x00000800 */
#define EXTI_PR_PR11                              EXTI_PR_PR11_Msk                                  
#define EXTI_PR_PR12_Pos                          (12U)
#define EXTI_PR_PR12_Msk                          (0x1UL<<EXTI_PR_PR12_Pos)                         /*!< 0x00001000 */
#define EXTI_PR_PR12                              EXTI_PR_PR12_Msk                                  
#define EXTI_PR_PR13_Pos                          (13U)
#define EXTI_PR_PR13_Msk                          (0x1UL<<EXTI_PR_PR13_Pos)                         /*!< 0x00002000 */
#define EXTI_PR_PR13                              EXTI_PR_PR13_Msk                                  
#define EXTI_PR_PR14_Pos                          (14U)
#define EXTI_PR_PR14_Msk                          (0x1UL<<EXTI_PR_PR14_Pos)                         /*!< 0x00004000 */
#define EXTI_PR_PR14                              EXTI_PR_PR14_Msk                                  
#define EXTI_PR_PR15_Pos                          (15U)
#define EXTI_PR_PR15_Msk                          (0x1UL<<EXTI_PR_PR15_Pos)                         /*!< 0x00008000 */
#define EXTI_PR_PR15                              EXTI_PR_PR15_Msk                                  
#define EXTI_PR_PR16_Pos                          (16U)
#define EXTI_PR_PR16_Msk                          (0x1UL<<EXTI_PR_PR16_Pos)                         /*!< 0x00010000 */
#define EXTI_PR_PR16                              EXTI_PR_PR16_Msk                                  
#define EXTI_PR_PR17_Pos                          (17U)
#define EXTI_PR_PR17_Msk                          (0x1UL<<EXTI_PR_PR17_Pos)                         /*!< 0x00020000 */
#define EXTI_PR_PR17                              EXTI_PR_PR17_Msk                                  
#define EXTI_PR_PR18_Pos                          (18U)
#define EXTI_PR_PR18_Msk                          (0x1UL<<EXTI_PR_PR18_Pos)                         /*!< 0x00040000 */
#define EXTI_PR_PR18                              EXTI_PR_PR18_Msk                                  
#define EXTI_PR_PR19_Pos                          (19U)
#define EXTI_PR_PR19_Msk                          (0x1UL<<EXTI_PR_PR19_Pos)                         /*!< 0x00080000 */
#define EXTI_PR_PR19                              EXTI_PR_PR19_Msk                                  
#define EXTI_PR_PR20_Pos                          (20U)
#define EXTI_PR_PR20_Msk                          (0x1UL<<EXTI_PR_PR20_Pos)                         /*!< 0x00100000 */
#define EXTI_PR_PR20                              EXTI_PR_PR20_Msk                                  
#define EXTI_PR_PR21_Pos                          (21U)
#define EXTI_PR_PR21_Msk                          (0x1UL<<EXTI_PR_PR21_Pos)                         /*!< 0x00200000 */
#define EXTI_PR_PR21                              EXTI_PR_PR21_Msk                                  

/********************************************************************************************************************/
/********************************* ADC ******************************************************************************/
/********************************************************************************************************************/
#define ADC_MULTIMODE_SUPPORT

/********************************* Bit definition for ADC_ISR register **********************************************/
#define ADC_ISR_ADRDY_Pos                         (0U)
#define ADC_ISR_ADRDY_Msk                         (0x1UL<<ADC_ISR_ADRDY_Pos)                        /*!< 0x00000001 */
#define ADC_ISR_ADRDY                             ADC_ISR_ADRDY_Msk                                 
#define ADC_ISR_EOSMP_Pos                         (1U)
#define ADC_ISR_EOSMP_Msk                         (0x1UL<<ADC_ISR_EOSMP_Pos)                        /*!< 0x00000002 */
#define ADC_ISR_EOSMP                             ADC_ISR_EOSMP_Msk                                 
#define ADC_ISR_EOC_Pos                           (2U)
#define ADC_ISR_EOC_Msk                           (0x1UL<<ADC_ISR_EOC_Pos)                          /*!< 0x00000004 */
#define ADC_ISR_EOC                               ADC_ISR_EOC_Msk                                   
#define ADC_ISR_EOS_Pos                           (3U)
#define ADC_ISR_EOS_Msk                           (0x1UL<<ADC_ISR_EOS_Pos)                          /*!< 0x00000008 */
#define ADC_ISR_EOS                               ADC_ISR_EOS_Msk                                   
#define ADC_ISR_OVR_Pos                           (4U)
#define ADC_ISR_OVR_Msk                           (0x1UL<<ADC_ISR_OVR_Pos)                          /*!< 0x00000010 */
#define ADC_ISR_OVR                               ADC_ISR_OVR_Msk                                   
#define ADC_ISR_JEOC_Pos                          (5U)
#define ADC_ISR_JEOC_Msk                          (0x1UL<<ADC_ISR_JEOC_Pos)                         /*!< 0x00000020 */
#define ADC_ISR_JEOC                              ADC_ISR_JEOC_Msk                                  
#define ADC_ISR_JEOS_Pos                          (6U)
#define ADC_ISR_JEOS_Msk                          (0x1UL<<ADC_ISR_JEOS_Pos)                         /*!< 0x00000040 */
#define ADC_ISR_JEOS                              ADC_ISR_JEOS_Msk                                  
#define ADC_ISR_AWD1_Pos                          (7U)
#define ADC_ISR_AWD1_Msk                          (0x1UL<<ADC_ISR_AWD1_Pos)                         /*!< 0x00000080 */
#define ADC_ISR_AWD1                              ADC_ISR_AWD1_Msk                                  
#define ADC_ISR_AWD2_Pos                          (8U)
#define ADC_ISR_AWD2_Msk                          (0x1UL<<ADC_ISR_AWD2_Pos)                         /*!< 0x00000100 */
#define ADC_ISR_AWD2                              ADC_ISR_AWD2_Msk                                  
#define ADC_ISR_AWD3_Pos                          (9U)
#define ADC_ISR_AWD3_Msk                          (0x1UL<<ADC_ISR_AWD3_Pos)                         /*!< 0x00000200 */
#define ADC_ISR_AWD3                              ADC_ISR_AWD3_Msk                                  
#define ADC_ISR_EOCAL_Pos                         (11U)
#define ADC_ISR_EOCAL_Msk                         (0x1UL<<ADC_ISR_EOCAL_Pos)                        /*!< 0x00000800 */
#define ADC_ISR_EOCAL                             ADC_ISR_EOCAL_Msk                                 

/********************************* Bit definition for ADC_IER register **********************************************/
#define ADC_IER_ADRDYIE_Pos                       (0U)
#define ADC_IER_ADRDYIE_Msk                       (0x1UL<<ADC_IER_ADRDYIE_Pos)                      /*!< 0x00000001 */
#define ADC_IER_ADRDYIE                           ADC_IER_ADRDYIE_Msk                               
#define ADC_IER_EOSMPIE_Pos                       (1U)
#define ADC_IER_EOSMPIE_Msk                       (0x1UL<<ADC_IER_EOSMPIE_Pos)                      /*!< 0x00000002 */
#define ADC_IER_EOSMPIE                           ADC_IER_EOSMPIE_Msk                               
#define ADC_IER_EOCIE_Pos                         (2U)
#define ADC_IER_EOCIE_Msk                         (0x1UL<<ADC_IER_EOCIE_Pos)                        /*!< 0x00000004 */
#define ADC_IER_EOCIE                             ADC_IER_EOCIE_Msk                                 
#define ADC_IER_EOSIE_Pos                         (3U)
#define ADC_IER_EOSIE_Msk                         (0x1UL<<ADC_IER_EOSIE_Pos)                        /*!< 0x00000008 */
#define ADC_IER_EOSIE                             ADC_IER_EOSIE_Msk                                 
#define ADC_IER_OVRIE_Pos                         (4U)
#define ADC_IER_OVRIE_Msk                         (0x1UL<<ADC_IER_OVRIE_Pos)                        /*!< 0x00000010 */
#define ADC_IER_OVRIE                             ADC_IER_OVRIE_Msk                                 
#define ADC_IER_JEOCIE_Pos                        (5U)
#define ADC_IER_JEOCIE_Msk                        (0x1UL<<ADC_IER_JEOCIE_Pos)                       /*!< 0x00000020 */
#define ADC_IER_JEOCIE                            ADC_IER_JEOCIE_Msk                                
#define ADC_IER_JEOSIE_Pos                        (6U)
#define ADC_IER_JEOSIE_Msk                        (0x1UL<<ADC_IER_JEOSIE_Pos)                       /*!< 0x00000040 */
#define ADC_IER_JEOSIE                            ADC_IER_JEOSIE_Msk                                
#define ADC_IER_AWD1IE_Pos                        (7U)
#define ADC_IER_AWD1IE_Msk                        (0x1UL<<ADC_IER_AWD1IE_Pos)                       /*!< 0x00000080 */
#define ADC_IER_AWD1IE                            ADC_IER_AWD1IE_Msk                                
#define ADC_IER_AWD2IE_Pos                        (8U)
#define ADC_IER_AWD2IE_Msk                        (0x1UL<<ADC_IER_AWD2IE_Pos)                       /*!< 0x00000100 */
#define ADC_IER_AWD2IE                            ADC_IER_AWD2IE_Msk                                
#define ADC_IER_AWD3IE_Pos                        (9U)
#define ADC_IER_AWD3IE_Msk                        (0x1UL<<ADC_IER_AWD3IE_Pos)                       /*!< 0x00000200 */
#define ADC_IER_AWD3IE                            ADC_IER_AWD3IE_Msk                                
#define ADC_IER_EOCALIE_Pos                       (11U)
#define ADC_IER_EOCALIE_Msk                       (0x1UL<<ADC_IER_EOCALIE_Pos)                      /*!< 0x00000800 */
#define ADC_IER_EOCALIE                           ADC_IER_EOCALIE_Msk                               

/********************************* Bit definition for ADC_CR register ***********************************************/
#define ADC_CR_ADEN_Pos                           (0U)
#define ADC_CR_ADEN_Msk                           (0x1UL<<ADC_CR_ADEN_Pos)                          /*!< 0x00000001 */
#define ADC_CR_ADEN                               ADC_CR_ADEN_Msk                                   
#define ADC_CR_ADDIS_Pos                          (1U)
#define ADC_CR_ADDIS_Msk                          (0x1UL<<ADC_CR_ADDIS_Pos)                         /*!< 0x00000002 */
#define ADC_CR_ADDIS                              ADC_CR_ADDIS_Msk                                  
#define ADC_CR_ADSTART_Pos                        (2U)
#define ADC_CR_ADSTART_Msk                        (0x1UL<<ADC_CR_ADSTART_Pos)                       /*!< 0x00000004 */
#define ADC_CR_ADSTART                            ADC_CR_ADSTART_Msk                                
#define ADC_CR_JADSTART_Pos                       (3U)
#define ADC_CR_JADSTART_Msk                       (0x1UL<<ADC_CR_JADSTART_Pos)                      /*!< 0x00000008 */
#define ADC_CR_JADSTART                           ADC_CR_JADSTART_Msk                               
#define ADC_CR_ADSTP_Pos                          (4U)
#define ADC_CR_ADSTP_Msk                          (0x1UL<<ADC_CR_ADSTP_Pos)                         /*!< 0x00000010 */
#define ADC_CR_ADSTP                              ADC_CR_ADSTP_Msk                                  
#define ADC_CR_JADSTP_Pos                         (5U)
#define ADC_CR_JADSTP_Msk                         (0x1UL<<ADC_CR_JADSTP_Pos)                        /*!< 0x00000020 */
#define ADC_CR_JADSTP                             ADC_CR_JADSTP_Msk                                 
#define ADC_CR_RSTCAL_Pos                         (27U)
#define ADC_CR_RSTCAL_Msk                         (0x1UL<<ADC_CR_RSTCAL_Pos)                        /*!< 0x08000000 */
#define ADC_CR_RSTCAL                             ADC_CR_RSTCAL_Msk                                 
#define ADC_CR_ADCAL_Pos                          (31U)
#define ADC_CR_ADCAL_Msk                          (0x1UL<<ADC_CR_ADCAL_Pos)                         /*!< 0x80000000 */
#define ADC_CR_ADCAL                              ADC_CR_ADCAL_Msk                                  

/********************************* Bit definition for ADC_CFGR register *********************************************/
#define ADC_CFGR_DMAEN_Pos                        (0U)
#define ADC_CFGR_DMAEN_Msk                        (0x1UL<<ADC_CFGR_DMAEN_Pos)                       /*!< 0x00000001 */
#define ADC_CFGR_DMAEN                            ADC_CFGR_DMAEN_Msk                                
#define ADC_CFGR_DMACFG_Pos                       (1U)
#define ADC_CFGR_DMACFG_Msk                       (0x1UL<<ADC_CFGR_DMACFG_Pos)                      /*!< 0x00000002 */
#define ADC_CFGR_DMACFG                           ADC_CFGR_DMACFG_Msk                               
#define ADC_CFGR_RES_Pos                          (3U)
#define ADC_CFGR_RES_Msk                          (0x3UL<<ADC_CFGR_RES_Pos)                         /*!< 0x00000018 */
#define ADC_CFGR_RES                              ADC_CFGR_RES_Msk
#define ADC_CFGR_RES_0                            (0x1UL<<ADC_CFGR_RES_Pos)                         /*!< 0x00000008 */
#define ADC_CFGR_RES_1                            (0x2UL<<ADC_CFGR_RES_Pos)                         /*!< 0x00000010 */
#define ADC_CFGR_EXTSEL_Pos                       (5U)
#define ADC_CFGR_EXTSEL_Msk                       (0x1FUL<<ADC_CFGR_EXTSEL_Pos)                     /*!< 0x000003E0 */
#define ADC_CFGR_EXTSEL                           ADC_CFGR_EXTSEL_Msk
#define ADC_CFGR_EXTSEL_0                         (0x1UL<<ADC_CFGR_EXTSEL_Pos)                      /*!< 0x00000020 */
#define ADC_CFGR_EXTSEL_1                         (0x2UL<<ADC_CFGR_EXTSEL_Pos)                      /*!< 0x00000040 */
#define ADC_CFGR_EXTSEL_2                         (0x4UL<<ADC_CFGR_EXTSEL_Pos)                      /*!< 0x00000080 */
#define ADC_CFGR_EXTSEL_3                         (0x8UL<<ADC_CFGR_EXTSEL_Pos)                      /*!< 0x00000100 */
#define ADC_CFGR_EXTSEL_4                         (0x10UL<<ADC_CFGR_EXTSEL_Pos)                     /*!< 0x00000200 */
#define ADC_CFGR_EXTEN_Pos                        (10U)
#define ADC_CFGR_EXTEN_Msk                        (0x3UL<<ADC_CFGR_EXTEN_Pos)                       /*!< 0x00000C00 */
#define ADC_CFGR_EXTEN                            ADC_CFGR_EXTEN_Msk
#define ADC_CFGR_EXTEN_0                          (0x1UL<<ADC_CFGR_EXTEN_Pos)                       /*!< 0x00000400 */
#define ADC_CFGR_EXTEN_1                          (0x2UL<<ADC_CFGR_EXTEN_Pos)                       /*!< 0x00000800 */
#define ADC_CFGR_OVRMOD_Pos                       (12U)
#define ADC_CFGR_OVRMOD_Msk                       (0x1UL<<ADC_CFGR_OVRMOD_Pos)                      /*!< 0x00001000 */
#define ADC_CFGR_OVRMOD                           ADC_CFGR_OVRMOD_Msk                               
#define ADC_CFGR_CONT_Pos                         (13U)
#define ADC_CFGR_CONT_Msk                         (0x1UL<<ADC_CFGR_CONT_Pos)                        /*!< 0x00002000 */
#define ADC_CFGR_CONT                             ADC_CFGR_CONT_Msk                                 
#define ADC_CFGR_AUTDLY_Pos                       (14U)
#define ADC_CFGR_AUTDLY_Msk                       (0x1UL<<ADC_CFGR_AUTDLY_Pos)                      /*!< 0x00004000 */
#define ADC_CFGR_AUTDLY                           ADC_CFGR_AUTDLY_Msk                               
#define ADC_CFGR_ALIGN_Pos                        (15U)
#define ADC_CFGR_ALIGN_Msk                        (0x1UL<<ADC_CFGR_ALIGN_Pos)                       /*!< 0x00008000 */
#define ADC_CFGR_ALIGN                            ADC_CFGR_ALIGN_Msk                                
#define ADC_CFGR_DISCEN_Pos                       (16U)
#define ADC_CFGR_DISCEN_Msk                       (0x1UL<<ADC_CFGR_DISCEN_Pos)                      /*!< 0x00010000 */
#define ADC_CFGR_DISCEN                           ADC_CFGR_DISCEN_Msk                               
#define ADC_CFGR_DISCNUM_Pos                      (17U)
#define ADC_CFGR_DISCNUM_Msk                      (0x7UL<<ADC_CFGR_DISCNUM_Pos)                     /*!< 0x000E0000 */
#define ADC_CFGR_DISCNUM                          ADC_CFGR_DISCNUM_Msk
#define ADC_CFGR_DISCNUM_0                        (0x1UL<<ADC_CFGR_DISCNUM_Pos)                     /*!< 0x00020000 */
#define ADC_CFGR_DISCNUM_1                        (0x2UL<<ADC_CFGR_DISCNUM_Pos)                     /*!< 0x00040000 */
#define ADC_CFGR_DISCNUM_2                        (0x4UL<<ADC_CFGR_DISCNUM_Pos)                     /*!< 0x00080000 */
#define ADC_CFGR_JDISCEN_Pos                      (20U)
#define ADC_CFGR_JDISCEN_Msk                      (0x1UL<<ADC_CFGR_JDISCEN_Pos)                     /*!< 0x00100000 */
#define ADC_CFGR_JDISCEN                          ADC_CFGR_JDISCEN_Msk                              
#define ADC_CFGR_AWD1SGL_Pos                      (22U)
#define ADC_CFGR_AWD1SGL_Msk                      (0x1UL<<ADC_CFGR_AWD1SGL_Pos)                     /*!< 0x00400000 */
#define ADC_CFGR_AWD1SGL                          ADC_CFGR_AWD1SGL_Msk                              
#define ADC_CFGR_AWD1EN_Pos                       (23U)
#define ADC_CFGR_AWD1EN_Msk                       (0x1UL<<ADC_CFGR_AWD1EN_Pos)                      /*!< 0x00800000 */
#define ADC_CFGR_AWD1EN                           ADC_CFGR_AWD1EN_Msk                               
#define ADC_CFGR_JAWD1EN_Pos                      (24U)
#define ADC_CFGR_JAWD1EN_Msk                      (0x1UL<<ADC_CFGR_JAWD1EN_Pos)                     /*!< 0x01000000 */
#define ADC_CFGR_JAWD1EN                          ADC_CFGR_JAWD1EN_Msk                              
#define ADC_CFGR_JAUTO_Pos                        (25U)
#define ADC_CFGR_JAUTO_Msk                        (0x1UL<<ADC_CFGR_JAUTO_Pos)                       /*!< 0x02000000 */
#define ADC_CFGR_JAUTO                            ADC_CFGR_JAUTO_Msk                                
#define ADC_CFGR_AWD1CH_Pos                       (26U)
#define ADC_CFGR_AWD1CH_Msk                       (0x1FUL<<ADC_CFGR_AWD1CH_Pos)                     /*!< 0x7C000000 */
#define ADC_CFGR_AWD1CH                           ADC_CFGR_AWD1CH_Msk
#define ADC_CFGR_AWD1CH_0                         (0x1UL<<ADC_CFGR_AWD1CH_Pos)                      /*!< 0x04000000 */
#define ADC_CFGR_AWD1CH_1                         (0x2UL<<ADC_CFGR_AWD1CH_Pos)                      /*!< 0x08000000 */
#define ADC_CFGR_AWD1CH_2                         (0x4UL<<ADC_CFGR_AWD1CH_Pos)                      /*!< 0x10000000 */
#define ADC_CFGR_AWD1CH_3                         (0x8UL<<ADC_CFGR_AWD1CH_Pos)                      /*!< 0x20000000 */
#define ADC_CFGR_AWD1CH_4                         (0x10UL<<ADC_CFGR_AWD1CH_Pos)                     /*!< 0x40000000 */

/********************************* Bit definition for ADC_CFGR2 register ********************************************/
#define ADC_CFGR2_ROVSE_Pos                       (0U)
#define ADC_CFGR2_ROVSE_Msk                       (0x1UL<<ADC_CFGR2_ROVSE_Pos)                      /*!< 0x00000001 */
#define ADC_CFGR2_ROVSE                           ADC_CFGR2_ROVSE_Msk                               
#define ADC_CFGR2_JOVSE_Pos                       (1U)
#define ADC_CFGR2_JOVSE_Msk                       (0x1UL<<ADC_CFGR2_JOVSE_Pos)                      /*!< 0x00000002 */
#define ADC_CFGR2_JOVSE                           ADC_CFGR2_JOVSE_Msk                               
#define ADC_CFGR2_OVSR_Pos                        (2U)
#define ADC_CFGR2_OVSR_Msk                        (0x7UL<<ADC_CFGR2_OVSR_Pos)                       /*!< 0x0000001C */
#define ADC_CFGR2_OVSR                            ADC_CFGR2_OVSR_Msk
#define ADC_CFGR2_OVSR_0                          (0x1UL<<ADC_CFGR2_OVSR_Pos)                       /*!< 0x00000004 */
#define ADC_CFGR2_OVSR_1                          (0x2UL<<ADC_CFGR2_OVSR_Pos)                       /*!< 0x00000008 */
#define ADC_CFGR2_OVSR_2                          (0x4UL<<ADC_CFGR2_OVSR_Pos)                       /*!< 0x00000010 */
#define ADC_CFGR2_OVSS_Pos                        (5U)
#define ADC_CFGR2_OVSS_Msk                        (0xFUL<<ADC_CFGR2_OVSS_Pos)                       /*!< 0x000001E0 */
#define ADC_CFGR2_OVSS                            ADC_CFGR2_OVSS_Msk
#define ADC_CFGR2_OVSS_0                          (0x1UL<<ADC_CFGR2_OVSS_Pos)                       /*!< 0x00000020 */
#define ADC_CFGR2_OVSS_1                          (0x2UL<<ADC_CFGR2_OVSS_Pos)                       /*!< 0x00000040 */
#define ADC_CFGR2_OVSS_2                          (0x4UL<<ADC_CFGR2_OVSS_Pos)                       /*!< 0x00000080 */
#define ADC_CFGR2_OVSS_3                          (0x8UL<<ADC_CFGR2_OVSS_Pos)                       /*!< 0x00000100 */
#define ADC_CFGR2_TROVS_Pos                       (9U)
#define ADC_CFGR2_TROVS_Msk                       (0x1UL<<ADC_CFGR2_TROVS_Pos)                      /*!< 0x00000200 */
#define ADC_CFGR2_TROVS                           ADC_CFGR2_TROVS_Msk                               
#define ADC_CFGR2_ROVSM_Pos                       (10U)
#define ADC_CFGR2_ROVSM_Msk                       (0x1UL<<ADC_CFGR2_ROVSM_Pos)                      /*!< 0x00000400 */
#define ADC_CFGR2_ROVSM                           ADC_CFGR2_ROVSM_Msk                               
#define ADC_CFGR2_GCOMP_Pos                       (16U)
#define ADC_CFGR2_GCOMP_Msk                       (0x1UL<<ADC_CFGR2_GCOMP_Pos)                      /*!< 0x00010000 */
#define ADC_CFGR2_GCOMP                           ADC_CFGR2_GCOMP_Msk                               
#define ADC_CFGR2_CALNUM_Pos                      (28U)
#define ADC_CFGR2_CALNUM_Msk                      (0x7UL<<ADC_CFGR2_CALNUM_Pos)                     /*!< 0x70000000 */
#define ADC_CFGR2_CALNUM                          ADC_CFGR2_CALNUM_Msk
#define ADC_CFGR2_CALNUM_0                        (0x1UL<<ADC_CFGR2_CALNUM_Pos)                     /*!< 0x10000000 */
#define ADC_CFGR2_CALNUM_1                        (0x2UL<<ADC_CFGR2_CALNUM_Pos)                     /*!< 0x20000000 */
#define ADC_CFGR2_CALNUM_2                        (0x4UL<<ADC_CFGR2_CALNUM_Pos)                     /*!< 0x40000000 */

/********************************* Bit definition for ADC_SMPR1 register ********************************************/
#define ADC_SMPR1_SMP0_Pos                        (0U)
#define ADC_SMPR1_SMP0_Msk                        (0x7UL<<ADC_SMPR1_SMP0_Pos)                       /*!< 0x00000007 */
#define ADC_SMPR1_SMP0                            ADC_SMPR1_SMP0_Msk
#define ADC_SMPR1_SMP0_0                          (0x1UL<<ADC_SMPR1_SMP0_Pos)                       /*!< 0x00000001 */
#define ADC_SMPR1_SMP0_1                          (0x2UL<<ADC_SMPR1_SMP0_Pos)                       /*!< 0x00000002 */
#define ADC_SMPR1_SMP0_2                          (0x4UL<<ADC_SMPR1_SMP0_Pos)                       /*!< 0x00000004 */
#define ADC_SMPR1_SMP1_Pos                        (3U)
#define ADC_SMPR1_SMP1_Msk                        (0x7UL<<ADC_SMPR1_SMP1_Pos)                       /*!< 0x00000038 */
#define ADC_SMPR1_SMP1                            ADC_SMPR1_SMP1_Msk
#define ADC_SMPR1_SMP1_0                          (0x1UL<<ADC_SMPR1_SMP1_Pos)                       /*!< 0x00000008 */
#define ADC_SMPR1_SMP1_1                          (0x2UL<<ADC_SMPR1_SMP1_Pos)                       /*!< 0x00000010 */
#define ADC_SMPR1_SMP1_2                          (0x4UL<<ADC_SMPR1_SMP1_Pos)                       /*!< 0x00000020 */
#define ADC_SMPR1_SMP2_Pos                        (6U)
#define ADC_SMPR1_SMP2_Msk                        (0x7UL<<ADC_SMPR1_SMP2_Pos)                       /*!< 0x000001C0 */
#define ADC_SMPR1_SMP2                            ADC_SMPR1_SMP2_Msk
#define ADC_SMPR1_SMP2_0                          (0x1UL<<ADC_SMPR1_SMP2_Pos)                       /*!< 0x00000040 */
#define ADC_SMPR1_SMP2_1                          (0x2UL<<ADC_SMPR1_SMP2_Pos)                       /*!< 0x00000080 */
#define ADC_SMPR1_SMP2_2                          (0x4UL<<ADC_SMPR1_SMP2_Pos)                       /*!< 0x00000100 */
#define ADC_SMPR1_SMP3_Pos                        (9U)
#define ADC_SMPR1_SMP3_Msk                        (0x7UL<<ADC_SMPR1_SMP3_Pos)                       /*!< 0x00000E00 */
#define ADC_SMPR1_SMP3                            ADC_SMPR1_SMP3_Msk
#define ADC_SMPR1_SMP3_0                          (0x1UL<<ADC_SMPR1_SMP3_Pos)                       /*!< 0x00000200 */
#define ADC_SMPR1_SMP3_1                          (0x2UL<<ADC_SMPR1_SMP3_Pos)                       /*!< 0x00000400 */
#define ADC_SMPR1_SMP3_2                          (0x4UL<<ADC_SMPR1_SMP3_Pos)                       /*!< 0x00000800 */
#define ADC_SMPR1_SMP4_Pos                        (12U)
#define ADC_SMPR1_SMP4_Msk                        (0x7UL<<ADC_SMPR1_SMP4_Pos)                       /*!< 0x00007000 */
#define ADC_SMPR1_SMP4                            ADC_SMPR1_SMP4_Msk
#define ADC_SMPR1_SMP4_0                          (0x1UL<<ADC_SMPR1_SMP4_Pos)                       /*!< 0x00001000 */
#define ADC_SMPR1_SMP4_1                          (0x2UL<<ADC_SMPR1_SMP4_Pos)                       /*!< 0x00002000 */
#define ADC_SMPR1_SMP4_2                          (0x4UL<<ADC_SMPR1_SMP4_Pos)                       /*!< 0x00004000 */
#define ADC_SMPR1_SMP5_Pos                        (15U)
#define ADC_SMPR1_SMP5_Msk                        (0x7UL<<ADC_SMPR1_SMP5_Pos)                       /*!< 0x00038000 */
#define ADC_SMPR1_SMP5                            ADC_SMPR1_SMP5_Msk
#define ADC_SMPR1_SMP5_0                          (0x1UL<<ADC_SMPR1_SMP5_Pos)                       /*!< 0x00008000 */
#define ADC_SMPR1_SMP5_1                          (0x2UL<<ADC_SMPR1_SMP5_Pos)                       /*!< 0x00010000 */
#define ADC_SMPR1_SMP5_2                          (0x4UL<<ADC_SMPR1_SMP5_Pos)                       /*!< 0x00020000 */
#define ADC_SMPR1_SMP6_Pos                        (18U)
#define ADC_SMPR1_SMP6_Msk                        (0x7UL<<ADC_SMPR1_SMP6_Pos)                       /*!< 0x001C0000 */
#define ADC_SMPR1_SMP6                            ADC_SMPR1_SMP6_Msk
#define ADC_SMPR1_SMP6_0                          (0x1UL<<ADC_SMPR1_SMP6_Pos)                       /*!< 0x00040000 */
#define ADC_SMPR1_SMP6_1                          (0x2UL<<ADC_SMPR1_SMP6_Pos)                       /*!< 0x00080000 */
#define ADC_SMPR1_SMP6_2                          (0x4UL<<ADC_SMPR1_SMP6_Pos)                       /*!< 0x00100000 */
#define ADC_SMPR1_SMP7_Pos                        (21U)
#define ADC_SMPR1_SMP7_Msk                        (0x7UL<<ADC_SMPR1_SMP7_Pos)                       /*!< 0x00E00000 */
#define ADC_SMPR1_SMP7                            ADC_SMPR1_SMP7_Msk
#define ADC_SMPR1_SMP7_0                          (0x1UL<<ADC_SMPR1_SMP7_Pos)                       /*!< 0x00200000 */
#define ADC_SMPR1_SMP7_1                          (0x2UL<<ADC_SMPR1_SMP7_Pos)                       /*!< 0x00400000 */
#define ADC_SMPR1_SMP7_2                          (0x4UL<<ADC_SMPR1_SMP7_Pos)                       /*!< 0x00800000 */
#define ADC_SMPR1_SMP8_Pos                        (24U)
#define ADC_SMPR1_SMP8_Msk                        (0x7UL<<ADC_SMPR1_SMP8_Pos)                       /*!< 0x07000000 */
#define ADC_SMPR1_SMP8                            ADC_SMPR1_SMP8_Msk
#define ADC_SMPR1_SMP8_0                          (0x1UL<<ADC_SMPR1_SMP8_Pos)                       /*!< 0x01000000 */
#define ADC_SMPR1_SMP8_1                          (0x2UL<<ADC_SMPR1_SMP8_Pos)                       /*!< 0x02000000 */
#define ADC_SMPR1_SMP8_2                          (0x4UL<<ADC_SMPR1_SMP8_Pos)                       /*!< 0x04000000 */
#define ADC_SMPR1_SMP9_Pos                        (27U)
#define ADC_SMPR1_SMP9_Msk                        (0x7UL<<ADC_SMPR1_SMP9_Pos)                       /*!< 0x38000000 */
#define ADC_SMPR1_SMP9                            ADC_SMPR1_SMP9_Msk
#define ADC_SMPR1_SMP9_0                          (0x1UL<<ADC_SMPR1_SMP9_Pos)                       /*!< 0x08000000 */
#define ADC_SMPR1_SMP9_1                          (0x2UL<<ADC_SMPR1_SMP9_Pos)                       /*!< 0x10000000 */
#define ADC_SMPR1_SMP9_2                          (0x4UL<<ADC_SMPR1_SMP9_Pos)                       /*!< 0x20000000 */

/********************************* Bit definition for ADC_SMPR2 register ********************************************/
#define ADC_SMPR2_SMP10_Pos                       (0U)
#define ADC_SMPR2_SMP10_Msk                       (0x7UL<<ADC_SMPR2_SMP10_Pos)                      /*!< 0x00000007 */
#define ADC_SMPR2_SMP10                           ADC_SMPR2_SMP10_Msk
#define ADC_SMPR2_SMP10_0                         (0x1UL<<ADC_SMPR2_SMP10_Pos)                      /*!< 0x00000001 */
#define ADC_SMPR2_SMP10_1                         (0x2UL<<ADC_SMPR2_SMP10_Pos)                      /*!< 0x00000002 */
#define ADC_SMPR2_SMP10_2                         (0x4UL<<ADC_SMPR2_SMP10_Pos)                      /*!< 0x00000004 */
#define ADC_SMPR2_SMP11_Pos                       (3U)
#define ADC_SMPR2_SMP11_Msk                       (0x7UL<<ADC_SMPR2_SMP11_Pos)                      /*!< 0x00000038 */
#define ADC_SMPR2_SMP11                           ADC_SMPR2_SMP11_Msk
#define ADC_SMPR2_SMP11_0                         (0x1UL<<ADC_SMPR2_SMP11_Pos)                      /*!< 0x00000008 */
#define ADC_SMPR2_SMP11_1                         (0x2UL<<ADC_SMPR2_SMP11_Pos)                      /*!< 0x00000010 */
#define ADC_SMPR2_SMP11_2                         (0x4UL<<ADC_SMPR2_SMP11_Pos)                      /*!< 0x00000020 */
#define ADC_SMPR2_SMP12_Pos                       (6U)
#define ADC_SMPR2_SMP12_Msk                       (0x7UL<<ADC_SMPR2_SMP12_Pos)                      /*!< 0x000001C0 */
#define ADC_SMPR2_SMP12                           ADC_SMPR2_SMP12_Msk
#define ADC_SMPR2_SMP12_0                         (0x1UL<<ADC_SMPR2_SMP12_Pos)                      /*!< 0x00000040 */
#define ADC_SMPR2_SMP12_1                         (0x2UL<<ADC_SMPR2_SMP12_Pos)                      /*!< 0x00000080 */
#define ADC_SMPR2_SMP12_2                         (0x4UL<<ADC_SMPR2_SMP12_Pos)                      /*!< 0x00000100 */
#define ADC_SMPR2_SMP13_Pos                       (9U)
#define ADC_SMPR2_SMP13_Msk                       (0x7UL<<ADC_SMPR2_SMP13_Pos)                      /*!< 0x00000E00 */
#define ADC_SMPR2_SMP13                           ADC_SMPR2_SMP13_Msk
#define ADC_SMPR2_SMP13_0                         (0x1UL<<ADC_SMPR2_SMP13_Pos)                      /*!< 0x00000200 */
#define ADC_SMPR2_SMP13_1                         (0x2UL<<ADC_SMPR2_SMP13_Pos)                      /*!< 0x00000400 */
#define ADC_SMPR2_SMP13_2                         (0x4UL<<ADC_SMPR2_SMP13_Pos)                      /*!< 0x00000800 */
#define ADC_SMPR2_SMP14_Pos                       (12U)
#define ADC_SMPR2_SMP14_Msk                       (0x7UL<<ADC_SMPR2_SMP14_Pos)                      /*!< 0x00007000 */
#define ADC_SMPR2_SMP14                           ADC_SMPR2_SMP14_Msk
#define ADC_SMPR2_SMP14_0                         (0x1UL<<ADC_SMPR2_SMP14_Pos)                      /*!< 0x00001000 */
#define ADC_SMPR2_SMP14_1                         (0x2UL<<ADC_SMPR2_SMP14_Pos)                      /*!< 0x00002000 */
#define ADC_SMPR2_SMP14_2                         (0x4UL<<ADC_SMPR2_SMP14_Pos)                      /*!< 0x00004000 */
#define ADC_SMPR2_SMP15_Pos                       (15U)
#define ADC_SMPR2_SMP15_Msk                       (0x7UL<<ADC_SMPR2_SMP15_Pos)                      /*!< 0x00038000 */
#define ADC_SMPR2_SMP15                           ADC_SMPR2_SMP15_Msk
#define ADC_SMPR2_SMP15_0                         (0x1UL<<ADC_SMPR2_SMP15_Pos)                      /*!< 0x00008000 */
#define ADC_SMPR2_SMP15_1                         (0x2UL<<ADC_SMPR2_SMP15_Pos)                      /*!< 0x00010000 */
#define ADC_SMPR2_SMP15_2                         (0x4UL<<ADC_SMPR2_SMP15_Pos)                      /*!< 0x00020000 */
#define ADC_SMPR2_SMP16_Pos                       (18U)
#define ADC_SMPR2_SMP16_Msk                       (0x7UL<<ADC_SMPR2_SMP16_Pos)                      /*!< 0x001C0000 */
#define ADC_SMPR2_SMP16                           ADC_SMPR2_SMP16_Msk
#define ADC_SMPR2_SMP16_0                         (0x1UL<<ADC_SMPR2_SMP16_Pos)                      /*!< 0x00040000 */
#define ADC_SMPR2_SMP16_1                         (0x2UL<<ADC_SMPR2_SMP16_Pos)                      /*!< 0x00080000 */
#define ADC_SMPR2_SMP16_2                         (0x4UL<<ADC_SMPR2_SMP16_Pos)                      /*!< 0x00100000 */
#define ADC_SMPR2_SMP17_Pos                       (21U)
#define ADC_SMPR2_SMP17_Msk                       (0x7UL<<ADC_SMPR2_SMP17_Pos)                      /*!< 0x00E00000 */
#define ADC_SMPR2_SMP17                           ADC_SMPR2_SMP17_Msk
#define ADC_SMPR2_SMP17_0                         (0x1UL<<ADC_SMPR2_SMP17_Pos)                      /*!< 0x00200000 */
#define ADC_SMPR2_SMP17_1                         (0x2UL<<ADC_SMPR2_SMP17_Pos)                      /*!< 0x00400000 */
#define ADC_SMPR2_SMP17_2                         (0x4UL<<ADC_SMPR2_SMP17_Pos)                      /*!< 0x00800000 */
#define ADC_SMPR2_SMP18_Pos                       (24U)
#define ADC_SMPR2_SMP18_Msk                       (0x7UL<<ADC_SMPR2_SMP18_Pos)                      /*!< 0x07000000 */
#define ADC_SMPR2_SMP18                           ADC_SMPR2_SMP18_Msk
#define ADC_SMPR2_SMP18_0                         (0x1UL<<ADC_SMPR2_SMP18_Pos)                      /*!< 0x01000000 */
#define ADC_SMPR2_SMP18_1                         (0x2UL<<ADC_SMPR2_SMP18_Pos)                      /*!< 0x02000000 */
#define ADC_SMPR2_SMP18_2                         (0x4UL<<ADC_SMPR2_SMP18_Pos)                      /*!< 0x04000000 */
#define ADC_SMPR2_SMP19_Pos                       (27U)
#define ADC_SMPR2_SMP19_Msk                       (0x7UL<<ADC_SMPR2_SMP19_Pos)                      /*!< 0x38000000 */
#define ADC_SMPR2_SMP19                           ADC_SMPR2_SMP19_Msk
#define ADC_SMPR2_SMP19_0                         (0x1UL<<ADC_SMPR2_SMP19_Pos)                      /*!< 0x08000000 */
#define ADC_SMPR2_SMP19_1                         (0x2UL<<ADC_SMPR2_SMP19_Pos)                      /*!< 0x10000000 */
#define ADC_SMPR2_SMP19_2                         (0x4UL<<ADC_SMPR2_SMP19_Pos)                      /*!< 0x20000000 */

/********************************* Bit definition for ADC_SMPR3 register ********************************************/
#define ADC_SMPR3_SMP20_Pos                       (0U)
#define ADC_SMPR3_SMP20_Msk                       (0x7UL<<ADC_SMPR3_SMP20_Pos)                      /*!< 0x00000007 */
#define ADC_SMPR3_SMP20                           ADC_SMPR3_SMP20_Msk
#define ADC_SMPR3_SMP20_0                         (0x1UL<<ADC_SMPR3_SMP20_Pos)                      /*!< 0x00000001 */
#define ADC_SMPR3_SMP20_1                         (0x2UL<<ADC_SMPR3_SMP20_Pos)                      /*!< 0x00000002 */
#define ADC_SMPR3_SMP20_2                         (0x4UL<<ADC_SMPR3_SMP20_Pos)                      /*!< 0x00000004 */
#define ADC_SMPR3_SMP21_Pos                       (3U)
#define ADC_SMPR3_SMP21_Msk                       (0x7UL<<ADC_SMPR3_SMP21_Pos)                      /*!< 0x00000038 */
#define ADC_SMPR3_SMP21                           ADC_SMPR3_SMP21_Msk
#define ADC_SMPR3_SMP21_0                         (0x1UL<<ADC_SMPR3_SMP21_Pos)                      /*!< 0x00000008 */
#define ADC_SMPR3_SMP21_1                         (0x2UL<<ADC_SMPR3_SMP21_Pos)                      /*!< 0x00000010 */
#define ADC_SMPR3_SMP21_2                         (0x4UL<<ADC_SMPR3_SMP21_Pos)                      /*!< 0x00000020 */

/********************************* Bit definition for ADC_TR1 register **********************************************/
#define ADC_TR1_LT1_Pos                           (0U)
#define ADC_TR1_LT1_Msk                           (0xFFFUL<<ADC_TR1_LT1_Pos)                        /*!< 0x00000FFF */
#define ADC_TR1_LT1                               ADC_TR1_LT1_Msk
#define ADC_TR1_AWDFILT_Pos                       (12U)
#define ADC_TR1_AWDFILT_Msk                       (0x7UL<<ADC_TR1_AWDFILT_Pos)                      /*!< 0x00007000 */
#define ADC_TR1_AWDFILT                           ADC_TR1_AWDFILT_Msk
#define ADC_TR1_AWDFILT_0                         (0x1UL<<ADC_TR1_AWDFILT_Pos)                      /*!< 0x00001000 */
#define ADC_TR1_AWDFILT_1                         (0x2UL<<ADC_TR1_AWDFILT_Pos)                      /*!< 0x00002000 */
#define ADC_TR1_AWDFILT_2                         (0x4UL<<ADC_TR1_AWDFILT_Pos)                      /*!< 0x00004000 */
#define ADC_TR1_HT1_Pos                           (16U)
#define ADC_TR1_HT1_Msk                           (0xFFFUL<<ADC_TR1_HT1_Pos)                        /*!< 0x0FFF0000 */
#define ADC_TR1_HT1                               ADC_TR1_HT1_Msk

/********************************* Bit definition for ADC_TR2 register **********************************************/
#define ADC_TR2_LT2_Pos                           (0U)
#define ADC_TR2_LT2_Msk                           (0xFFUL<<ADC_TR2_LT2_Pos)                         /*!< 0x000000FF */
#define ADC_TR2_LT2                               ADC_TR2_LT2_Msk
#define ADC_TR2_HT2_Pos                           (16U)
#define ADC_TR2_HT2_Msk                           (0xFFUL<<ADC_TR2_HT2_Pos)                         /*!< 0x00FF0000 */
#define ADC_TR2_HT2                               ADC_TR2_HT2_Msk

/********************************* Bit definition for ADC_TR3 register **********************************************/
#define ADC_TR3_LT3_Pos                           (0U)
#define ADC_TR3_LT3_Msk                           (0xFFUL<<ADC_TR3_LT3_Pos)                         /*!< 0x000000FF */
#define ADC_TR3_LT3                               ADC_TR3_LT3_Msk
#define ADC_TR3_HT3_Pos                           (16U)
#define ADC_TR3_HT3_Msk                           (0xFFUL<<ADC_TR3_HT3_Pos)                         /*!< 0x00FF0000 */
#define ADC_TR3_HT3                               ADC_TR3_HT3_Msk

/********************************* Bit definition for ADC_SQR1 register *********************************************/
#define ADC_SQR1_L_Pos                            (0U)
#define ADC_SQR1_L_Msk                            (0xFUL<<ADC_SQR1_L_Pos)                           /*!< 0x0000000F */
#define ADC_SQR1_L                                ADC_SQR1_L_Msk
#define ADC_SQR1_L_0                              (0x1UL<<ADC_SQR1_L_Pos)                           /*!< 0x00000001 */
#define ADC_SQR1_L_1                              (0x2UL<<ADC_SQR1_L_Pos)                           /*!< 0x00000002 */
#define ADC_SQR1_L_2                              (0x4UL<<ADC_SQR1_L_Pos)                           /*!< 0x00000004 */
#define ADC_SQR1_L_3                              (0x8UL<<ADC_SQR1_L_Pos)                           /*!< 0x00000008 */
#define ADC_SQR1_SQ1_Pos                          (6U)
#define ADC_SQR1_SQ1_Msk                          (0x1FUL<<ADC_SQR1_SQ1_Pos)                        /*!< 0x000007C0 */
#define ADC_SQR1_SQ1                              ADC_SQR1_SQ1_Msk
#define ADC_SQR1_SQ1_0                            (0x1UL<<ADC_SQR1_SQ1_Pos)                         /*!< 0x00000040 */
#define ADC_SQR1_SQ1_1                            (0x2UL<<ADC_SQR1_SQ1_Pos)                         /*!< 0x00000080 */
#define ADC_SQR1_SQ1_2                            (0x4UL<<ADC_SQR1_SQ1_Pos)                         /*!< 0x00000100 */
#define ADC_SQR1_SQ1_3                            (0x8UL<<ADC_SQR1_SQ1_Pos)                         /*!< 0x00000200 */
#define ADC_SQR1_SQ1_4                            (0x10UL<<ADC_SQR1_SQ1_Pos)                        /*!< 0x00000400 */
#define ADC_SQR1_SQ2_Pos                          (12U)
#define ADC_SQR1_SQ2_Msk                          (0x1FUL<<ADC_SQR1_SQ2_Pos)                        /*!< 0x0001F000 */
#define ADC_SQR1_SQ2                              ADC_SQR1_SQ2_Msk
#define ADC_SQR1_SQ2_0                            (0x1UL<<ADC_SQR1_SQ2_Pos)                         /*!< 0x00001000 */
#define ADC_SQR1_SQ2_1                            (0x2UL<<ADC_SQR1_SQ2_Pos)                         /*!< 0x00002000 */
#define ADC_SQR1_SQ2_2                            (0x4UL<<ADC_SQR1_SQ2_Pos)                         /*!< 0x00004000 */
#define ADC_SQR1_SQ2_3                            (0x8UL<<ADC_SQR1_SQ2_Pos)                         /*!< 0x00008000 */
#define ADC_SQR1_SQ2_4                            (0x10UL<<ADC_SQR1_SQ2_Pos)                        /*!< 0x00010000 */
#define ADC_SQR1_SQ3_Pos                          (18U)
#define ADC_SQR1_SQ3_Msk                          (0x1FUL<<ADC_SQR1_SQ3_Pos)                        /*!< 0x007C0000 */
#define ADC_SQR1_SQ3                              ADC_SQR1_SQ3_Msk
#define ADC_SQR1_SQ3_0                            (0x1UL<<ADC_SQR1_SQ3_Pos)                         /*!< 0x00040000 */
#define ADC_SQR1_SQ3_1                            (0x2UL<<ADC_SQR1_SQ3_Pos)                         /*!< 0x00080000 */
#define ADC_SQR1_SQ3_2                            (0x4UL<<ADC_SQR1_SQ3_Pos)                         /*!< 0x00100000 */
#define ADC_SQR1_SQ3_3                            (0x8UL<<ADC_SQR1_SQ3_Pos)                         /*!< 0x00200000 */
#define ADC_SQR1_SQ3_4                            (0x10UL<<ADC_SQR1_SQ3_Pos)                        /*!< 0x00400000 */
#define ADC_SQR1_SQ4_Pos                          (24U)
#define ADC_SQR1_SQ4_Msk                          (0x1FUL<<ADC_SQR1_SQ4_Pos)                        /*!< 0x1F000000 */
#define ADC_SQR1_SQ4                              ADC_SQR1_SQ4_Msk
#define ADC_SQR1_SQ4_0                            (0x1UL<<ADC_SQR1_SQ4_Pos)                         /*!< 0x01000000 */
#define ADC_SQR1_SQ4_1                            (0x2UL<<ADC_SQR1_SQ4_Pos)                         /*!< 0x02000000 */
#define ADC_SQR1_SQ4_2                            (0x4UL<<ADC_SQR1_SQ4_Pos)                         /*!< 0x04000000 */
#define ADC_SQR1_SQ4_3                            (0x8UL<<ADC_SQR1_SQ4_Pos)                         /*!< 0x08000000 */
#define ADC_SQR1_SQ4_4                            (0x10UL<<ADC_SQR1_SQ4_Pos)                        /*!< 0x10000000 */

/********************************* Bit definition for ADC_SQR2 register *********************************************/
#define ADC_SQR2_SQ5_Pos                          (0U)
#define ADC_SQR2_SQ5_Msk                          (0x1FUL<<ADC_SQR2_SQ5_Pos)                        /*!< 0x0000001F */
#define ADC_SQR2_SQ5                              ADC_SQR2_SQ5_Msk
#define ADC_SQR2_SQ5_0                            (0x1UL<<ADC_SQR2_SQ5_Pos)                         /*!< 0x00000001 */
#define ADC_SQR2_SQ5_1                            (0x2UL<<ADC_SQR2_SQ5_Pos)                         /*!< 0x00000002 */
#define ADC_SQR2_SQ5_2                            (0x4UL<<ADC_SQR2_SQ5_Pos)                         /*!< 0x00000004 */
#define ADC_SQR2_SQ5_3                            (0x8UL<<ADC_SQR2_SQ5_Pos)                         /*!< 0x00000008 */
#define ADC_SQR2_SQ5_4                            (0x10UL<<ADC_SQR2_SQ5_Pos)                        /*!< 0x00000010 */
#define ADC_SQR2_SQ6_Pos                          (6U)
#define ADC_SQR2_SQ6_Msk                          (0x1FUL<<ADC_SQR2_SQ6_Pos)                        /*!< 0x000007C0 */
#define ADC_SQR2_SQ6                              ADC_SQR2_SQ6_Msk
#define ADC_SQR2_SQ6_0                            (0x1UL<<ADC_SQR2_SQ6_Pos)                         /*!< 0x00000040 */
#define ADC_SQR2_SQ6_1                            (0x2UL<<ADC_SQR2_SQ6_Pos)                         /*!< 0x00000080 */
#define ADC_SQR2_SQ6_2                            (0x4UL<<ADC_SQR2_SQ6_Pos)                         /*!< 0x00000100 */
#define ADC_SQR2_SQ6_3                            (0x8UL<<ADC_SQR2_SQ6_Pos)                         /*!< 0x00000200 */
#define ADC_SQR2_SQ6_4                            (0x10UL<<ADC_SQR2_SQ6_Pos)                        /*!< 0x00000400 */
#define ADC_SQR2_SQ7_Pos                          (12U)
#define ADC_SQR2_SQ7_Msk                          (0x1FUL<<ADC_SQR2_SQ7_Pos)                        /*!< 0x0001F000 */
#define ADC_SQR2_SQ7                              ADC_SQR2_SQ7_Msk
#define ADC_SQR2_SQ7_0                            (0x1UL<<ADC_SQR2_SQ7_Pos)                         /*!< 0x00001000 */
#define ADC_SQR2_SQ7_1                            (0x2UL<<ADC_SQR2_SQ7_Pos)                         /*!< 0x00002000 */
#define ADC_SQR2_SQ7_2                            (0x4UL<<ADC_SQR2_SQ7_Pos)                         /*!< 0x00004000 */
#define ADC_SQR2_SQ7_3                            (0x8UL<<ADC_SQR2_SQ7_Pos)                         /*!< 0x00008000 */
#define ADC_SQR2_SQ7_4                            (0x10UL<<ADC_SQR2_SQ7_Pos)                        /*!< 0x00010000 */
#define ADC_SQR2_SQ8_Pos                          (18U)
#define ADC_SQR2_SQ8_Msk                          (0x1FUL<<ADC_SQR2_SQ8_Pos)                        /*!< 0x007C0000 */
#define ADC_SQR2_SQ8                              ADC_SQR2_SQ8_Msk
#define ADC_SQR2_SQ8_0                            (0x1UL<<ADC_SQR2_SQ8_Pos)                         /*!< 0x00040000 */
#define ADC_SQR2_SQ8_1                            (0x2UL<<ADC_SQR2_SQ8_Pos)                         /*!< 0x00080000 */
#define ADC_SQR2_SQ8_2                            (0x4UL<<ADC_SQR2_SQ8_Pos)                         /*!< 0x00100000 */
#define ADC_SQR2_SQ8_3                            (0x8UL<<ADC_SQR2_SQ8_Pos)                         /*!< 0x00200000 */
#define ADC_SQR2_SQ8_4                            (0x10UL<<ADC_SQR2_SQ8_Pos)                        /*!< 0x00400000 */
#define ADC_SQR2_SQ9_Pos                          (24U)
#define ADC_SQR2_SQ9_Msk                          (0x1FUL<<ADC_SQR2_SQ9_Pos)                        /*!< 0x1F000000 */
#define ADC_SQR2_SQ9                              ADC_SQR2_SQ9_Msk
#define ADC_SQR2_SQ9_0                            (0x1UL<<ADC_SQR2_SQ9_Pos)                         /*!< 0x01000000 */
#define ADC_SQR2_SQ9_1                            (0x2UL<<ADC_SQR2_SQ9_Pos)                         /*!< 0x02000000 */
#define ADC_SQR2_SQ9_2                            (0x4UL<<ADC_SQR2_SQ9_Pos)                         /*!< 0x04000000 */
#define ADC_SQR2_SQ9_3                            (0x8UL<<ADC_SQR2_SQ9_Pos)                         /*!< 0x08000000 */
#define ADC_SQR2_SQ9_4                            (0x10UL<<ADC_SQR2_SQ9_Pos)                        /*!< 0x10000000 */

/********************************* Bit definition for ADC_SQR3 register *********************************************/
#define ADC_SQR3_SQ10_Pos                         (0U)
#define ADC_SQR3_SQ10_Msk                         (0x1FUL<<ADC_SQR3_SQ10_Pos)                       /*!< 0x0000001F */
#define ADC_SQR3_SQ10                             ADC_SQR3_SQ10_Msk
#define ADC_SQR3_SQ10_0                           (0x1UL<<ADC_SQR3_SQ10_Pos)                        /*!< 0x00000001 */
#define ADC_SQR3_SQ10_1                           (0x2UL<<ADC_SQR3_SQ10_Pos)                        /*!< 0x00000002 */
#define ADC_SQR3_SQ10_2                           (0x4UL<<ADC_SQR3_SQ10_Pos)                        /*!< 0x00000004 */
#define ADC_SQR3_SQ10_3                           (0x8UL<<ADC_SQR3_SQ10_Pos)                        /*!< 0x00000008 */
#define ADC_SQR3_SQ10_4                           (0x10UL<<ADC_SQR3_SQ10_Pos)                       /*!< 0x00000010 */
#define ADC_SQR3_SQ11_Pos                         (6U)
#define ADC_SQR3_SQ11_Msk                         (0x1FUL<<ADC_SQR3_SQ11_Pos)                       /*!< 0x000007C0 */
#define ADC_SQR3_SQ11                             ADC_SQR3_SQ11_Msk
#define ADC_SQR3_SQ11_0                           (0x1UL<<ADC_SQR3_SQ11_Pos)                        /*!< 0x00000040 */
#define ADC_SQR3_SQ11_1                           (0x2UL<<ADC_SQR3_SQ11_Pos)                        /*!< 0x00000080 */
#define ADC_SQR3_SQ11_2                           (0x4UL<<ADC_SQR3_SQ11_Pos)                        /*!< 0x00000100 */
#define ADC_SQR3_SQ11_3                           (0x8UL<<ADC_SQR3_SQ11_Pos)                        /*!< 0x00000200 */
#define ADC_SQR3_SQ11_4                           (0x10UL<<ADC_SQR3_SQ11_Pos)                       /*!< 0x00000400 */
#define ADC_SQR3_SQ12_Pos                         (12U)
#define ADC_SQR3_SQ12_Msk                         (0x1FUL<<ADC_SQR3_SQ12_Pos)                       /*!< 0x0001F000 */
#define ADC_SQR3_SQ12                             ADC_SQR3_SQ12_Msk
#define ADC_SQR3_SQ12_0                           (0x1UL<<ADC_SQR3_SQ12_Pos)                        /*!< 0x00001000 */
#define ADC_SQR3_SQ12_1                           (0x2UL<<ADC_SQR3_SQ12_Pos)                        /*!< 0x00002000 */
#define ADC_SQR3_SQ12_2                           (0x4UL<<ADC_SQR3_SQ12_Pos)                        /*!< 0x00004000 */
#define ADC_SQR3_SQ12_3                           (0x8UL<<ADC_SQR3_SQ12_Pos)                        /*!< 0x00008000 */
#define ADC_SQR3_SQ12_4                           (0x10UL<<ADC_SQR3_SQ12_Pos)                       /*!< 0x00010000 */
#define ADC_SQR3_SQ13_Pos                         (18U)
#define ADC_SQR3_SQ13_Msk                         (0x1FUL<<ADC_SQR3_SQ13_Pos)                       /*!< 0x007C0000 */
#define ADC_SQR3_SQ13                             ADC_SQR3_SQ13_Msk
#define ADC_SQR3_SQ13_0                           (0x1UL<<ADC_SQR3_SQ13_Pos)                        /*!< 0x00040000 */
#define ADC_SQR3_SQ13_1                           (0x2UL<<ADC_SQR3_SQ13_Pos)                        /*!< 0x00080000 */
#define ADC_SQR3_SQ13_2                           (0x4UL<<ADC_SQR3_SQ13_Pos)                        /*!< 0x00100000 */
#define ADC_SQR3_SQ13_3                           (0x8UL<<ADC_SQR3_SQ13_Pos)                        /*!< 0x00200000 */
#define ADC_SQR3_SQ13_4                           (0x10UL<<ADC_SQR3_SQ13_Pos)                       /*!< 0x00400000 */
#define ADC_SQR3_SQ14_Pos                         (24U)
#define ADC_SQR3_SQ14_Msk                         (0x1FUL<<ADC_SQR3_SQ14_Pos)                       /*!< 0x1F000000 */
#define ADC_SQR3_SQ14                             ADC_SQR3_SQ14_Msk
#define ADC_SQR3_SQ14_0                           (0x1UL<<ADC_SQR3_SQ14_Pos)                        /*!< 0x01000000 */
#define ADC_SQR3_SQ14_1                           (0x2UL<<ADC_SQR3_SQ14_Pos)                        /*!< 0x02000000 */
#define ADC_SQR3_SQ14_2                           (0x4UL<<ADC_SQR3_SQ14_Pos)                        /*!< 0x04000000 */
#define ADC_SQR3_SQ14_3                           (0x8UL<<ADC_SQR3_SQ14_Pos)                        /*!< 0x08000000 */
#define ADC_SQR3_SQ14_4                           (0x10UL<<ADC_SQR3_SQ14_Pos)                       /*!< 0x10000000 */

/********************************* Bit definition for ADC_SQR4 register *********************************************/
#define ADC_SQR4_SQ15_Pos                         (0U)
#define ADC_SQR4_SQ15_Msk                         (0x1FUL<<ADC_SQR4_SQ15_Pos)                       /*!< 0x0000001F */
#define ADC_SQR4_SQ15                             ADC_SQR4_SQ15_Msk
#define ADC_SQR4_SQ15_0                           (0x1UL<<ADC_SQR4_SQ15_Pos)                        /*!< 0x00000001 */
#define ADC_SQR4_SQ15_1                           (0x2UL<<ADC_SQR4_SQ15_Pos)                        /*!< 0x00000002 */
#define ADC_SQR4_SQ15_2                           (0x4UL<<ADC_SQR4_SQ15_Pos)                        /*!< 0x00000004 */
#define ADC_SQR4_SQ15_3                           (0x8UL<<ADC_SQR4_SQ15_Pos)                        /*!< 0x00000008 */
#define ADC_SQR4_SQ15_4                           (0x10UL<<ADC_SQR4_SQ15_Pos)                       /*!< 0x00000010 */
#define ADC_SQR4_SQ16_Pos                         (6U)
#define ADC_SQR4_SQ16_Msk                         (0x1FUL<<ADC_SQR4_SQ16_Pos)                       /*!< 0x000007C0 */
#define ADC_SQR4_SQ16                             ADC_SQR4_SQ16_Msk
#define ADC_SQR4_SQ16_0                           (0x1UL<<ADC_SQR4_SQ16_Pos)                        /*!< 0x00000040 */
#define ADC_SQR4_SQ16_1                           (0x2UL<<ADC_SQR4_SQ16_Pos)                        /*!< 0x00000080 */
#define ADC_SQR4_SQ16_2                           (0x4UL<<ADC_SQR4_SQ16_Pos)                        /*!< 0x00000100 */
#define ADC_SQR4_SQ16_3                           (0x8UL<<ADC_SQR4_SQ16_Pos)                        /*!< 0x00000200 */
#define ADC_SQR4_SQ16_4                           (0x10UL<<ADC_SQR4_SQ16_Pos)                       /*!< 0x00000400 */

/********************************* Bit definition for ADC_DR register ***********************************************/
#define ADC_DR_RDATA_Pos                          (0U)
#define ADC_DR_RDATA_Msk                          (0xFFFFUL<<ADC_DR_RDATA_Pos)                      /*!< 0x0000FFFF */
#define ADC_DR_RDATA                              ADC_DR_RDATA_Msk

/********************************* Bit definition for ADC_JSQR register *********************************************/
#define ADC_JSQR_JL_Pos                           (0U)
#define ADC_JSQR_JL_Msk                           (0x3UL<<ADC_JSQR_JL_Pos)                          /*!< 0x00000003 */
#define ADC_JSQR_JL                               ADC_JSQR_JL_Msk
#define ADC_JSQR_JL_0                             (0x1UL<<ADC_JSQR_JL_Pos)                          /*!< 0x00000001 */
#define ADC_JSQR_JL_1                             (0x2UL<<ADC_JSQR_JL_Pos)                          /*!< 0x00000002 */
#define ADC_JSQR_JEXTSEL_Pos                      (2U)
#define ADC_JSQR_JEXTSEL_Msk                      (0x1FUL<<ADC_JSQR_JEXTSEL_Pos)                    /*!< 0x0000007C */
#define ADC_JSQR_JEXTSEL                          ADC_JSQR_JEXTSEL_Msk
#define ADC_JSQR_JEXTSEL_0                        (0x1UL<<ADC_JSQR_JEXTSEL_Pos)                     /*!< 0x00000004 */
#define ADC_JSQR_JEXTSEL_1                        (0x2UL<<ADC_JSQR_JEXTSEL_Pos)                     /*!< 0x00000008 */
#define ADC_JSQR_JEXTSEL_2                        (0x4UL<<ADC_JSQR_JEXTSEL_Pos)                     /*!< 0x00000010 */
#define ADC_JSQR_JEXTSEL_3                        (0x8UL<<ADC_JSQR_JEXTSEL_Pos)                     /*!< 0x00000020 */
#define ADC_JSQR_JEXTSEL_4                        (0x10UL<<ADC_JSQR_JEXTSEL_Pos)                    /*!< 0x00000040 */
#define ADC_JSQR_JEXTEN_Pos                       (7U)
#define ADC_JSQR_JEXTEN_Msk                       (0x3UL<<ADC_JSQR_JEXTEN_Pos)                      /*!< 0x00000180 */
#define ADC_JSQR_JEXTEN                           ADC_JSQR_JEXTEN_Msk
#define ADC_JSQR_JEXTEN_0                         (0x1UL<<ADC_JSQR_JEXTEN_Pos)                      /*!< 0x00000080 */
#define ADC_JSQR_JEXTEN_1                         (0x2UL<<ADC_JSQR_JEXTEN_Pos)                      /*!< 0x00000100 */
#define ADC_JSQR_JSQ1_Pos                         (9U)
#define ADC_JSQR_JSQ1_Msk                         (0x1FUL<<ADC_JSQR_JSQ1_Pos)                       /*!< 0x00003E00 */
#define ADC_JSQR_JSQ1                             ADC_JSQR_JSQ1_Msk
#define ADC_JSQR_JSQ1_0                           (0x1UL<<ADC_JSQR_JSQ1_Pos)                        /*!< 0x00000200 */
#define ADC_JSQR_JSQ1_1                           (0x2UL<<ADC_JSQR_JSQ1_Pos)                        /*!< 0x00000400 */
#define ADC_JSQR_JSQ1_2                           (0x4UL<<ADC_JSQR_JSQ1_Pos)                        /*!< 0x00000800 */
#define ADC_JSQR_JSQ1_3                           (0x8UL<<ADC_JSQR_JSQ1_Pos)                        /*!< 0x00001000 */
#define ADC_JSQR_JSQ1_4                           (0x10UL<<ADC_JSQR_JSQ1_Pos)                       /*!< 0x00002000 */
#define ADC_JSQR_JSQ2_Pos                         (15U)
#define ADC_JSQR_JSQ2_Msk                         (0x1FUL<<ADC_JSQR_JSQ2_Pos)                       /*!< 0x000F8000 */
#define ADC_JSQR_JSQ2                             ADC_JSQR_JSQ2_Msk
#define ADC_JSQR_JSQ2_0                           (0x1UL<<ADC_JSQR_JSQ2_Pos)                        /*!< 0x00008000 */
#define ADC_JSQR_JSQ2_1                           (0x2UL<<ADC_JSQR_JSQ2_Pos)                        /*!< 0x00010000 */
#define ADC_JSQR_JSQ2_2                           (0x4UL<<ADC_JSQR_JSQ2_Pos)                        /*!< 0x00020000 */
#define ADC_JSQR_JSQ2_3                           (0x8UL<<ADC_JSQR_JSQ2_Pos)                        /*!< 0x00040000 */
#define ADC_JSQR_JSQ2_4                           (0x10UL<<ADC_JSQR_JSQ2_Pos)                       /*!< 0x00080000 */
#define ADC_JSQR_JSQ3_Pos                         (21U)
#define ADC_JSQR_JSQ3_Msk                         (0x1FUL<<ADC_JSQR_JSQ3_Pos)                       /*!< 0x03E00000 */
#define ADC_JSQR_JSQ3                             ADC_JSQR_JSQ3_Msk
#define ADC_JSQR_JSQ3_0                           (0x1UL<<ADC_JSQR_JSQ3_Pos)                        /*!< 0x00200000 */
#define ADC_JSQR_JSQ3_1                           (0x2UL<<ADC_JSQR_JSQ3_Pos)                        /*!< 0x00400000 */
#define ADC_JSQR_JSQ3_2                           (0x4UL<<ADC_JSQR_JSQ3_Pos)                        /*!< 0x00800000 */
#define ADC_JSQR_JSQ3_3                           (0x8UL<<ADC_JSQR_JSQ3_Pos)                        /*!< 0x01000000 */
#define ADC_JSQR_JSQ3_4                           (0x10UL<<ADC_JSQR_JSQ3_Pos)                       /*!< 0x02000000 */
#define ADC_JSQR_JSQ4_Pos                         (27U)
#define ADC_JSQR_JSQ4_Msk                         (0x1FUL<<ADC_JSQR_JSQ4_Pos)                       /*!< 0xF8000000 */
#define ADC_JSQR_JSQ4                             ADC_JSQR_JSQ4_Msk
#define ADC_JSQR_JSQ4_0                           (0x1UL<<ADC_JSQR_JSQ4_Pos)                        /*!< 0x08000000 */
#define ADC_JSQR_JSQ4_1                           (0x2UL<<ADC_JSQR_JSQ4_Pos)                        /*!< 0x10000000 */
#define ADC_JSQR_JSQ4_2                           (0x4UL<<ADC_JSQR_JSQ4_Pos)                        /*!< 0x20000000 */
#define ADC_JSQR_JSQ4_3                           (0x8UL<<ADC_JSQR_JSQ4_Pos)                        /*!< 0x40000000 */
#define ADC_JSQR_JSQ4_4                           (0x10UL<<ADC_JSQR_JSQ4_Pos)                       /*!< 0x80000000 */

/********************************* Bit definition for ADC_OFR1 register *********************************************/
#define ADC_OFR1_OFFSET1_Pos                      (0U)
#define ADC_OFR1_OFFSET1_Msk                      (0xFFFUL<<ADC_OFR1_OFFSET1_Pos)                   /*!< 0x00000FFF */
#define ADC_OFR1_OFFSET1                          ADC_OFR1_OFFSET1_Msk
#define ADC_OFR1_OFFSETPOS_Pos                    (24U)
#define ADC_OFR1_OFFSETPOS_Msk                    (0x1UL<<ADC_OFR1_OFFSETPOS_Pos)                   /*!< 0x01000000 */
#define ADC_OFR1_OFFSETPOS                        ADC_OFR1_OFFSETPOS_Msk                            
#define ADC_OFR1_SATEN_Pos                        (25U)
#define ADC_OFR1_SATEN_Msk                        (0x1UL<<ADC_OFR1_SATEN_Pos)                       /*!< 0x02000000 */
#define ADC_OFR1_SATEN                            ADC_OFR1_SATEN_Msk                                
#define ADC_OFR1_OFFSET1_CH_Pos                   (26U)
#define ADC_OFR1_OFFSET1_CH_Msk                   (0x1FUL<<ADC_OFR1_OFFSET1_CH_Pos)                 /*!< 0x7C000000 */
#define ADC_OFR1_OFFSET1_CH                       ADC_OFR1_OFFSET1_CH_Msk
#define ADC_OFR1_OFFSET1_CH_0                     (0x1UL<<ADC_OFR1_OFFSET1_CH_Pos)                  /*!< 0x04000000 */
#define ADC_OFR1_OFFSET1_CH_1                     (0x2UL<<ADC_OFR1_OFFSET1_CH_Pos)                  /*!< 0x08000000 */
#define ADC_OFR1_OFFSET1_CH_2                     (0x4UL<<ADC_OFR1_OFFSET1_CH_Pos)                  /*!< 0x10000000 */
#define ADC_OFR1_OFFSET1_CH_3                     (0x8UL<<ADC_OFR1_OFFSET1_CH_Pos)                  /*!< 0x20000000 */
#define ADC_OFR1_OFFSET1_CH_4                     (0x10UL<<ADC_OFR1_OFFSET1_CH_Pos)                 /*!< 0x40000000 */
#define ADC_OFR1_OFFSET1_EN_Pos                   (31U)
#define ADC_OFR1_OFFSET1_EN_Msk                   (0x1UL<<ADC_OFR1_OFFSET1_EN_Pos)                  /*!< 0x80000000 */
#define ADC_OFR1_OFFSET1_EN                       ADC_OFR1_OFFSET1_EN_Msk                           

/********************************* Bit definition for ADC_OFR2 register *********************************************/
#define ADC_OFR2_OFFSET2_Pos                      (0U)
#define ADC_OFR2_OFFSET2_Msk                      (0xFFFUL<<ADC_OFR2_OFFSET2_Pos)                   /*!< 0x00000FFF */
#define ADC_OFR2_OFFSET2                          ADC_OFR2_OFFSET2_Msk
#define ADC_OFR2_OFFSET2_CH_Pos                   (26U)
#define ADC_OFR2_OFFSET2_CH_Msk                   (0x1FUL<<ADC_OFR2_OFFSET2_CH_Pos)                 /*!< 0x7C000000 */
#define ADC_OFR2_OFFSET2_CH                       ADC_OFR2_OFFSET2_CH_Msk
#define ADC_OFR2_OFFSET2_CH_0                     (0x1UL<<ADC_OFR2_OFFSET2_CH_Pos)                  /*!< 0x04000000 */
#define ADC_OFR2_OFFSET2_CH_1                     (0x2UL<<ADC_OFR2_OFFSET2_CH_Pos)                  /*!< 0x08000000 */
#define ADC_OFR2_OFFSET2_CH_2                     (0x4UL<<ADC_OFR2_OFFSET2_CH_Pos)                  /*!< 0x10000000 */
#define ADC_OFR2_OFFSET2_CH_3                     (0x8UL<<ADC_OFR2_OFFSET2_CH_Pos)                  /*!< 0x20000000 */
#define ADC_OFR2_OFFSET2_CH_4                     (0x10UL<<ADC_OFR2_OFFSET2_CH_Pos)                 /*!< 0x40000000 */
#define ADC_OFR2_OFFSET2_EN_Pos                   (31U)
#define ADC_OFR2_OFFSET2_EN_Msk                   (0x1UL<<ADC_OFR2_OFFSET2_EN_Pos)                  /*!< 0x80000000 */
#define ADC_OFR2_OFFSET2_EN                       ADC_OFR2_OFFSET2_EN_Msk                           

/********************************* Bit definition for ADC_OFR3 register *********************************************/
#define ADC_OFR3_OFFSET3_Pos                      (0U)
#define ADC_OFR3_OFFSET3_Msk                      (0xFFFUL<<ADC_OFR3_OFFSET3_Pos)                   /*!< 0x00000FFF */
#define ADC_OFR3_OFFSET3                          ADC_OFR3_OFFSET3_Msk
#define ADC_OFR3_OFFSET3_CH_Pos                   (26U)
#define ADC_OFR3_OFFSET3_CH_Msk                   (0x1FUL<<ADC_OFR3_OFFSET3_CH_Pos)                 /*!< 0x7C000000 */
#define ADC_OFR3_OFFSET3_CH                       ADC_OFR3_OFFSET3_CH_Msk
#define ADC_OFR3_OFFSET3_CH_0                     (0x1UL<<ADC_OFR3_OFFSET3_CH_Pos)                  /*!< 0x04000000 */
#define ADC_OFR3_OFFSET3_CH_1                     (0x2UL<<ADC_OFR3_OFFSET3_CH_Pos)                  /*!< 0x08000000 */
#define ADC_OFR3_OFFSET3_CH_2                     (0x4UL<<ADC_OFR3_OFFSET3_CH_Pos)                  /*!< 0x10000000 */
#define ADC_OFR3_OFFSET3_CH_3                     (0x8UL<<ADC_OFR3_OFFSET3_CH_Pos)                  /*!< 0x20000000 */
#define ADC_OFR3_OFFSET3_CH_4                     (0x10UL<<ADC_OFR3_OFFSET3_CH_Pos)                 /*!< 0x40000000 */
#define ADC_OFR3_OFFSET3_EN_Pos                   (31U)
#define ADC_OFR3_OFFSET3_EN_Msk                   (0x1UL<<ADC_OFR3_OFFSET3_EN_Pos)                  /*!< 0x80000000 */
#define ADC_OFR3_OFFSET3_EN                       ADC_OFR3_OFFSET3_EN_Msk                           

/********************************* Bit definition for ADC_OFR4 register *********************************************/
#define ADC_OFR4_OFFSET4_Pos                      (0U)
#define ADC_OFR4_OFFSET4_Msk                      (0xFFFUL<<ADC_OFR4_OFFSET4_Pos)                   /*!< 0x00000FFF */
#define ADC_OFR4_OFFSET4                          ADC_OFR4_OFFSET4_Msk
#define ADC_OFR4_OFFSET4_CH_Pos                   (26U)
#define ADC_OFR4_OFFSET4_CH_Msk                   (0x1FUL<<ADC_OFR4_OFFSET4_CH_Pos)                 /*!< 0x7C000000 */
#define ADC_OFR4_OFFSET4_CH                       ADC_OFR4_OFFSET4_CH_Msk
#define ADC_OFR4_OFFSET4_CH_0                     (0x1UL<<ADC_OFR4_OFFSET4_CH_Pos)                  /*!< 0x04000000 */
#define ADC_OFR4_OFFSET4_CH_1                     (0x2UL<<ADC_OFR4_OFFSET4_CH_Pos)                  /*!< 0x08000000 */
#define ADC_OFR4_OFFSET4_CH_2                     (0x4UL<<ADC_OFR4_OFFSET4_CH_Pos)                  /*!< 0x10000000 */
#define ADC_OFR4_OFFSET4_CH_3                     (0x8UL<<ADC_OFR4_OFFSET4_CH_Pos)                  /*!< 0x20000000 */
#define ADC_OFR4_OFFSET4_CH_4                     (0x10UL<<ADC_OFR4_OFFSET4_CH_Pos)                 /*!< 0x40000000 */
#define ADC_OFR4_OFFSET4_EN_Pos                   (31U)
#define ADC_OFR4_OFFSET4_EN_Msk                   (0x1UL<<ADC_OFR4_OFFSET4_EN_Pos)                  /*!< 0x80000000 */
#define ADC_OFR4_OFFSET4_EN                       ADC_OFR4_OFFSET4_EN_Msk                           

/********************************* Bit definition for ADC_JDR1 register *********************************************/
#define ADC_JDR1_JDATA_Pos                        (0U)
#define ADC_JDR1_JDATA_Msk                        (0xFFFFUL<<ADC_JDR1_JDATA_Pos)                    /*!< 0x0000FFFF */
#define ADC_JDR1_JDATA                            ADC_JDR1_JDATA_Msk

/********************************* Bit definition for ADC_JDR2 register *********************************************/
#define ADC_JDR2_JDATA_Pos                        (0U)
#define ADC_JDR2_JDATA_Msk                        (0xFFFFUL<<ADC_JDR2_JDATA_Pos)                    /*!< 0x0000FFFF */
#define ADC_JDR2_JDATA                            ADC_JDR2_JDATA_Msk

/********************************* Bit definition for ADC_JDR3 register *********************************************/
#define ADC_JDR3_JDATA_Pos                        (0U)
#define ADC_JDR3_JDATA_Msk                        (0xFFFFUL<<ADC_JDR3_JDATA_Pos)                    /*!< 0x0000FFFF */
#define ADC_JDR3_JDATA                            ADC_JDR3_JDATA_Msk

/********************************* Bit definition for ADC_JDR4 register *********************************************/
#define ADC_JDR4_JDATA_Pos                        (0U)
#define ADC_JDR4_JDATA_Msk                        (0xFFFFUL<<ADC_JDR4_JDATA_Pos)                    /*!< 0x0000FFFF */
#define ADC_JDR4_JDATA                            ADC_JDR4_JDATA_Msk

/********************************* Bit definition for ADC_AWD2CR register *******************************************/
#define ADC_AWD2CR_AWD2CH_Pos                     (0U)
#define ADC_AWD2CR_AWD2CH_Msk                     (0x3FFFFFUL<<ADC_AWD2CR_AWD2CH_Pos)               /*!< 0x003FFFFF */
#define ADC_AWD2CR_AWD2CH                         ADC_AWD2CR_AWD2CH_Msk
#define ADC_AWD2CR_AWD2CH_0                       (0x000001UL << ADC_AWD2CR_AWD2CH_Pos)              /*!< 0x00000001 */
#define ADC_AWD2CR_AWD2CH_1                       (0x000002UL << ADC_AWD2CR_AWD2CH_Pos)              /*!< 0x00000002 */
#define ADC_AWD2CR_AWD2CH_2                       (0x000004UL << ADC_AWD2CR_AWD2CH_Pos)              /*!< 0x00000004 */
#define ADC_AWD2CR_AWD2CH_3                       (0x000008UL << ADC_AWD2CR_AWD2CH_Pos)              /*!< 0x00000008 */
#define ADC_AWD2CR_AWD2CH_4                       (0x000010UL << ADC_AWD2CR_AWD2CH_Pos)              /*!< 0x00000010 */
#define ADC_AWD2CR_AWD2CH_5                       (0x000020UL << ADC_AWD2CR_AWD2CH_Pos)              /*!< 0x00000020 */
#define ADC_AWD2CR_AWD2CH_6                       (0x000040UL << ADC_AWD2CR_AWD2CH_Pos)              /*!< 0x00000040 */
#define ADC_AWD2CR_AWD2CH_7                       (0x000080UL << ADC_AWD2CR_AWD2CH_Pos)              /*!< 0x00000080 */
#define ADC_AWD2CR_AWD2CH_8                       (0x000100UL << ADC_AWD2CR_AWD2CH_Pos)              /*!< 0x00000100 */
#define ADC_AWD2CR_AWD2CH_9                       (0x000200UL << ADC_AWD2CR_AWD2CH_Pos)              /*!< 0x00000200 */
#define ADC_AWD2CR_AWD2CH_10                      (0x000400UL << ADC_AWD2CR_AWD2CH_Pos)              /*!< 0x00000400 */
#define ADC_AWD2CR_AWD2CH_11                      (0x000800UL << ADC_AWD2CR_AWD2CH_Pos)              /*!< 0x00000800 */
#define ADC_AWD2CR_AWD2CH_12                      (0x001000UL << ADC_AWD2CR_AWD2CH_Pos)              /*!< 0x00001000 */
#define ADC_AWD2CR_AWD2CH_13                      (0x002000UL << ADC_AWD2CR_AWD2CH_Pos)              /*!< 0x00002000 */
#define ADC_AWD2CR_AWD2CH_14                      (0x004000UL << ADC_AWD2CR_AWD2CH_Pos)              /*!< 0x00004000 */
#define ADC_AWD2CR_AWD2CH_15                      (0x008000UL << ADC_AWD2CR_AWD2CH_Pos)              /*!< 0x00008000 */
#define ADC_AWD2CR_AWD2CH_16                      (0x010000UL << ADC_AWD2CR_AWD2CH_Pos)              /*!< 0x00010000 */
#define ADC_AWD2CR_AWD2CH_17                      (0x020000UL << ADC_AWD2CR_AWD2CH_Pos)              /*!< 0x00020000 */
#define ADC_AWD2CR_AWD2CH_18                      (0x040000UL << ADC_AWD2CR_AWD2CH_Pos)              /*!< 0x00040000 */
#define ADC_AWD2CR_AWD2CH_19                      (0x080000UL << ADC_AWD2CR_AWD2CH_Pos)              /*!< 0x00080000 */
#define ADC_AWD2CR_AWD2CH_20                      (0x100000UL << ADC_AWD2CR_AWD2CH_Pos)              /*!< 0x00100000 */
#define ADC_AWD2CR_AWD2CH_21                      (0x200000UL << ADC_AWD2CR_AWD2CH_Pos)              /*!< 0x00200000 */

/********************************* Bit definition for ADC_AWD3CR register *******************************************/
#define ADC_AWD3CR_AWD3CH_Pos                     (0U)
#define ADC_AWD3CR_AWD3CH_Msk                     (0x3FFFFFUL<<ADC_AWD3CR_AWD3CH_Pos)               /*!< 0x003FFFFF */
#define ADC_AWD3CR_AWD3CH                         ADC_AWD3CR_AWD3CH_Msk
#define ADC_AWD3CR_AWD3CH_0                       (0x000001UL << ADC_AWD3CR_AWD3CH_Pos)              /*!< 0x00000001 */
#define ADC_AWD3CR_AWD3CH_1                       (0x000002UL << ADC_AWD3CR_AWD3CH_Pos)              /*!< 0x00000002 */
#define ADC_AWD3CR_AWD3CH_2                       (0x000004UL << ADC_AWD3CR_AWD3CH_Pos)              /*!< 0x00000004 */
#define ADC_AWD3CR_AWD3CH_3                       (0x000008UL << ADC_AWD3CR_AWD3CH_Pos)              /*!< 0x00000008 */
#define ADC_AWD3CR_AWD3CH_4                       (0x000010UL << ADC_AWD3CR_AWD3CH_Pos)              /*!< 0x00000010 */
#define ADC_AWD3CR_AWD3CH_5                       (0x000020UL << ADC_AWD3CR_AWD3CH_Pos)              /*!< 0x00000020 */
#define ADC_AWD3CR_AWD3CH_6                       (0x000040UL << ADC_AWD3CR_AWD3CH_Pos)              /*!< 0x00000040 */
#define ADC_AWD3CR_AWD3CH_7                       (0x000080UL << ADC_AWD3CR_AWD3CH_Pos)              /*!< 0x00000080 */
#define ADC_AWD3CR_AWD3CH_8                       (0x000100UL << ADC_AWD3CR_AWD3CH_Pos)              /*!< 0x00000100 */
#define ADC_AWD3CR_AWD3CH_9                       (0x000200UL << ADC_AWD3CR_AWD3CH_Pos)              /*!< 0x00000200 */
#define ADC_AWD3CR_AWD3CH_10                      (0x000400UL << ADC_AWD3CR_AWD3CH_Pos)              /*!< 0x00000400 */
#define ADC_AWD3CR_AWD3CH_11                      (0x000800UL << ADC_AWD3CR_AWD3CH_Pos)              /*!< 0x00000800 */
#define ADC_AWD3CR_AWD3CH_12                      (0x001000UL << ADC_AWD3CR_AWD3CH_Pos)              /*!< 0x00001000 */
#define ADC_AWD3CR_AWD3CH_13                      (0x002000UL << ADC_AWD3CR_AWD3CH_Pos)              /*!< 0x00002000 */
#define ADC_AWD3CR_AWD3CH_14                      (0x004000UL << ADC_AWD3CR_AWD3CH_Pos)              /*!< 0x00004000 */
#define ADC_AWD3CR_AWD3CH_15                      (0x008000UL << ADC_AWD3CR_AWD3CH_Pos)              /*!< 0x00008000 */
#define ADC_AWD3CR_AWD3CH_16                      (0x010000UL << ADC_AWD3CR_AWD3CH_Pos)              /*!< 0x00010000 */
#define ADC_AWD3CR_AWD3CH_17                      (0x020000UL << ADC_AWD3CR_AWD3CH_Pos)              /*!< 0x00020000 */
#define ADC_AWD3CR_AWD3CH_18                      (0x040000UL << ADC_AWD3CR_AWD3CH_Pos)              /*!< 0x00040000 */
#define ADC_AWD2CR_AWD3CH_19                      (0x080000UL << ADC_AWD3CR_AWD3CH_Pos)              /*!< 0x00080000 */
#define ADC_AWD2CR_AWD3CH_20                      (0x100000UL << ADC_AWD3CR_AWD3CH_Pos)              /*!< 0x00100000 */
#define ADC_AWD2CR_AWD3CH_21                      (0x200000UL << ADC_AWD3CR_AWD3CH_Pos)              /*!< 0x00200000 */

/********************************* Bit definition for ADC_DIFSEL register *******************************************/
#define ADC_DIFSEL_DIFSEL6_Pos                    (6U)
#define ADC_DIFSEL_DIFSEL6_Msk                    (0x1UL<<ADC_DIFSEL_DIFSEL6_Pos)               /*!< 0x00000040 */
#define ADC_DIFSEL_DIFSEL6                        ADC_DIFSEL_DIFSEL6_Msk
#define ADC_DIFSEL_DIFSEL8_Pos                    (8U)
#define ADC_DIFSEL_DIFSEL8_Msk                    (0x1UL<<ADC_DIFSEL_DIFSEL8_Pos)               /*!< 0x00000100 */
#define ADC_DIFSEL_DIFSEL8                        ADC_DIFSEL_DIFSEL8_Msk
#define ADC_DIFSEL_DIFSEL10_Pos                   (10U)
#define ADC_DIFSEL_DIFSEL10_Msk                   (0x1UL<<ADC_DIFSEL_DIFSEL10_Pos)              /*!< 0x00000400 */
#define ADC_DIFSEL_DIFSEL10                       ADC_DIFSEL_DIFSEL10_Msk
#define ADC_DIFSEL_DIFSEL12_Pos                   (12U)
#define ADC_DIFSEL_DIFSEL12_Msk                   (0x1UL<<ADC_DIFSEL_DIFSEL12_Pos)              /*!< 0x00001000 */
#define ADC_DIFSEL_DIFSEL12                       ADC_DIFSEL_DIFSEL12_Msk
#define ADC_DIFSEL_DIFSEL_Pos                     (0U)
#define ADC_DIFSEL_DIFSEL_Msk                     (0x0FFFFUL<<ADC_DIFSEL_DIFSEL_Pos)                /*!< 0x0000FFFF */
#define ADC_DIFSEL_DIFSEL                         ADC_DIFSEL_DIFSEL_Msk

/********************************* Bit definition for ADC_CALFACT register ******************************************/
#define ADC_CALFACT_WCALFACT_Pos                  (0U)
#define ADC_CALFACT_WCALFACT_Msk                  (0x1FFUL<<ADC_CALFACT_WCALFACT_Pos)               /*!< 0x000001FF */
#define ADC_CALFACT_WCALFACT                      ADC_CALFACT_WCALFACT_Msk
#define ADC_CALFACT_FACTSEL_Pos                   (9U)
#define ADC_CALFACT_FACTSEL_Msk                   (0x1FUL<<ADC_CALFACT_FACTSEL_Pos)                 /*!< 0x00003E00 */
#define ADC_CALFACT_FACTSEL                       ADC_CALFACT_FACTSEL_Msk
#define ADC_CALFACT_FACTSEL_0                     (0x1UL<<ADC_CALFACT_FACTSEL_Pos)                  /*!< 0x00000200 */
#define ADC_CALFACT_FACTSEL_1                     (0x2UL<<ADC_CALFACT_FACTSEL_Pos)                  /*!< 0x00000400 */
#define ADC_CALFACT_FACTSEL_2                     (0x4UL<<ADC_CALFACT_FACTSEL_Pos)                  /*!< 0x00000800 */
#define ADC_CALFACT_FACTSEL_3                     (0x8UL<<ADC_CALFACT_FACTSEL_Pos)                  /*!< 0x00001000 */
#define ADC_CALFACT_FACTSEL_4                     (0x10UL<<ADC_CALFACT_FACTSEL_Pos)                 /*!< 0x00002000 */
#define ADC_CALFACT_WRVLD_Pos                     (14U)
#define ADC_CALFACT_WRVLD_Msk                     (0x1UL<<ADC_CALFACT_WRVLD_Pos)                    /*!< 0x00004000 */
#define ADC_CALFACT_WRVLD                         ADC_CALFACT_WRVLD_Msk                             
#define ADC_CALFACT_RDVLD_Pos                     (15U)
#define ADC_CALFACT_RDVLD_Msk                     (0x1UL<<ADC_CALFACT_RDVLD_Pos)                    /*!< 0x00008000 */
#define ADC_CALFACT_RDVLD                         ADC_CALFACT_RDVLD_Msk                             
#define ADC_CALFACT_OFFSUC_Pos                    (20U)
#define ADC_CALFACT_OFFSUC_Msk                    (0x1UL<<ADC_CALFACT_OFFSUC_Pos)                   /*!< 0x00100000 */
#define ADC_CALFACT_OFFSUC                        ADC_CALFACT_OFFSUC_Msk                            
#define ADC_CALFACT_CAPSUC_Pos                    (21U)
#define ADC_CALFACT_CAPSUC_Msk                    (0x1UL<<ADC_CALFACT_CAPSUC_Pos)                   /*!< 0x00200000 */
#define ADC_CALFACT_CAPSUC                        ADC_CALFACT_CAPSUC_Msk                            
#define ADC_CALFACT_RCALFACT_Pos                  (23U)
#define ADC_CALFACT_RCALFACT_Msk                  (0x1FFUL<<ADC_CALFACT_RCALFACT_Pos)               /*!< 0xFF800000 */
#define ADC_CALFACT_RCALFACT                      ADC_CALFACT_RCALFACT_Msk

/********************************* Bit definition for ADC_GCOMP register ********************************************/
#define ADC_GCOMP_GCOMPCOEFF_Pos                  (0U)
#define ADC_GCOMP_GCOMPCOEFF_Msk                  (0x3FFFUL<<ADC_GCOMP_GCOMPCOEFF_Pos)              /*!< 0x00003FFF */
#define ADC_GCOMP_GCOMPCOEFF                      ADC_GCOMP_GCOMPCOEFF_Msk

/********************************* Bit definition for ADC_ANACR register ********************************************/
#define ADC_ANACR_PWRMODE_Pos                     (1U)
#define ADC_ANACR_PWRMODE_Msk                     (0x7UL<<ADC_ANACR_PWRMODE_Pos)                    /*!< 0x0000000E */
#define ADC_ANACR_PWRMODE                         ADC_ANACR_PWRMODE_Msk
#define ADC_ANACR_PWRMODE_0                       (0x1UL<<ADC_ANACR_PWRMODE_Pos)                    /*!< 0x00000002 */
#define ADC_ANACR_PWRMODE_1                       (0x2UL<<ADC_ANACR_PWRMODE_Pos)                    /*!< 0x00000004 */
#define ADC_ANACR_PWRMODE_2                       (0x4UL<<ADC_ANACR_PWRMODE_Pos)                    /*!< 0x00000008 */
#define ADC_ANACR_VREFSEL_Pos                     (4U)
#define ADC_ANACR_VREFSEL_Msk                     (0x1UL<<ADC_ANACR_VREFSEL_Pos)                    /*!< 0x00000010 */
#define ADC_ANACR_VREFSEL                         ADC_ANACR_VREFSEL_Msk                             

/********************************* Bit definition for ADC_CSR register **********************************************/
#define ADC_CSR_ADRDY_MST_Pos                     (0U)
#define ADC_CSR_ADRDY_MST_Msk                     (0x1UL<<ADC_CSR_ADRDY_MST_Pos)                    /*!< 0x00000001 */
#define ADC_CSR_ADRDY_MST                         ADC_CSR_ADRDY_MST_Msk                             
#define ADC_CSR_EOSMP_MST_Pos                     (1U)
#define ADC_CSR_EOSMP_MST_Msk                     (0x1UL<<ADC_CSR_EOSMP_MST_Pos)                    /*!< 0x00000002 */
#define ADC_CSR_EOSMP_MST                         ADC_CSR_EOSMP_MST_Msk                             
#define ADC_CSR_EOC_MST_Pos                       (2U)
#define ADC_CSR_EOC_MST_Msk                       (0x1UL<<ADC_CSR_EOC_MST_Pos)                      /*!< 0x00000004 */
#define ADC_CSR_EOC_MST                           ADC_CSR_EOC_MST_Msk                               
#define ADC_CSR_EOS_MST_Pos                       (3U)
#define ADC_CSR_EOS_MST_Msk                       (0x1UL<<ADC_CSR_EOS_MST_Pos)                      /*!< 0x00000008 */
#define ADC_CSR_EOS_MST                           ADC_CSR_EOS_MST_Msk                               
#define ADC_CSR_OVR_MST_Pos                       (4U)
#define ADC_CSR_OVR_MST_Msk                       (0x1UL<<ADC_CSR_OVR_MST_Pos)                      /*!< 0x00000010 */
#define ADC_CSR_OVR_MST                           ADC_CSR_OVR_MST_Msk                               
#define ADC_CSR_JEOC_MST_Pos                      (5U)
#define ADC_CSR_JEOC_MST_Msk                      (0x1UL<<ADC_CSR_JEOC_MST_Pos)                     /*!< 0x00000020 */
#define ADC_CSR_JEOC_MST                          ADC_CSR_JEOC_MST_Msk                              
#define ADC_CSR_JEOS_MST_Pos                      (6U)
#define ADC_CSR_JEOS_MST_Msk                      (0x1UL<<ADC_CSR_JEOS_MST_Pos)                     /*!< 0x00000040 */
#define ADC_CSR_JEOS_MST                          ADC_CSR_JEOS_MST_Msk                              
#define ADC_CSR_AWD1_MST_Pos                      (7U)
#define ADC_CSR_AWD1_MST_Msk                      (0x1UL<<ADC_CSR_AWD1_MST_Pos)                     /*!< 0x00000080 */
#define ADC_CSR_AWD1_MST                          ADC_CSR_AWD1_MST_Msk                              
#define ADC_CSR_AWD2_MST_Pos                      (8U)
#define ADC_CSR_AWD2_MST_Msk                      (0x1UL<<ADC_CSR_AWD2_MST_Pos)                     /*!< 0x00000100 */
#define ADC_CSR_AWD2_MST                          ADC_CSR_AWD2_MST_Msk                              
#define ADC_CSR_AWD3_MST_Pos                      (9U)
#define ADC_CSR_AWD3_MST_Msk                      (0x1UL<<ADC_CSR_AWD3_MST_Pos)                     /*!< 0x00000200 */
#define ADC_CSR_AWD3_MST                          ADC_CSR_AWD3_MST_Msk                              
#define ADC_CSR_ADRDY_SLV_Pos                     (16U)
#define ADC_CSR_ADRDY_SLV_Msk                     (0x1UL<<ADC_CSR_ADRDY_SLV_Pos)                    /*!< 0x00010000 */
#define ADC_CSR_ADRDY_SLV                         ADC_CSR_ADRDY_SLV_Msk                             
#define ADC_CSR_EOSMP_SLV_Pos                     (17U)
#define ADC_CSR_EOSMP_SLV_Msk                     (0x1UL<<ADC_CSR_EOSMP_SLV_Pos)                    /*!< 0x00020000 */
#define ADC_CSR_EOSMP_SLV                         ADC_CSR_EOSMP_SLV_Msk                             
#define ADC_CSR_EOC_SLV_Pos                       (18U)
#define ADC_CSR_EOC_SLV_Msk                       (0x1UL<<ADC_CSR_EOC_SLV_Pos)                      /*!< 0x00040000 */
#define ADC_CSR_EOC_SLV                           ADC_CSR_EOC_SLV_Msk                               
#define ADC_CSR_EOS_SLV_Pos                       (19U)
#define ADC_CSR_EOS_SLV_Msk                       (0x1UL<<ADC_CSR_EOS_SLV_Pos)                      /*!< 0x00080000 */
#define ADC_CSR_EOS_SLV                           ADC_CSR_EOS_SLV_Msk                               
#define ADC_CSR_OVR_SLV_Pos                       (20U)
#define ADC_CSR_OVR_SLV_Msk                       (0x1UL<<ADC_CSR_OVR_SLV_Pos)                      /*!< 0x00100000 */
#define ADC_CSR_OVR_SLV                           ADC_CSR_OVR_SLV_Msk                               
#define ADC_CSR_JEOC_SLV_Pos                      (21U)
#define ADC_CSR_JEOC_SLV_Msk                      (0x1UL<<ADC_CSR_JEOC_SLV_Pos)                     /*!< 0x00200000 */
#define ADC_CSR_JEOC_SLV                          ADC_CSR_JEOC_SLV_Msk                              
#define ADC_CSR_JEOS_SLV_Pos                      (22U)
#define ADC_CSR_JEOS_SLV_Msk                      (0x1UL<<ADC_CSR_JEOS_SLV_Pos)                     /*!< 0x00400000 */
#define ADC_CSR_JEOS_SLV                          ADC_CSR_JEOS_SLV_Msk                              
#define ADC_CSR_AWD1_SLV_Pos                      (23U)
#define ADC_CSR_AWD1_SLV_Msk                      (0x1UL<<ADC_CSR_AWD1_SLV_Pos)                     /*!< 0x00800000 */
#define ADC_CSR_AWD1_SLV                          ADC_CSR_AWD1_SLV_Msk                              
#define ADC_CSR_AWD2_SLV_Pos                      (24U)
#define ADC_CSR_AWD2_SLV_Msk                      (0x1UL<<ADC_CSR_AWD2_SLV_Pos)                     /*!< 0x01000000 */
#define ADC_CSR_AWD2_SLV                          ADC_CSR_AWD2_SLV_Msk                              
#define ADC_CSR_AWD3_SLV_Pos                      (25U)
#define ADC_CSR_AWD3_SLV_Msk                      (0x1UL<<ADC_CSR_AWD3_SLV_Pos)                     /*!< 0x02000000 */
#define ADC_CSR_AWD3_SLV                          ADC_CSR_AWD3_SLV_Msk                              

/********************************* Bit definition for ADC_CCR register **********************************************/
#define ADC_CCR_DUAL_Pos                          (0U)
#define ADC_CCR_DUAL_Msk                          (0x1FUL<<ADC_CCR_DUAL_Pos)                        /*!< 0x0000001F */
#define ADC_CCR_DUAL                              ADC_CCR_DUAL_Msk
#define ADC_CCR_DUAL_0                            (0x1UL<<ADC_CCR_DUAL_Pos)                         /*!< 0x00000001 */
#define ADC_CCR_DUAL_1                            (0x2UL<<ADC_CCR_DUAL_Pos)                         /*!< 0x00000002 */
#define ADC_CCR_DUAL_2                            (0x4UL<<ADC_CCR_DUAL_Pos)                         /*!< 0x00000004 */
#define ADC_CCR_DUAL_3                            (0x8UL<<ADC_CCR_DUAL_Pos)                         /*!< 0x00000008 */
#define ADC_CCR_DUAL_4                            (0x10UL<<ADC_CCR_DUAL_Pos)                        /*!< 0x00000010 */
#define ADC_CCR_DELAY_Pos                         (8U)
#define ADC_CCR_DELAY_Msk                         (0xFUL<<ADC_CCR_DELAY_Pos)                        /*!< 0x00000F00 */
#define ADC_CCR_DELAY                             ADC_CCR_DELAY_Msk
#define ADC_CCR_DELAY_0                           (0x1UL<<ADC_CCR_DELAY_Pos)                        /*!< 0x00000100 */
#define ADC_CCR_DELAY_1                           (0x2UL<<ADC_CCR_DELAY_Pos)                        /*!< 0x00000200 */
#define ADC_CCR_DELAY_2                           (0x4UL<<ADC_CCR_DELAY_Pos)                        /*!< 0x00000400 */
#define ADC_CCR_DELAY_3                           (0x8UL<<ADC_CCR_DELAY_Pos)                        /*!< 0x00000800 */
#define ADC_CCR_DMACFG_Pos                        (13U)
#define ADC_CCR_DMACFG_Msk                        (0x1UL<<ADC_CCR_DMACFG_Pos)                       /*!< 0x00002000 */
#define ADC_CCR_DMACFG                            ADC_CCR_DMACFG_Msk                                
#define ADC_CCR_MDMA_Pos                          (14U)
#define ADC_CCR_MDMA_Msk                          (0x3UL<<ADC_CCR_MDMA_Pos)                         /*!< 0x0000C000 */
#define ADC_CCR_MDMA                              ADC_CCR_MDMA_Msk
#define ADC_CCR_MDMA_0                            (0x1UL<<ADC_CCR_MDMA_Pos)                         /*!< 0x00004000 */
#define ADC_CCR_MDMA_1                            (0x2UL<<ADC_CCR_MDMA_Pos)                         /*!< 0x00008000 */
#define ADC_CCR_CKMODE_Pos                        (16U)
#define ADC_CCR_CKMODE_Msk                        (0x3UL<<ADC_CCR_CKMODE_Pos)                       /*!< 0x00030000 */
#define ADC_CCR_CKMODE                            ADC_CCR_CKMODE_Msk
#define ADC_CCR_CKMODE_0                          (0x1UL<<ADC_CCR_CKMODE_Pos)                       /*!< 0x00010000 */
#define ADC_CCR_CKMODE_1                          (0x2UL<<ADC_CCR_CKMODE_Pos)                       /*!< 0x00020000 */
#define ADC_CCR_PRESC_Pos                         (18U)
#define ADC_CCR_PRESC_Msk                         (0xFUL<<ADC_CCR_PRESC_Pos)                        /*!< 0x003C0000 */
#define ADC_CCR_PRESC                             ADC_CCR_PRESC_Msk
#define ADC_CCR_PRESC_0                           (0x1UL<<ADC_CCR_PRESC_Pos)                        /*!< 0x00040000 */
#define ADC_CCR_PRESC_1                           (0x2UL<<ADC_CCR_PRESC_Pos)                        /*!< 0x00080000 */
#define ADC_CCR_PRESC_2                           (0x4UL<<ADC_CCR_PRESC_Pos)                        /*!< 0x00100000 */
#define ADC_CCR_PRESC_3                           (0x8UL<<ADC_CCR_PRESC_Pos)                        /*!< 0x00200000 */
#define ADC_CCR_VREFEN_Pos                        (22U)
#define ADC_CCR_VREFEN_Msk                        (0x1UL<<ADC_CCR_VREFEN_Pos)                       /*!< 0x00400000 */
#define ADC_CCR_VREFEN                            ADC_CCR_VREFEN_Msk                                
#define ADC_CCR_VSENSESEL_Pos                     (23U)
#define ADC_CCR_VSENSESEL_Msk                     (0x1UL<<ADC_CCR_VSENSESEL_Pos)                    /*!< 0x00800000 */
#define ADC_CCR_VSENSESEL                         ADC_CCR_VSENSESEL_Msk                             
#define ADC_CCR_BUFFER_EN_Pos                     (24U)
#define ADC_CCR_BUFFER_EN_Msk                     (0x1UL<<ADC_CCR_BUFFER_EN_Pos)                    /*!< 0x01000000 */
#define ADC_CCR_BUFFER_EN                         ADC_CCR_BUFFER_EN_Msk                             
#define ADC_CCR_BUFFER_SEL_CR_Pos                 (25U)
#define ADC_CCR_BUFFER_SEL_CR_Msk                 (0x1UL<<ADC_CCR_BUFFER_SEL_CR_Pos)                /*!< 0x02000000 */
#define ADC_CCR_BUFFER_SEL_CR                     ADC_CCR_BUFFER_SEL_CR_Msk                                           

/********************************* Bit definition for ADC_CDR register **********************************************/
#define ADC_CDR_RDATA_MST_Pos                     (0U)
#define ADC_CDR_RDATA_MST_Msk                     (0xFFFFUL<<ADC_CDR_RDATA_MST_Pos)                 /*!< 0x0000FFFF */
#define ADC_CDR_RDATA_MST                         ADC_CDR_RDATA_MST_Msk
#define ADC_CDR_RDATA_SLV_Pos                     (16U)
#define ADC_CDR_RDATA_SLV_Msk                     (0xFFFFUL<<ADC_CDR_RDATA_SLV_Pos)                 /*!< 0xFFFF0000 */
#define ADC_CDR_RDATA_SLV                         ADC_CDR_RDATA_SLV_Msk

/********************************************************************************************************************/
/********************************* DAC ******************************************************************************/
/********************************************************************************************************************/

/********************************* Bit definition for DAC_CR register ***********************************************/
#define DAC_CR_EN1_Pos                            (0U)
#define DAC_CR_EN1_Msk                            (0x1UL<<DAC_CR_EN1_Pos)                           /*!< 0x00000001 */
#define DAC_CR_EN1                                DAC_CR_EN1_Msk                                    
#define DAC_CR_TEN1_Pos                           (2U)
#define DAC_CR_TEN1_Msk                           (0x1UL<<DAC_CR_TEN1_Pos)                          /*!< 0x00000004 */
#define DAC_CR_TEN1                               DAC_CR_TEN1_Msk                                   
#define DAC_CR_TSEL1_Pos                          (3U)
#define DAC_CR_TSEL1_Msk                          (0xFUL<<DAC_CR_TSEL1_Pos)                         /*!< 0x00000078 */
#define DAC_CR_TSEL1                              DAC_CR_TSEL1_Msk
#define DAC_CR_TSEL1_0                            (0x1UL<<DAC_CR_TSEL1_Pos)                         /*!< 0x00000008 */
#define DAC_CR_TSEL1_1                            (0x2UL<<DAC_CR_TSEL1_Pos)                         /*!< 0x00000010 */
#define DAC_CR_TSEL1_2                            (0x4UL<<DAC_CR_TSEL1_Pos)                         /*!< 0x00000020 */
#define DAC_CR_TSEL1_3                            (0x8UL<<DAC_CR_TSEL1_Pos)                         /*!< 0x00000040 */
#define DAC_CR_WAVE1_Pos                          (7U)
#define DAC_CR_WAVE1_Msk                          (0x3UL<<DAC_CR_WAVE1_Pos)                         /*!< 0x00000180 */
#define DAC_CR_WAVE1                              DAC_CR_WAVE1_Msk
#define DAC_CR_WAVE1_0                            (0x1UL<<DAC_CR_WAVE1_Pos)                         /*!< 0x00000080 */
#define DAC_CR_WAVE1_1                            (0x2UL<<DAC_CR_WAVE1_Pos)                         /*!< 0x00000100 */
#define DAC_CR_MAMP1_Pos                          (9U)
#define DAC_CR_MAMP1_Msk                          (0xFUL<<DAC_CR_MAMP1_Pos)                         /*!< 0x00001E00 */
#define DAC_CR_MAMP1                              DAC_CR_MAMP1_Msk
#define DAC_CR_MAMP1_0                            (0x1UL<<DAC_CR_MAMP1_Pos)                         /*!< 0x00000200 */
#define DAC_CR_MAMP1_1                            (0x2UL<<DAC_CR_MAMP1_Pos)                         /*!< 0x00000400 */
#define DAC_CR_MAMP1_2                            (0x4UL<<DAC_CR_MAMP1_Pos)                         /*!< 0x00000800 */
#define DAC_CR_MAMP1_3                            (0x8UL<<DAC_CR_MAMP1_Pos)                         /*!< 0x00001000 */
#define DAC_CR_DMAEN1_Pos                         (13U)
#define DAC_CR_DMAEN1_Msk                         (0x1UL<<DAC_CR_DMAEN1_Pos)                        /*!< 0x00002000 */
#define DAC_CR_DMAEN1                             DAC_CR_DMAEN1_Msk                                 
#define DAC_CR_DMAUDRIE1_Pos                      (14U)
#define DAC_CR_DMAUDRIE1_Msk                      (0x1UL<<DAC_CR_DMAUDRIE1_Pos)                     /*!< 0x00004000 */
#define DAC_CR_DMAUDRIE1                          DAC_CR_DMAUDRIE1_Msk                              
#define DAC_CR_EN2_Pos                            (16U)
#define DAC_CR_EN2_Msk                            (0x1UL<<DAC_CR_EN2_Pos)                           /*!< 0x00010000 */
#define DAC_CR_EN2                                DAC_CR_EN2_Msk                                    
#define DAC_CR_TEN2_Pos                           (18U)
#define DAC_CR_TEN2_Msk                           (0x1UL<<DAC_CR_TEN2_Pos)                          /*!< 0x00040000 */
#define DAC_CR_TEN2                               DAC_CR_TEN2_Msk                                   
#define DAC_CR_TSEL2_Pos                          (19U)
#define DAC_CR_TSEL2_Msk                          (0xFUL<<DAC_CR_TSEL2_Pos)                         /*!< 0x00780000 */
#define DAC_CR_TSEL2                              DAC_CR_TSEL2_Msk
#define DAC_CR_TSEL2_0                            (0x1UL<<DAC_CR_TSEL2_Pos)                         /*!< 0x00080000 */
#define DAC_CR_TSEL2_1                            (0x2UL<<DAC_CR_TSEL2_Pos)                         /*!< 0x00100000 */
#define DAC_CR_TSEL2_2                            (0x4UL<<DAC_CR_TSEL2_Pos)                         /*!< 0x00200000 */
#define DAC_CR_TSEL2_3                            (0x8UL<<DAC_CR_TSEL2_Pos)                         /*!< 0x00400000 */
#define DAC_CR_WAVE2_Pos                          (23U)
#define DAC_CR_WAVE2_Msk                          (0x3UL<<DAC_CR_WAVE2_Pos)                         /*!< 0x01800000 */
#define DAC_CR_WAVE2                              DAC_CR_WAVE2_Msk
#define DAC_CR_WAVE2_0                            (0x1UL<<DAC_CR_WAVE2_Pos)                         /*!< 0x00800000 */
#define DAC_CR_WAVE2_1                            (0x2UL<<DAC_CR_WAVE2_Pos)                         /*!< 0x01000000 */
#define DAC_CR_MAMP2_Pos                          (25U)
#define DAC_CR_MAMP2_Msk                          (0xFUL<<DAC_CR_MAMP2_Pos)                         /*!< 0x1E000000 */
#define DAC_CR_MAMP2                              DAC_CR_MAMP2_Msk
#define DAC_CR_MAMP2_0                            (0x1UL<<DAC_CR_MAMP2_Pos)                         /*!< 0x02000000 */
#define DAC_CR_MAMP2_1                            (0x2UL<<DAC_CR_MAMP2_Pos)                         /*!< 0x04000000 */
#define DAC_CR_MAMP2_2                            (0x4UL<<DAC_CR_MAMP2_Pos)                         /*!< 0x08000000 */
#define DAC_CR_MAMP2_3                            (0x8UL<<DAC_CR_MAMP2_Pos)                         /*!< 0x10000000 */
#define DAC_CR_DMAEN2_Pos                         (29U)
#define DAC_CR_DMAEN2_Msk                         (0x1UL<<DAC_CR_DMAEN2_Pos)                        /*!< 0x20000000 */
#define DAC_CR_DMAEN2                             DAC_CR_DMAEN2_Msk                                 
#define DAC_CR_DMAUDRIE2_Pos                      (30U)
#define DAC_CR_DMAUDRIE2_Msk                      (0x1UL<<DAC_CR_DMAUDRIE2_Pos)                     /*!< 0x40000000 */
#define DAC_CR_DMAUDRIE2                          DAC_CR_DMAUDRIE2_Msk                              

/********************************* Bit definition for DAC_SWTRIGR register ******************************************/
#define DAC_SWTRIGR_SWTRIG1_Pos                   (0U)
#define DAC_SWTRIGR_SWTRIG1_Msk                   (0x1UL<<DAC_SWTRIGR_SWTRIG1_Pos)                  /*!< 0x00000001 */
#define DAC_SWTRIGR_SWTRIG1                       DAC_SWTRIGR_SWTRIG1_Msk                           
#define DAC_SWTRIGR_SWTRIG2_Pos                   (1U)
#define DAC_SWTRIGR_SWTRIG2_Msk                   (0x1UL<<DAC_SWTRIGR_SWTRIG2_Pos)                  /*!< 0x00000002 */
#define DAC_SWTRIGR_SWTRIG2                       DAC_SWTRIGR_SWTRIG2_Msk                           

/********************************* Bit definition for DAC_DHR12R1 register ******************************************/
#define DAC_DHR12R1_DACC1DHR_Pos                  (0U)
#define DAC_DHR12R1_DACC1DHR_Msk                  (0xFFFUL<<DAC_DHR12R1_DACC1DHR_Pos)               /*!< 0x00000FFF */
#define DAC_DHR12R1_DACC1DHR                      DAC_DHR12R1_DACC1DHR_Msk

/********************************* Bit definition for DAC_DHR12L1 register ******************************************/
#define DAC_DHR12L1_DACC1DHR_Pos                  (4U)
#define DAC_DHR12L1_DACC1DHR_Msk                  (0xFFFUL<<DAC_DHR12L1_DACC1DHR_Pos)               /*!< 0x0000FFF0 */
#define DAC_DHR12L1_DACC1DHR                      DAC_DHR12L1_DACC1DHR_Msk

/********************************* Bit definition for DAC_DHR8R1 register *******************************************/
#define DAC_DHR8R1_DACC1DHR_Pos                   (0U)
#define DAC_DHR8R1_DACC1DHR_Msk                   (0xFFUL<<DAC_DHR8R1_DACC1DHR_Pos)                 /*!< 0x000000FF */
#define DAC_DHR8R1_DACC1DHR                       DAC_DHR8R1_DACC1DHR_Msk

/********************************* Bit definition for DAC_DHR12R2 register ******************************************/
#define DAC_DHR12R2_DACC2DHR_Pos                  (0U)
#define DAC_DHR12R2_DACC2DHR_Msk                  (0xFFFUL<<DAC_DHR12R2_DACC2DHR_Pos)               /*!< 0x00000FFF */
#define DAC_DHR12R2_DACC2DHR                      DAC_DHR12R2_DACC2DHR_Msk

/********************************* Bit definition for DAC_DHR12L2 register ******************************************/
#define DAC_DHR12L2_DACC2DHR_Pos                  (4U)
#define DAC_DHR12L2_DACC2DHR_Msk                  (0xFFFUL<<DAC_DHR12L2_DACC2DHR_Pos)               /*!< 0x0000FFF0 */
#define DAC_DHR12L2_DACC2DHR                      DAC_DHR12L2_DACC2DHR_Msk

/********************************* Bit definition for DAC_DHR8R2 register *******************************************/
#define DAC_DHR8R2_DACC2DHR_Pos                   (0U)
#define DAC_DHR8R2_DACC2DHR_Msk                   (0xFFUL<<DAC_DHR8R2_DACC2DHR_Pos)                 /*!< 0x000000FF */
#define DAC_DHR8R2_DACC2DHR                       DAC_DHR8R2_DACC2DHR_Msk

/********************************* Bit definition for DAC_DHR12RD register ******************************************/
#define DAC_DHR12RD_DACC1DHR_Pos                  (0U)
#define DAC_DHR12RD_DACC1DHR_Msk                  (0xFFFUL<<DAC_DHR12RD_DACC1DHR_Pos)               /*!< 0x00000FFF */
#define DAC_DHR12RD_DACC1DHR                      DAC_DHR12RD_DACC1DHR_Msk
#define DAC_DHR12RD_DACC2DHR_Pos                  (16U)
#define DAC_DHR12RD_DACC2DHR_Msk                  (0xFFFUL<<DAC_DHR12RD_DACC2DHR_Pos)               /*!< 0x0FFF0000 */
#define DAC_DHR12RD_DACC2DHR                      DAC_DHR12RD_DACC2DHR_Msk

/********************************* Bit definition for DAC_DHR12LD register ******************************************/
#define DAC_DHR12LD_DACC1DHR_Pos                  (4U)
#define DAC_DHR12LD_DACC1DHR_Msk                  (0xFFFUL<<DAC_DHR12LD_DACC1DHR_Pos)               /*!< 0x0000FFF0 */
#define DAC_DHR12LD_DACC1DHR                      DAC_DHR12LD_DACC1DHR_Msk
#define DAC_DHR12LD_DACC2DHR_Pos                  (20U)
#define DAC_DHR12LD_DACC2DHR_Msk                  (0xFFFUL<<DAC_DHR12LD_DACC2DHR_Pos)               /*!< 0xFFF00000 */
#define DAC_DHR12LD_DACC2DHR                      DAC_DHR12LD_DACC2DHR_Msk

/********************************* Bit definition for DAC_DHR8RD register *******************************************/
#define DAC_DHR8RD_DACC1DHR_Pos                   (0U)
#define DAC_DHR8RD_DACC1DHR_Msk                   (0xFFUL<<DAC_DHR8RD_DACC1DHR_Pos)                 /*!< 0x000000FF */
#define DAC_DHR8RD_DACC1DHR                       DAC_DHR8RD_DACC1DHR_Msk
#define DAC_DHR8RD_DACC2DHR_Pos                   (8U)
#define DAC_DHR8RD_DACC2DHR_Msk                   (0xFFUL<<DAC_DHR8RD_DACC2DHR_Pos)                 /*!< 0x0000FF00 */
#define DAC_DHR8RD_DACC2DHR                       DAC_DHR8RD_DACC2DHR_Msk

/********************************* Bit definition for DAC_DOR1 register *********************************************/
#define DAC_DOR1_DACC1DOR_Pos                     (0U)
#define DAC_DOR1_DACC1DOR_Msk                     (0xFFFUL<<DAC_DOR1_DACC1DOR_Pos)                  /*!< 0x00000FFF */
#define DAC_DOR1_DACC1DOR                         DAC_DOR1_DACC1DOR_Msk
#define DAC_DOR1_DAC_CMPOUT_Pos                   (12U)
#define DAC_DOR1_DAC_CMPOUT_Msk                   (0x1UL<<DAC_DOR1_DAC_CMPOUT_Pos)                  /*!< 0x00001000 */
#define DAC_DOR1_DAC_CMPOUT                       DAC_DOR1_DAC_CMPOUT_Msk                           

/********************************* Bit definition for DAC_DOR2 register *********************************************/
#define DAC_DOR2_DACC2DOR_Pos                     (0U)
#define DAC_DOR2_DACC2DOR_Msk                     (0xFFFUL<<DAC_DOR2_DACC2DOR_Pos)                  /*!< 0x00000FFF */
#define DAC_DOR2_DACC2DOR                         DAC_DOR2_DACC2DOR_Msk

/********************************* Bit definition for DAC_SR register ***********************************************/
#define DAC_SR_DMAUDR1_Pos                        (13U)
#define DAC_SR_DMAUDR1_Msk                        (0x1UL<<DAC_SR_DMAUDR1_Pos)                       /*!< 0x00002000 */
#define DAC_SR_DMAUDR1                            DAC_SR_DMAUDR1_Msk                                
#define DAC_SR_DMAUDR2_Pos                        (29U)
#define DAC_SR_DMAUDR2_Msk                        (0x1UL<<DAC_SR_DMAUDR2_Pos)                       /*!< 0x20000000 */
#define DAC_SR_DMAUDR2                            DAC_SR_DMAUDR2_Msk                                

/********************************* Bit definition for DAC_OC register ***********************************************/
#define DAC_OC_DAC_EXTEN_Pos                      (0U)
#define DAC_OC_DAC_EXTEN_Msk                      (0x3UL<<DAC_OC_DAC_EXTEN_Pos)                     /*!< 0x00000003 */
#define DAC_OC_DAC_EXTEN                          DAC_OC_DAC_EXTEN_Msk
#define DAC_OC_DAC_EXTEN_0                        (0x1UL<<DAC_OC_DAC_EXTEN_Pos)                     /*!< 0x00000001 */
#define DAC_OC_DAC_EXTEN_1                        (0x2UL<<DAC_OC_DAC_EXTEN_Pos)                     /*!< 0x00000002 */
#define DAC_OC_DAC_EXTSRC_CR_Pos                  (2U)
#define DAC_OC_DAC_EXTSRC_CR_Msk                  (0x1UL<<DAC_OC_DAC_EXTSRC_CR_Pos)                 /*!< 0x00000004 */
#define DAC_OC_DAC_EXTSRC_CR                      DAC_OC_DAC_EXTSRC_CR_Msk                          
#define DAC_OC_DAC_VREFSEL_Pos                    (3U)
#define DAC_OC_DAC_VREFSEL_Msk                    (0x1UL<<DAC_OC_DAC_VREFSEL_Pos)                  /*!< 0x00000008 */
#define DAC_OC_DAC_VREFSEL                        DAC_OC_DAC_VREFSEL_Msk                                                  
#define DAC_OC_DAC_INTER1_CR_Pos                  (5U)
#define DAC_OC_DAC_INTER1_CR_Msk                  (0x1UL<<DAC_OC_DAC_INTER1_CR_Pos)                 /*!< 0x00000020 */
#define DAC_OC_DAC_INTER1_CR                      DAC_OC_DAC_INTER1_CR_Msk                          
#define DAC_OC_DAC_INTER2_CR_Pos                  (6U)
#define DAC_OC_DAC_INTER2_CR_Msk                  (0x1UL<<DAC_OC_DAC_INTER2_CR_Pos)                 /*!< 0x00000040 */
#define DAC_OC_DAC_INTER2_CR                      DAC_OC_DAC_INTER2_CR_Msk                          
#define DAC_OC_DAC_CALMODE_Pos                    (7U)
#define DAC_OC_DAC_CALMODE_Msk                    (0x3UL<<DAC_OC_DAC_CALMODE_Pos)                   /*!< 0x00000180 */
#define DAC_OC_DAC_CALMODE                        DAC_OC_DAC_CALMODE_Msk
#define DAC_OC_DAC_CALMODE_0                      (0x1UL<<DAC_OC_DAC_CALMODE_Pos)                   /*!< 0x00000080 */
#define DAC_OC_DAC_CALMODE_1                      (0x2UL<<DAC_OC_DAC_CALMODE_Pos)                   /*!< 0x00000100 */
#define DAC_OC_DAC_EXTCH_CR_Pos                   (9U)
#define DAC_OC_DAC_EXTCH_CR_Msk                   (0x3UL<<DAC_OC_DAC_EXTCH_CR_Pos)                  /*!< 0x00000600 */
#define DAC_OC_DAC_EXTCH_CR                       DAC_OC_DAC_EXTCH_CR_Msk
#define DAC_OC_DAC_EXTCH_CR_0                     (0x1UL<<DAC_OC_DAC_EXTCH_CR_Pos)                  /*!< 0x00000200 */
#define DAC_OC_DAC_EXTCH_CR_1                     (0x2UL<<DAC_OC_DAC_EXTCH_CR_Pos)                  /*!< 0x00000400 */
#define DAC_OC_DAC_OS_TRIMCR_Pos                  (24U)
#define DAC_OC_DAC_OS_TRIMCR_Msk                  (0x3FUL<<DAC_OC_DAC_OS_TRIMCR_Pos)                /*!< 0x3F000000 */
#define DAC_OC_DAC_OS_TRIMCR                      DAC_OC_DAC_OS_TRIMCR_Msk
#define DAC_OC_DAC_OS_TRIMCR_0                    (0x1UL<<DAC_OC_DAC_OS_TRIMCR_Pos)                 /*!< 0x01000000 */
#define DAC_OC_DAC_OS_TRIMCR_1                    (0x2UL<<DAC_OC_DAC_OS_TRIMCR_Pos)                 /*!< 0x02000000 */
#define DAC_OC_DAC_OS_TRIMCR_2                    (0x4UL<<DAC_OC_DAC_OS_TRIMCR_Pos)                 /*!< 0x04000000 */
#define DAC_OC_DAC_OS_TRIMCR_3                    (0x8UL<<DAC_OC_DAC_OS_TRIMCR_Pos)                 /*!< 0x08000000 */
#define DAC_OC_DAC_OS_TRIMCR_4                    (0x10UL<<DAC_OC_DAC_OS_TRIMCR_Pos)                /*!< 0x10000000 */
#define DAC_OC_DAC_OS_TRIMCR_5                    (0x20UL<<DAC_OC_DAC_OS_TRIMCR_Pos)                /*!< 0x20000000 */

/********************************* Bit definition for DAC_RAMPCFGR1 register ****************************************/
#define DAC_RAMPCFGR1_RAMPREFS1_Pos               (0U)
#define DAC_RAMPCFGR1_RAMPREFS1_Msk               (0xFFFUL<<DAC_RAMPCFGR1_RAMPREFS1_Pos)            /*!< 0x00000FFF */
#define DAC_RAMPCFGR1_RAMPREFS1                   DAC_RAMPCFGR1_RAMPREFS1_Msk
#define DAC_RAMPCFGR1_RAMPHSTEPVALS1_Pos          (16U)
#define DAC_RAMPCFGR1_RAMPHSTEPVALS1_Msk          (0xFFFUL<<DAC_RAMPCFGR1_RAMPHSTEPVALS1_Pos)       /*!< 0x0FFF0000 */
#define DAC_RAMPCFGR1_RAMPHSTEPVALS1              DAC_RAMPCFGR1_RAMPHSTEPVALS1_Msk

/********************************* Bit definition for DAC_RAMPCFGR2 register ****************************************/
#define DAC_RAMPCFGR2_RAMPREFS2_Pos               (0U)
#define DAC_RAMPCFGR2_RAMPREFS2_Msk               (0xFFFUL<<DAC_RAMPCFGR2_RAMPREFS2_Pos)            /*!< 0x00000FFF */
#define DAC_RAMPCFGR2_RAMPREFS2                   DAC_RAMPCFGR2_RAMPREFS2_Msk
#define DAC_RAMPCFGR2_RAMPHSTEPVALS2_Pos          (16U)
#define DAC_RAMPCFGR2_RAMPHSTEPVALS2_Msk          (0xFFFUL<<DAC_RAMPCFGR2_RAMPHSTEPVALS2_Pos)       /*!< 0x0FFF0000 */
#define DAC_RAMPCFGR2_RAMPHSTEPVALS2              DAC_RAMPCFGR2_RAMPHSTEPVALS2_Msk

/********************************* Bit definition for DAC_RAMPDLYS register *****************************************/
#define DAC_RAMPDLYS_RAMPDELAY_EN1_Pos            (0U)
#define DAC_RAMPDLYS_RAMPDELAY_EN1_Msk            (0x1UL<<DAC_RAMPDLYS_RAMPDELAY_EN1_Pos)           /*!< 0x00000001 */
#define DAC_RAMPDLYS_RAMPDELAY_EN1                DAC_RAMPDLYS_RAMPDELAY_EN1_Msk                    
#define DAC_RAMPDLYS_RAMPDELAYDATA1_Pos           (1U)
#define DAC_RAMPDLYS_RAMPDELAYDATA1_Msk           (0xFFFUL<<DAC_RAMPDLYS_RAMPDELAYDATA1_Pos)        /*!< 0x00001FFE */
#define DAC_RAMPDLYS_RAMPDELAYDATA1               DAC_RAMPDLYS_RAMPDELAYDATA1_Msk
#define DAC_RAMPDLYS_RAMPDELAY_EN2_Pos            (16U)
#define DAC_RAMPDLYS_RAMPDELAY_EN2_Msk            (0x1UL<<DAC_RAMPDLYS_RAMPDELAY_EN2_Pos)           /*!< 0x00010000 */
#define DAC_RAMPDLYS_RAMPDELAY_EN2                DAC_RAMPDLYS_RAMPDELAY_EN2_Msk                    
#define DAC_RAMPDLYS_RAMPDELAYDATA2_Pos           (17U)
#define DAC_RAMPDLYS_RAMPDELAYDATA2_Msk           (0xFFFUL<<DAC_RAMPDLYS_RAMPDELAYDATA2_Pos)        /*!< 0x1FFE0000 */
#define DAC_RAMPDLYS_RAMPDELAYDATA2               DAC_RAMPDLYS_RAMPDELAYDATA2_Msk

/********************************* Bit definition for DAC_RAMPCR register *******************************************/
#define DAC_RAMPCR_RAMPLOADSEL1_Pos               (0U)
#define DAC_RAMPCR_RAMPLOADSEL1_Msk               (0x1UL<<DAC_RAMPCR_RAMPLOADSEL1_Pos)              /*!< 0x00000001 */
#define DAC_RAMPCR_RAMPLOADSEL1                   DAC_RAMPCR_RAMPLOADSEL1_Msk                       
#define DAC_RAMPCR_RAMPUPTRIGSEL1_Pos             (1U)
#define DAC_RAMPCR_RAMPUPTRIGSEL1_Msk             (0xFUL<<DAC_RAMPCR_RAMPUPTRIGSEL1_Pos)            /*!< 0x0000001E */
#define DAC_RAMPCR_RAMPUPTRIGSEL1                 DAC_RAMPCR_RAMPUPTRIGSEL1_Msk
#define DAC_RAMPCR_RAMPUPTRIGSEL1_0               (0x1UL<<DAC_RAMPCR_RAMPUPTRIGSEL1_Pos)            /*!< 0x00000002 */
#define DAC_RAMPCR_RAMPUPTRIGSEL1_1               (0x2UL<<DAC_RAMPCR_RAMPUPTRIGSEL1_Pos)            /*!< 0x00000004 */
#define DAC_RAMPCR_RAMPUPTRIGSEL1_2               (0x4UL<<DAC_RAMPCR_RAMPUPTRIGSEL1_Pos)            /*!< 0x00000008 */
#define DAC_RAMPCR_RAMPUPTRIGSEL1_3               (0x8UL<<DAC_RAMPCR_RAMPUPTRIGSEL1_Pos)            /*!< 0x00000010 */
#define DAC_RAMPCR_RAMPSTPTRIGSEL1_Pos            (5U)
#define DAC_RAMPCR_RAMPSTPTRIGSEL1_Msk            (0xFUL<<DAC_RAMPCR_RAMPSTPTRIGSEL1_Pos)           /*!< 0x00000180 */
#define DAC_RAMPCR_RAMPSTPTRIGSEL1                DAC_RAMPCR_RAMPSTPTRIGSEL1_Msk
#define DAC_RAMPCR_RAMPSTPTRIGSEL1_0              (0x1UL<<DAC_RAMPCR_RAMPSTPTRIGSEL1_Pos)           /*!< 0x00000080 */
#define DAC_RAMPCR_RAMPSTPTRIGSEL1_1              (0x2UL<<DAC_RAMPCR_RAMPSTPTRIGSEL1_Pos)           /*!< 0x00000100 */
#define DAC_RAMPCR_RAMPSTPTRIGSEL1_2              (0x4UL<<DAC_RAMPCR_RAMPSTPTRIGSEL1_Pos)           /*!< 0x00000200 */
#define DAC_RAMPCR_RAMPSTPTRIGSEL1_3              (0x8UL<<DAC_RAMPCR_RAMPSTPTRIGSEL1_Pos)           /*!< 0x00000400 */
#define DAC_RAMPCR_RAMPLOADSEL2_Pos               (16U)
#define DAC_RAMPCR_RAMPLOADSEL2_Msk               (0x1UL<<DAC_RAMPCR_RAMPLOADSEL2_Pos)              /*!< 0x00010000 */
#define DAC_RAMPCR_RAMPLOADSEL2                   DAC_RAMPCR_RAMPLOADSEL2_Msk                       
#define DAC_RAMPCR_RAMPUPTRIGSEL2_Pos             (17U)
#define DAC_RAMPCR_RAMPUPTRIGSEL2_Msk             (0xFUL<<DAC_RAMPCR_RAMPUPTRIGSEL2_Pos)            /*!< 0x001E0000 */
#define DAC_RAMPCR_RAMPUPTRIGSEL2                 DAC_RAMPCR_RAMPUPTRIGSEL2_Msk
#define DAC_RAMPCR_RAMPUPTRIGSEL2_0               (0x1UL<<DAC_RAMPCR_RAMPUPTRIGSEL2_Pos)            /*!< 0x00020000 */
#define DAC_RAMPCR_RAMPUPTRIGSEL2_1               (0x2UL<<DAC_RAMPCR_RAMPUPTRIGSEL2_Pos)            /*!< 0x00040000 */
#define DAC_RAMPCR_RAMPUPTRIGSEL2_2               (0x4UL<<DAC_RAMPCR_RAMPUPTRIGSEL2_Pos)            /*!< 0x00080000 */
#define DAC_RAMPCR_RAMPUPTRIGSEL2_3               (0x8UL<<DAC_RAMPCR_RAMPUPTRIGSEL2_Pos)            /*!< 0x00100000 */
#define DAC_RAMPCR_RAMPSTPTRIGSEL2_Pos            (21U)
#define DAC_RAMPCR_RAMPSTPTRIGSEL2_Msk            (0xFUL<<DAC_RAMPCR_RAMPSTPTRIGSEL2_Pos)           /*!< 0x01E00000 */
#define DAC_RAMPCR_RAMPSTPTRIGSEL2                DAC_RAMPCR_RAMPSTPTRIGSEL2_Msk
#define DAC_RAMPCR_RAMPSTPTRIGSEL2_0              (0x1UL<<DAC_RAMPCR_RAMPSTPTRIGSEL2_Pos)           /*!< 0x00200000 */
#define DAC_RAMPCR_RAMPSTPTRIGSEL2_1              (0x2UL<<DAC_RAMPCR_RAMPSTPTRIGSEL2_Pos)           /*!< 0x00400000 */
#define DAC_RAMPCR_RAMPSTPTRIGSEL2_2              (0x4UL<<DAC_RAMPCR_RAMPSTPTRIGSEL2_Pos)           /*!< 0x00800000 */
#define DAC_RAMPCR_RAMPSTPTRIGSEL2_3              (0x8UL<<DAC_RAMPCR_RAMPSTPTRIGSEL2_Pos)           /*!< 0x01000000 */

/********************************* Bit definition for DAC_CLKCR register ********************************************/
#define DAC_CLKCR_DACCLK_SETUP_Pos                (0U)
#define DAC_CLKCR_DACCLK_SETUP_Msk                (0x7UL<<DAC_CLKCR_DACCLK_SETUP_Pos)               /*!< 0x00000007 */
#define DAC_CLKCR_DACCLK_SETUP                    DAC_CLKCR_DACCLK_SETUP_Msk
#define DAC_CLKCR_DACCLK_SETUP_0                  (0x1UL<<DAC_CLKCR_DACCLK_SETUP_Pos)               /*!< 0x00000001 */
#define DAC_CLKCR_DACCLK_SETUP_1                  (0x2UL<<DAC_CLKCR_DACCLK_SETUP_Pos)               /*!< 0x00000002 */
#define DAC_CLKCR_DACCLK_SETUP_2                  (0x4UL<<DAC_CLKCR_DACCLK_SETUP_Pos)               /*!< 0x00000004 */
#define DAC_CLKCR_DACCLK_WIDTH_Pos                (3U)
#define DAC_CLKCR_DACCLK_WIDTH_Msk                (0x7UL<<DAC_CLKCR_DACCLK_WIDTH_Pos)               /*!< 0x00000038 */
#define DAC_CLKCR_DACCLK_WIDTH                    DAC_CLKCR_DACCLK_WIDTH_Msk
#define DAC_CLKCR_DACCLK_WIDTH_0                  (0x1UL<<DAC_CLKCR_DACCLK_WIDTH_Pos)               /*!< 0x00000008 */
#define DAC_CLKCR_DACCLK_WIDTH_1                  (0x2UL<<DAC_CLKCR_DACCLK_WIDTH_Pos)               /*!< 0x00000010 */
#define DAC_CLKCR_DACCLK_WIDTH_2                  (0x4UL<<DAC_CLKCR_DACCLK_WIDTH_Pos)               /*!< 0x00000020 */
#define DAC_CLKCR_DACCLK_HOLD_Pos                 (6U)
#define DAC_CLKCR_DACCLK_HOLD_Msk                 (0x7UL<<DAC_CLKCR_DACCLK_HOLD_Pos)                /*!< 0x000001C0 */
#define DAC_CLKCR_DACCLK_HOLD                     DAC_CLKCR_DACCLK_HOLD_Msk
#define DAC_CLKCR_DACCLK_HOLD_0                   (0x1UL<<DAC_CLKCR_DACCLK_HOLD_Pos)                /*!< 0x00000040 */
#define DAC_CLKCR_DACCLK_HOLD_1                   (0x2UL<<DAC_CLKCR_DACCLK_HOLD_Pos)                /*!< 0x00000080 */
#define DAC_CLKCR_DACCLK_HOLD_2                   (0x4UL<<DAC_CLKCR_DACCLK_HOLD_Pos)                /*!< 0x00000100 */

/********************************************************************************************************************/
/********************************** Analog Comparators (COMP)  ******************************************************/
/********************************************************************************************************************/

/**********************  Bit definition for COMP_CSR register  **************/
#define COMP_CSR_EN_Pos            (0U)
#define COMP_CSR_EN_Msk            (0x1UL << COMP_CSR_EN_Pos)                  /*!< 0x00000001 */
#define COMP_CSR_EN                COMP_CSR_EN_Msk                             /*!< Comparator enable */
#define COMP_CSR_COMP1_EN          COMP_CSR_EN
#define COMP_CSR_COMP2_EN          COMP_CSR_EN
#define COMP_CSR_COMP3_EN          COMP_CSR_EN
#define COMP_CSR_COMP4_EN          COMP_CSR_EN

#define COMP_CSR_INNSEL_Pos        (3U)
#define COMP_CSR_INNSEL_Msk        (0x3UL << COMP_CSR_INNSEL_Pos)              /*!< 0x00000018 */
#define COMP_CSR_INNSEL            COMP_CSR_INNSEL_Msk                         /*!< desc INNSEL */
#define COMP_CSR_INNSEL_0          (0x1UL << COMP_CSR_INNSEL_Pos)              /*!< 0x00000008 */
#define COMP_CSR_INNSEL_1          (0x2UL << COMP_CSR_INNSEL_Pos)              /*!< 0x00000010 */

#define COMP_CSR_INPSEL_Pos        (8U)
#define COMP_CSR_INPSEL_Msk        (0x7UL << COMP_CSR_INPSEL_Pos)              /*!< 0x00000300 */
#define COMP_CSR_INPSEL            COMP_CSR_INPSEL_Msk                         /*!< Comparator plus minus selection */
#define COMP_CSR_INPSEL_0		   (0x1UL << COMP_CSR_INPSEL_Pos)              /*!< 0x00000100 */
#define COMP_CSR_INPSEL_1		   (0x2UL << COMP_CSR_INPSEL_Pos)              /*!< 0x00000200 */ 
#define COMP_CSR_INPSEL_2          (0x4UL << COMP_CSR_INPSEL_Pos)              /*!< 0x00000400 */ 

#define COMP_CSR_BLANKSEL_Pos      (11U)
#define COMP_CSR_BLANKSEL_Msk      (0xFUL << COMP_CSR_BLANKSEL_Pos)            /*!< 0x001E0000 */
#define COMP_CSR_BLANKSEL          COMP_CSR_BLANKSEL_Msk                       /*!< Pair of comparators window mode. Bit intended to be used with COMP common instance (COMP_Common_TypeDef) */
#define COMP_CSR_BLANKSEL_0        (0x1UL << COMP_CSR_BLANKSEL_Pos)             /*!< 0x00000800 */
#define COMP_CSR_BLANKSEL_1        (0x2UL << COMP_CSR_BLANKSEL_Pos)             /*!< 0x00001000 */ 
#define COMP_CSR_BLANKSEL_2        (0x4UL << COMP_CSR_BLANKSEL_Pos)             /*!< 0x00002000 */ 
#define COMP_CSR_BLANKSEL_3        (0x8UL << COMP_CSR_BLANKSEL_Pos)             /*!< 0x00004000 */ 

#define COMP_CSR_POLARITY_Pos      (15U)
#define COMP_CSR_POLARITY_Msk      (0x1UL << COMP_CSR_POLARITY_Pos)            /*!< 0x00008000 */
#define COMP_CSR_POLARITY          COMP_CSR_POLARITY_Msk                       /*!< Comparator output polarity */

#define COMP_CSR_HYST_Pos          (16U)
#define COMP_CSR_HYST_Msk          (0x1UL << COMP_CSR_HYST_Pos)                /*!< 0x00010000 */
#define COMP_CSR_HYST              COMP_CSR_HYST_Msk                           /*!< Comparator hysteresis enable */

#define COMP_CSR_PWRMODE_Pos       (18U)
#define COMP_CSR_PWRMODE_Msk       (0x1UL << COMP_CSR_PWRMODE_Pos)             /*!< 0x00040000 */
#define COMP_CSR_PWRMODE           COMP_CSR_PWRMODE_Msk                        /*!< Comparator power mode */

#define COMP_CSR_WINMODE_Pos       (19U)
#define COMP_CSR_WINMODE_Msk       (0x1UL << COMP_CSR_WINMODE_Pos)             /*!< 0x00080000 */
#define COMP_CSR_WINMODE           COMP_CSR_WINMODE_Msk                        /*!< Pair of comparators window mode. Bit intended to be used with COMP common instance (COMP_Common_TypeDef) */

#define COMP_CSR_TIM_EXTI_OUT_SEL_Pos         (29U)
#define COMP_CSR_TIM_EXTI_OUT_SEL_Msk         (0x1UL << COMP_CSR_TIM_EXTI_OUT_SEL_Pos)	/*!< 0x02000000 */
#define COMP_CSR_TIM_EXTI_OUT_SEL             COMP_CSR_TIM_EXTI_OUT_SEL_Msk				/*!< COMP output to TIM/EXTI selection */

#define COMP_CSR_COMP_OUT_Pos       (30U)
#define COMP_CSR_COMP_OUT_Msk       (0x1UL << COMP_CSR_COMP_OUT_Pos)           /*!< 0x40000000 */
#define COMP_CSR_COMP_OUT           COMP_CSR_COMP_OUT_Msk                      /*!< COMP output status */

#define COMP_CSR_LOCK_Pos         (31U)
#define COMP_CSR_LOCK_Msk         (0x1UL << COMP_CSR_LOCK_Pos)                 /*!< 0x80000000 */
#define COMP_CSR_LOCK             COMP_CSR_LOCK_Msk                            /*!< desc COMP_OUT */

/**********************  Bit definition for COMP_FR register  ***************/
#define COMP_FR_FLTEN_Pos          (0U)
#define COMP_FR_FLTEN_Msk          (0x1UL << COMP_FR_FLTEN_Pos)                /*!< 0x00000001 */
#define COMP_FR_FLTEN              COMP_FR_FLTEN_Msk                           /*!< Comparator filter enable */
#define COMP_FR_FLTCNT_Pos         (16U)
#define COMP_FR_FLTCNT_Msk         (0xFFFFUL << COMP_FR_FLTCNT_Pos)            /*!< 0xFFFF0000 */
#define COMP_FR_FLTCNT             COMP_FR_FLTCNT_Msk                          /*!< Comparator filter counter */

/********************************************************************************************************************/
/********************************* OPA ******************************************************************************/
/********************************************************************************************************************/

/********************************* Bit definition for OPA_CSR register *********************************************/
#define OPA_CSR_OPAEN_Pos                   (0U)
#define OPA_CSR_OPAEN_Msk                   (0x1UL<<OPA_CSR_OPAEN_Pos)                     /*!< 0x00000001 */
#define OPA_CSR_OPAEN                       OPA_CSR_OPAEN_Msk     

#define OPA_CSR_VPSEL_Pos                   (2U)
#define OPA_CSR_VPSEL_Msk                   (0x1UL<<OPA_CSR_VPSEL_Pos)                  /*!< 0x00000004 */
#define OPA_CSR_VPSEL                       OPA_CSR_VPSEL_Msk

#define OPA_CSR_VPSEL_Pos                   (2U)
#define OPA_CSR_VPSEL_Msk                   (0x1UL<<OPA_CSR_VPSEL_Pos)                  /*!< 0x00000004 */
#define OPA_CSR_VPSEL                       OPA_CSR_VPSEL_Msk  

#define OPA_CSR_VNSEL_Pos                   (5U)
#define OPA_CSR_VNSEL_Msk                   (0x3UL<<OPA_CSR_VNSEL_Pos)                  /*!< 0x00000060 */
#define OPA_CSR_VNSEL                       OPA_CSR_VNSEL_Msk  
#define OPA_CSR_VNSEL_0                     (0x1UL<<OPA_CSR_VNSEL_Pos)                   /*!< 0x00000020 */
#define OPA_CSR_VNSEL_1                     (0x2UL<<OPA_CSR_VNSEL_Pos)                   /*!< 0x00000040 */   

#define OPA_CSR_INTOEN_Pos                  (8U)
#define OPA_CSR_INTOEN_Msk                  (0x1UL<<OPA_CSR_INTOEN_Pos)                 /*!< 0x00000100 */
#define OPA_CSR_INTOEN                      OPA_CSR_INTOEN_Msk   

#define OPA_CSR_EXTOEN_Pos                  (9U)
#define OPA_CSR_EXTOEN_Msk                  (0x1UL<<OPA_CSR_EXTOEN_Pos)                 /*!< 0x00000200 */
#define OPA_CSR_EXTOEN                      OPA_CSR_EXTOEN_Msk    

#define OPA_CSR_MODE_Pos                    (14U)
#define OPA_CSR_MODE_Msk                    (0x3UL<<OPA_CSR_MODE_Pos)                   /*!< 0x0000C000 */
#define OPA_CSR_MODE                        OPA_CSR_MODE_Msk
#define OPA_CSR_MODE_0                      (0x1UL<<OPA_CSR_MODE_Pos)                   /*!< 0x00004000 */
#define OPA_CSR_MODE_1                      (0x2UL<<OPA_CSR_MODE_Pos)                   /*!< 0x00008000 */

#define OPA_CSR_PGA_GAIN_Pos                (16U)
#define OPA_CSR_PGA_GAIN_Msk                (0xFUL<<OPA_CSR_PGA_GAIN_Pos)               /*!< 0x000F0000 */
#define OPA_CSR_PGA_GAIN                    OPA_CSR_PGA_GAIN_Msk
#define OPA_CSR_PGA_GAIN_0                  (0x1UL<<OPA_CSR_PGA_GAIN_Pos)               /*!< 0x00010000 */
#define OPA_CSR_PGA_GAIN_1                  (0x2UL<<OPA_CSR_PGA_GAIN_Pos)               /*!< 0x00020000 */
#define OPA_CSR_PGA_GAIN_2                  (0x4UL<<OPA_CSR_PGA_GAIN_Pos)               /*!< 0x00040000 */
#define OPA_CSR_PGA_GAIN_3                  (0x8UL<<OPA_CSR_PGA_GAIN_Pos)               /*!< 0x00080000 */

#define OPA_CSR_VBIAS_Pos                   (23U)
#define OPA_CSR_VBIAS_Msk                   (0xFUL<<OPA_CSR_VBIAS_Pos)                  /*!< 0x07800000 */
#define OPA_CSR_VBIAS                       OPA_CSR_VBIAS_Msk
#define OPA_CSR_VBIAS_0                     (0x1UL<<OPA_CSR_VBIAS_Pos)                  /*!< 0x00800000 */
#define OPA_CSR_VBIAS_1                     (0x2UL<<OPA_CSR_VBIAS_Pos)                  /*!< 0x01000000 */
#define OPA_CSR_VBIAS_2                     (0x4UL<<OPA_CSR_VBIAS_Pos)                  /*!< 0x02000000 */
#define OPA_CSR_VBIAS_3                     (0x8UL<<OPA_CSR_VBIAS_Pos)                  /*!< 0x04000000 */
   
#define OPA_CSR_VREF_SEL_Pos                (27U)
#define OPA_CSR_VREF_SEL_Msk                (0x1UL<<OPA_CSR_VREF_SEL_Pos)               /*!< 0x08000000 */
#define OPA_CSR_VREF_SEL                    OPA_CSR_VREF_SEL_Msk 

#define OPA_CSR_VBSEL_Pos                   (29U)
#define OPA_CSR_VBSEL_Msk                   (0x1UL<<OPA_CSR_VBSEL_Pos)                  /*!< 0x20000000 */
#define OPA_CSR_VBSEL                       OPA_CSR_VBSEL_Msk       

#define OPA_CSR_LOCK_Pos                    (31U)
#define OPA_CSR_LOCK_Msk                    (0x1UL<<OPA_CSR_LOCK_Pos)                   /*!< 0x80000000 */
#define OPA_CSR_LOCK                        OPA_CSR_LOCK_Msk         

/********************************************************************************************************************/
/********************************* TIM ******************************************************************************/
/********************************************************************************************************************/

/********************************* Bit definition for TIM_CR1 register **********************************************/
#define TIM_CR1_CEN_Pos                           (0U)
#define TIM_CR1_CEN_Msk                           (0x1UL<<TIM_CR1_CEN_Pos)                          /*!< 0x00000001 */
#define TIM_CR1_CEN                               TIM_CR1_CEN_Msk                                   
#define TIM_CR1_UDIS_Pos                          (1U)
#define TIM_CR1_UDIS_Msk                          (0x1UL<<TIM_CR1_UDIS_Pos)                         /*!< 0x00000002 */
#define TIM_CR1_UDIS                              TIM_CR1_UDIS_Msk                                  
#define TIM_CR1_URS_Pos                           (2U)
#define TIM_CR1_URS_Msk                           (0x1UL<<TIM_CR1_URS_Pos)                          /*!< 0x00000004 */
#define TIM_CR1_URS                               TIM_CR1_URS_Msk                                   
#define TIM_CR1_OPM_Pos                           (3U)
#define TIM_CR1_OPM_Msk                           (0x1UL<<TIM_CR1_OPM_Pos)                          /*!< 0x00000008 */
#define TIM_CR1_OPM                               TIM_CR1_OPM_Msk                                   
#define TIM_CR1_DIR_Pos                           (4U)
#define TIM_CR1_DIR_Msk                           (0x1UL<<TIM_CR1_DIR_Pos)                          /*!< 0x00000010 */
#define TIM_CR1_DIR                               TIM_CR1_DIR_Msk                                   
#define TIM_CR1_CMS_Pos                           (5U)
#define TIM_CR1_CMS_Msk                           (0x3UL<<TIM_CR1_CMS_Pos)                          /*!< 0x00000060 */
#define TIM_CR1_CMS                               TIM_CR1_CMS_Msk
#define TIM_CR1_CMS_0                             (0x1UL<<TIM_CR1_CMS_Pos)                          /*!< 0x00000020 */
#define TIM_CR1_CMS_1                             (0x2UL<<TIM_CR1_CMS_Pos)                          /*!< 0x00000040 */
#define TIM_CR1_ARPE_Pos                          (7U)
#define TIM_CR1_ARPE_Msk                          (0x1UL<<TIM_CR1_ARPE_Pos)                         /*!< 0x00000080 */
#define TIM_CR1_ARPE                              TIM_CR1_ARPE_Msk                                  
#define TIM_CR1_CKD_Pos                           (8U)
#define TIM_CR1_CKD_Msk                           (0x3UL<<TIM_CR1_CKD_Pos)                          /*!< 0x00000300 */
#define TIM_CR1_CKD                               TIM_CR1_CKD_Msk
#define TIM_CR1_CKD_0                             (0x1UL<<TIM_CR1_CKD_Pos)                          /*!< 0x00000100 */
#define TIM_CR1_CKD_1                             (0x2UL << TIM_CR1_CKD_Pos)                        /*!< 0x00000200 */

/********************************* Bit definition for TIM_CR2 register **********************************************/
#define TIM_CR2_CCPC_Pos                          (0U)
#define TIM_CR2_CCPC_Msk                          (0x1UL<<TIM_CR2_CCPC_Pos)                         /*!< 0x00000001 */
#define TIM_CR2_CCPC                              TIM_CR2_CCPC_Msk                                  
#define TIM_CR2_CCUS_Pos                          (2U)
#define TIM_CR2_CCUS_Msk                          (0x1UL<<TIM_CR2_CCUS_Pos)                         /*!< 0x00000004 */
#define TIM_CR2_CCUS                              TIM_CR2_CCUS_Msk                                  
#define TIM_CR2_CCDS_Pos                          (3U)
#define TIM_CR2_CCDS_Msk                          (0x1UL<<TIM_CR2_CCDS_Pos)                         /*!< 0x00000008 */
#define TIM_CR2_CCDS                              TIM_CR2_CCDS_Msk                                  
#define TIM_CR2_MMS_Pos                          (4U)
#define TIM_CR2_MMS_Msk                          (0x200007UL << TIM_CR2_MMS_Pos)               /*!< 0x02000070 */
#define TIM_CR2_MMS                              TIM_CR2_MMS_Msk
#define TIM_CR2_MMS_0                            (0x000001UL << TIM_CR2_MMS_Pos)               /*!< 0x00000010 */
#define TIM_CR2_MMS_1                            (0x000002UL << TIM_CR2_MMS_Pos)               /*!< 0x00000020 */
#define TIM_CR2_MMS_2                            (0x000004UL << TIM_CR2_MMS_Pos)               /*!< 0x00000040 */
#define TIM_CR2_MMS_3                            (0x200000UL << TIM_CR2_MMS_Pos)               /*!< 0x02000000 */
#define TIM_CR2_TI1S_Pos                          (7U)
#define TIM_CR2_TI1S_Msk                          (0x1UL<<TIM_CR2_TI1S_Pos)                         /*!< 0x00000080 */
#define TIM_CR2_TI1S                              TIM_CR2_TI1S_Msk                                  
#define TIM_CR2_OIS1_Pos                          (8U)
#define TIM_CR2_OIS1_Msk                          (0x1UL<<TIM_CR2_OIS1_Pos)                         /*!< 0x00000100 */
#define TIM_CR2_OIS1                              TIM_CR2_OIS1_Msk                                  
#define TIM_CR2_OIS1N_Pos                         (9U)
#define TIM_CR2_OIS1N_Msk                         (0x1UL<<TIM_CR2_OIS1N_Pos)                        /*!< 0x00000200 */
#define TIM_CR2_OIS1N                             TIM_CR2_OIS1N_Msk                                 
#define TIM_CR2_OIS2_Pos                          (10U)
#define TIM_CR2_OIS2_Msk                          (0x1UL<<TIM_CR2_OIS2_Pos)                         /*!< 0x00000400 */
#define TIM_CR2_OIS2                              TIM_CR2_OIS2_Msk                                  
#define TIM_CR2_OIS2N_Pos                         (11U)
#define TIM_CR2_OIS2N_Msk                         (0x1UL<<TIM_CR2_OIS2N_Pos)                        /*!< 0x00000800 */
#define TIM_CR2_OIS2N                             TIM_CR2_OIS2N_Msk                                 
#define TIM_CR2_OIS3_Pos                          (12U)
#define TIM_CR2_OIS3_Msk                          (0x1UL<<TIM_CR2_OIS3_Pos)                         /*!< 0x00001000 */
#define TIM_CR2_OIS3                              TIM_CR2_OIS3_Msk                                  
#define TIM_CR2_OIS3N_Pos                         (13U)
#define TIM_CR2_OIS3N_Msk                         (0x1UL<<TIM_CR2_OIS3N_Pos)                        /*!< 0x00002000 */
#define TIM_CR2_OIS3N                             TIM_CR2_OIS3N_Msk                                 
#define TIM_CR2_OIS4_Pos                          (14U)
#define TIM_CR2_OIS4_Msk                          (0x1UL<<TIM_CR2_OIS4_Pos)                         /*!< 0x00004000 */
#define TIM_CR2_OIS4                              TIM_CR2_OIS4_Msk                                  
#define TIM_CR2_OIS4N_Pos                         (15U)
#define TIM_CR2_OIS4N_Msk                         (0x1UL<<TIM_CR2_OIS4N_Pos)                        /*!< 0x00008000 */
#define TIM_CR2_OIS4N                             TIM_CR2_OIS4N_Msk                                 
#define TIM_CR2_OIS5_Pos                          (16U)
#define TIM_CR2_OIS5_Msk                          (0x1UL<<TIM_CR2_OIS5_Pos)                         /*!< 0x00010000 */
#define TIM_CR2_OIS5                              TIM_CR2_OIS5_Msk                                  
#define TIM_CR2_OIS6_Pos                          (18U)
#define TIM_CR2_OIS6_Msk                          (0x1UL<<TIM_CR2_OIS6_Pos)                         /*!< 0x00040000 */
#define TIM_CR2_OIS6                              TIM_CR2_OIS6_Msk                                  
#define TIM_CR2_MMS2_Pos                          (20U)
#define TIM_CR2_MMS2_Msk                          (0xFUL<<TIM_CR2_MMS2_Pos)                         /*!< 0x00F00000 */
#define TIM_CR2_MMS2                              TIM_CR2_MMS2_Msk
#define TIM_CR2_MMS2_0                            (0x1UL<<TIM_CR2_MMS2_Pos)                         /*!< 0x00100000 */
#define TIM_CR2_MMS2_1                            (0x2UL<<TIM_CR2_MMS2_Pos)                         /*!< 0x00200000 */
#define TIM_CR2_MMS2_2                            (0x4UL<<TIM_CR2_MMS2_Pos)                         /*!< 0x00400000 */
#define TIM_CR2_MMS2_3                            (0x8UL<<TIM_CR2_MMS2_Pos)                         /*!< 0x00800000 */


/********************************* Bit definition for TIM_SMCR register *********************************************/
#define TIM_SMCR_SMS_Pos                          (0U)
#define TIM_SMCR_SMS_Msk                         (0x00010007UL<<TIM_SMCR_SMS_Pos)                 /*!< 0x00010007 */
#define TIM_SMCR_SMS                             TIM_SMCR_SMS_Msk
#define TIM_SMCR_SMS_0                           (0x1UL<<TIM_SMCR_SMS_Pos)                        /*!< 0x00000001 */
#define TIM_SMCR_SMS_1                           (0x2UL<<TIM_SMCR_SMS_Pos)                        /*!< 0x00000002 */
#define TIM_SMCR_SMS_2                           (0x4UL<<TIM_SMCR_SMS_Pos)                        /*!< 0x00000004 */
#define TIM_SMCR_SMS_3                           (0x10000UL<<TIM_SMCR_SMS_Pos)                    /*!< 0x00010000 */
#define TIM_SMCR_OCCS_Pos                         (3U)
#define TIM_SMCR_OCCS_Msk                         (0x1UL<<TIM_SMCR_OCCS_Pos)                        /*!< 0x00000008 */
#define TIM_SMCR_OCCS                             TIM_SMCR_OCCS_Msk                                 
#define TIM_SMCR_TS_Pos                           (4U)
#define TIM_SMCR_TS_Msk                          (0x30007UL<<TIM_SMCR_TS_Pos)                     /*!< 0x00300070 */
#define TIM_SMCR_TS                              TIM_SMCR_TS_Msk
#define TIM_SMCR_TS_0                             (0x1UL<<TIM_SMCR_TS_Pos)                          /*!< 0x00000010 */
#define TIM_SMCR_TS_1                             (0x2UL<<TIM_SMCR_TS_Pos)                          /*!< 0x00000020 */
#define TIM_SMCR_TS_2                             (0x4UL<<TIM_SMCR_TS_Pos)                          /*!< 0x00000040 */
#define TIM_SMCR_TS_3                            (0x10000UL<<TIM_SMCR_TS_Pos)                     /*!< 0x00100000 */
#define TIM_SMCR_TS_4                            (0x20000UL<<TIM_SMCR_TS_Pos)                     /*!< 0x00200000 */
#define TIM_SMCR_MSM_Pos                          (7U)
#define TIM_SMCR_MSM_Msk                          (0x1UL<<TIM_SMCR_MSM_Pos)                         /*!< 0x00000080 */
#define TIM_SMCR_MSM                              TIM_SMCR_MSM_Msk                                  
#define TIM_SMCR_ETF_Pos                          (8U)
#define TIM_SMCR_ETF_Msk                          (0xFUL<<TIM_SMCR_ETF_Pos)                         /*!< 0x00000F00 */
#define TIM_SMCR_ETF                              TIM_SMCR_ETF_Msk
#define TIM_SMCR_ETF_0                            (0x1UL<<TIM_SMCR_ETF_Pos)                         /*!< 0x00000100 */
#define TIM_SMCR_ETF_1                            (0x2UL<<TIM_SMCR_ETF_Pos)                         /*!< 0x00000200 */
#define TIM_SMCR_ETF_2                            (0x4UL<<TIM_SMCR_ETF_Pos)                         /*!< 0x00000400 */
#define TIM_SMCR_ETF_3                            (0x8UL<<TIM_SMCR_ETF_Pos)                         /*!< 0x00000800 */
#define TIM_SMCR_ETPS_Pos                         (12U)
#define TIM_SMCR_ETPS_Msk                         (0x3UL<<TIM_SMCR_ETPS_Pos)                        /*!< 0x00003000 */
#define TIM_SMCR_ETPS                             TIM_SMCR_ETPS_Msk
#define TIM_SMCR_ETPS_0                           (0x1UL<<TIM_SMCR_ETPS_Pos)                        /*!< 0x00001000 */
#define TIM_SMCR_ETPS_1                           (0x2UL<<TIM_SMCR_ETPS_Pos)                        /*!< 0x00002000 */
#define TIM_SMCR_ECE_Pos                          (14U)
#define TIM_SMCR_ECE_Msk                          (0x1UL<<TIM_SMCR_ECE_Pos)                         /*!< 0x00004000 */
#define TIM_SMCR_ECE                              TIM_SMCR_ECE_Msk                                  
#define TIM_SMCR_ETP_Pos                          (15U)
#define TIM_SMCR_ETP_Msk                          (0x1UL<<TIM_SMCR_ETP_Pos)                         /*!< 0x00008000 */
#define TIM_SMCR_ETP                             TIM_SMCR_ETP_Msk                                

/********************************* Bit definition for TIM_DIER register *********************************************/
#define TIM_DIER_UIE_Pos                          (0U)
#define TIM_DIER_UIE_Msk                          (0x1UL<<TIM_DIER_UIE_Pos)                         /*!< 0x00000001 */
#define TIM_DIER_UIE                              TIM_DIER_UIE_Msk                                  
#define TIM_DIER_CC1IE_Pos                        (1U)
#define TIM_DIER_CC1IE_Msk                        (0x1UL<<TIM_DIER_CC1IE_Pos)                       /*!< 0x00000002 */
#define TIM_DIER_CC1IE                            TIM_DIER_CC1IE_Msk                                
#define TIM_DIER_CC2IE_Pos                        (2U)
#define TIM_DIER_CC2IE_Msk                        (0x1UL<<TIM_DIER_CC2IE_Pos)                       /*!< 0x00000004 */
#define TIM_DIER_CC2IE                            TIM_DIER_CC2IE_Msk                                
#define TIM_DIER_CC3IE_Pos                        (3U)
#define TIM_DIER_CC3IE_Msk                        (0x1UL<<TIM_DIER_CC3IE_Pos)                       /*!< 0x00000008 */
#define TIM_DIER_CC3IE                            TIM_DIER_CC3IE_Msk                                
#define TIM_DIER_CC4IE_Pos                        (4U)
#define TIM_DIER_CC4IE_Msk                        (0x1UL<<TIM_DIER_CC4IE_Pos)                       /*!< 0x00000010 */
#define TIM_DIER_CC4IE                            TIM_DIER_CC4IE_Msk                                
#define TIM_DIER_COMIE_Pos                        (5U)
#define TIM_DIER_COMIE_Msk                        (0x1UL<<TIM_DIER_COMIE_Pos)                       /*!< 0x00000020 */
#define TIM_DIER_COMIE                            TIM_DIER_COMIE_Msk                                
#define TIM_DIER_TIE_Pos                          (6U)
#define TIM_DIER_TIE_Msk                          (0x1UL<<TIM_DIER_TIE_Pos)                         /*!< 0x00000040 */
#define TIM_DIER_TIE                              TIM_DIER_TIE_Msk                                  
#define TIM_DIER_BIE_Pos                          (7U)
#define TIM_DIER_BIE_Msk                          (0x1UL<<TIM_DIER_BIE_Pos)                         /*!< 0x00000080 */
#define TIM_DIER_BIE                              TIM_DIER_BIE_Msk                                  
#define TIM_DIER_UDE_Pos                          (8U)
#define TIM_DIER_UDE_Msk                          (0x1UL<<TIM_DIER_UDE_Pos)                         /*!< 0x00000100 */
#define TIM_DIER_UDE                              TIM_DIER_UDE_Msk                                  
#define TIM_DIER_CC1DE_Pos                        (9U)
#define TIM_DIER_CC1DE_Msk                        (0x1UL<<TIM_DIER_CC1DE_Pos)                       /*!< 0x00000200 */
#define TIM_DIER_CC1DE                            TIM_DIER_CC1DE_Msk                                
#define TIM_DIER_CC2DE_Pos                        (10U)
#define TIM_DIER_CC2DE_Msk                        (0x1UL<<TIM_DIER_CC2DE_Pos)                       /*!< 0x00000400 */
#define TIM_DIER_CC2DE                            TIM_DIER_CC2DE_Msk                                
#define TIM_DIER_CC3DE_Pos                        (11U)
#define TIM_DIER_CC3DE_Msk                        (0x1UL<<TIM_DIER_CC3DE_Pos)                       /*!< 0x00000800 */
#define TIM_DIER_CC3DE                            TIM_DIER_CC3DE_Msk                                
#define TIM_DIER_CC4DE_Pos                        (12U)
#define TIM_DIER_CC4DE_Msk                        (0x1UL<<TIM_DIER_CC4DE_Pos)                       /*!< 0x00001000 */
#define TIM_DIER_CC4DE                            TIM_DIER_CC4DE_Msk                                
#define TIM_DIER_COMDE_Pos                        (13U)
#define TIM_DIER_COMDE_Msk                        (0x1UL<<TIM_DIER_COMDE_Pos)                       /*!< 0x00002000 */
#define TIM_DIER_COMDE                            TIM_DIER_COMDE_Msk                                
#define TIM_DIER_TDE_Pos                          (14U)
#define TIM_DIER_TDE_Msk                          (0x1UL<<TIM_DIER_TDE_Pos)                         /*!< 0x00004000 */
#define TIM_DIER_TDE                             TIM_DIER_TDE_Msk                              /*!<Trigger DMA request enable */       
#define TIM_DIER_IDXIE_Pos                       (20U)
#define TIM_DIER_IDXIE_Msk                       (0x1UL<<TIM_DIER_IDXIE_Pos)                      /*!< 0x00100000 */
#define TIM_DIER_IDXIE                           TIM_DIER_IDXIE_Msk                               
#define TIM_DIER_DIRIE_Pos                       (21U)
#define TIM_DIER_DIRIE_Msk                       (0x1UL<<TIM_DIER_DIRIE_Pos)                      /*!< 0x00200000 */
#define TIM_DIER_DIRIE                           TIM_DIER_DIRIE_Msk                               
#define TIM_DIER_IERRIE_Pos                      (22U)
#define TIM_DIER_IERRIE_Msk                      (0x1UL<<TIM_DIER_IERRIE_Pos)                     /*!< 0x00400000 */
#define TIM_DIER_IERRIE                          TIM_DIER_IERRIE_Msk                              
#define TIM_DIER_TERRIE_Pos                      (23U)
#define TIM_DIER_TERRIE_Msk                      (0x1UL<<TIM_DIER_TERRIE_Pos)                     /*!< 0x00800000 */
#define TIM_DIER_TERRIE                          TIM_DIER_TERRIE_Msk                              
/********************************* Bit definition for TIM_SR register ***********************************************/
#define TIM_SR_UIF_Pos                            (0U)
#define TIM_SR_UIF_Msk                            (0x1UL<<TIM_SR_UIF_Pos)                           /*!< 0x00000001 */
#define TIM_SR_UIF                                TIM_SR_UIF_Msk                                    
#define TIM_SR_CC1IF_Pos                          (1U)
#define TIM_SR_CC1IF_Msk                          (0x1UL<<TIM_SR_CC1IF_Pos)                         /*!< 0x00000002 */
#define TIM_SR_CC1IF                              TIM_SR_CC1IF_Msk                                  
#define TIM_SR_CC2IF_Pos                          (2U)
#define TIM_SR_CC2IF_Msk                          (0x1UL<<TIM_SR_CC2IF_Pos)                         /*!< 0x00000004 */
#define TIM_SR_CC2IF                              TIM_SR_CC2IF_Msk                                  
#define TIM_SR_CC3IF_Pos                          (3U)
#define TIM_SR_CC3IF_Msk                          (0x1UL<<TIM_SR_CC3IF_Pos)                         /*!< 0x00000008 */
#define TIM_SR_CC3IF                              TIM_SR_CC3IF_Msk                                  
#define TIM_SR_CC4IF_Pos                          (4U)
#define TIM_SR_CC4IF_Msk                          (0x1UL<<TIM_SR_CC4IF_Pos)                         /*!< 0x00000010 */
#define TIM_SR_CC4IF                              TIM_SR_CC4IF_Msk                                  
#define TIM_SR_COMIF_Pos                          (5U)
#define TIM_SR_COMIF_Msk                          (0x1UL<<TIM_SR_COMIF_Pos)                         /*!< 0x00000020 */
#define TIM_SR_COMIF                              TIM_SR_COMIF_Msk                                  
#define TIM_SR_TIF_Pos                            (6U)
#define TIM_SR_TIF_Msk                            (0x1UL<<TIM_SR_TIF_Pos)                           /*!< 0x00000040 */
#define TIM_SR_TIF                                TIM_SR_TIF_Msk                                    
#define TIM_SR_BIF_Pos                            (7U)
#define TIM_SR_BIF_Msk                            (0x1UL<<TIM_SR_BIF_Pos)                           /*!< 0x00000080 */
#define TIM_SR_BIF                                TIM_SR_BIF_Msk                                    
#define TIM_SR_B2IF_Pos                           (8U)
#define TIM_SR_B2IF_Msk                           (0x1UL<<TIM_SR_B2IF_Pos)                          /*!< 0x00000100 */
#define TIM_SR_B2IF                               TIM_SR_B2IF_Msk                                   
#define TIM_SR_CC1OF_Pos                          (9U)
#define TIM_SR_CC1OF_Msk                          (0x1UL<<TIM_SR_CC1OF_Pos)                         /*!< 0x00000200 */
#define TIM_SR_CC1OF                              TIM_SR_CC1OF_Msk                                  
#define TIM_SR_CC2OF_Pos                          (10U)
#define TIM_SR_CC2OF_Msk                          (0x1UL<<TIM_SR_CC2OF_Pos)                         /*!< 0x00000400 */
#define TIM_SR_CC2OF                              TIM_SR_CC2OF_Msk                                  
#define TIM_SR_CC3OF_Pos                          (11U)
#define TIM_SR_CC3OF_Msk                          (0x1UL<<TIM_SR_CC3OF_Pos)                         /*!< 0x00000800 */
#define TIM_SR_CC3OF                              TIM_SR_CC3OF_Msk                                  
#define TIM_SR_CC4OF_Pos                          (12U)
#define TIM_SR_CC4OF_Msk                          (0x1UL<<TIM_SR_CC4OF_Pos)                         /*!< 0x00001000 */
#define TIM_SR_CC4OF                              TIM_SR_CC4OF_Msk                                  
#define TIM_SR_SBIF_Pos                           (13U)
#define TIM_SR_SBIF_Msk                           (0x1UL<<TIM_SR_SBIF_Pos)                          /*!< 0x00002000 */
#define TIM_SR_SBIF                               TIM_SR_SBIF_Msk                                   
#define TIM_SR_CC5IF_Pos                          (16U)
#define TIM_SR_CC5IF_Msk                          (0x1UL<<TIM_SR_CC5IF_Pos)                         /*!< 0x00010000 */
#define TIM_SR_CC5IF                              TIM_SR_CC5IF_Msk                                  
#define TIM_SR_CC6IF_Pos                          (17U)
#define TIM_SR_CC6IF_Msk                          (0x1UL<<TIM_SR_CC6IF_Pos)                         /*!< 0x00020000 */
#define TIM_SR_CC6IF                              TIM_SR_CC6IF_Msk                                  
#define TIM_SR_IC1IR_Pos                          (18U)
#define TIM_SR_IC1IR_Msk                          (0x1UL<<TIM_SR_IC1IR_Pos)                         /*!< 0x00040000 */
#define TIM_SR_IC1IR                              TIM_SR_IC1IR_Msk                                  
#define TIM_SR_IC2IR_Pos                          (19U)
#define TIM_SR_IC2IR_Msk                          (0x1UL<<TIM_SR_IC2IR_Pos)                         /*!< 0x00080000 */
#define TIM_SR_IC2IR                             TIM_SR_IC2IR_Msk                                                              
#define TIM_SR_IDXF_Pos                          (20U)
#define TIM_SR_IDXF_Msk                          (0x1UL<<TIM_SR_IDXF_Pos)                         /*!< 0x00100000 */
#define TIM_SR_IDXF                              TIM_SR_IDXF_Msk                                  
#define TIM_SR_DIRF_Pos                          (21U)
#define TIM_SR_DIRF_Msk                          (0x1UL<<TIM_SR_DIRF_Pos)                         /*!< 0x00200000 */
#define TIM_SR_DIRF                              TIM_SR_DIRF_Msk                                  
#define TIM_SR_IERRF_Pos                         (22U)
#define TIM_SR_IERRF_Msk                         (0x1UL<<TIM_SR_IERRF_Pos)                        /*!< 0x00400000 */
#define TIM_SR_IERRF                             TIM_SR_IERRF_Msk                                 
#define TIM_SR_TERRF_Pos                         (23U)
#define TIM_SR_TERRF_Msk                         (0x1UL<<TIM_SR_TERRF_Pos)                        /*!< 0x00800000 */
#define TIM_SR_TERRF                             TIM_SR_TERRF_Msk                                 
#define TIM_SR_IC3IR_Pos                         (24U)
#define TIM_SR_IC3IR_Msk                          (0x1UL<<TIM_SR_IC3IR_Pos)                         /*!< 0x01000000 */
#define TIM_SR_IC3IR                              TIM_SR_IC3IR_Msk                                  
#define TIM_SR_IC4IR_Pos                          (25U)
#define TIM_SR_IC4IR_Msk                          (0x1UL<<TIM_SR_IC4IR_Pos)                         /*!< 0x02000000 */
#define TIM_SR_IC4IR                              TIM_SR_IC4IR_Msk                                  
#define TIM_SR_IC1IF_Pos                          (26U)
#define TIM_SR_IC1IF_Msk                          (0x1UL<<TIM_SR_IC1IF_Pos)                         /*!< 0x04000000 */
#define TIM_SR_IC1IF                              TIM_SR_IC1IF_Msk                                  
#define TIM_SR_IC2IF_Pos                          (27U)
#define TIM_SR_IC2IF_Msk                          (0x1UL<<TIM_SR_IC2IF_Pos)                         /*!< 0x08000000 */
#define TIM_SR_IC2IF                              TIM_SR_IC2IF_Msk                                  
#define TIM_SR_IC3IF_Pos                          (28U)
#define TIM_SR_IC3IF_Msk                          (0x1UL<<TIM_SR_IC3IF_Pos)                         /*!< 0x10000000 */
#define TIM_SR_IC3IF                              TIM_SR_IC3IF_Msk                                  
#define TIM_SR_IC4IF_Pos                          (29U)
#define TIM_SR_IC4IF_Msk                          (0x1UL<<TIM_SR_IC4IF_Pos)                         /*!< 0x20000000 */
#define TIM_SR_IC4IF                              TIM_SR_IC4IF_Msk                                  

/********************************* Bit definition for TIM_EGR register **********************************************/
#define TIM_EGR_UG_Pos                            (0U)
#define TIM_EGR_UG_Msk                            (0x1UL<<TIM_EGR_UG_Pos)                           /*!< 0x00000001 */
#define TIM_EGR_UG                                TIM_EGR_UG_Msk                                    
#define TIM_EGR_CC1G_Pos                          (1U)
#define TIM_EGR_CC1G_Msk                          (0x1UL<<TIM_EGR_CC1G_Pos)                         /*!< 0x00000002 */
#define TIM_EGR_CC1G                              TIM_EGR_CC1G_Msk                                  
#define TIM_EGR_CC2G_Pos                          (2U)
#define TIM_EGR_CC2G_Msk                          (0x1UL<<TIM_EGR_CC2G_Pos)                         /*!< 0x00000004 */
#define TIM_EGR_CC2G                              TIM_EGR_CC2G_Msk                                  
#define TIM_EGR_CC3G_Pos                          (3U)
#define TIM_EGR_CC3G_Msk                          (0x1UL<<TIM_EGR_CC3G_Pos)                         /*!< 0x00000008 */
#define TIM_EGR_CC3G                              TIM_EGR_CC3G_Msk                                  
#define TIM_EGR_CC4G_Pos                          (4U)
#define TIM_EGR_CC4G_Msk                          (0x1UL<<TIM_EGR_CC4G_Pos)                         /*!< 0x00000010 */
#define TIM_EGR_CC4G                              TIM_EGR_CC4G_Msk                                  
#define TIM_EGR_COMG_Pos                          (5U)
#define TIM_EGR_COMG_Msk                          (0x1UL<<TIM_EGR_COMG_Pos)                         /*!< 0x00000020 */
#define TIM_EGR_COMG                              TIM_EGR_COMG_Msk                                  
#define TIM_EGR_TG_Pos                            (6U)
#define TIM_EGR_TG_Msk                            (0x1UL<<TIM_EGR_TG_Pos)                           /*!< 0x00000040 */
#define TIM_EGR_TG                                TIM_EGR_TG_Msk                                    
#define TIM_EGR_BG_Pos                            (7U)
#define TIM_EGR_BG_Msk                            (0x1UL<<TIM_EGR_BG_Pos)                           /*!< 0x00000080 */
#define TIM_EGR_BG                                TIM_EGR_BG_Msk                                    
#define TIM_EGR_B2G_Pos                           (8U)
#define TIM_EGR_B2G_Msk                           (0x1UL<<TIM_EGR_B2G_Pos)                          /*!< 0x00000100 */
#define TIM_EGR_B2G                               TIM_EGR_B2G_Msk                                   

/********************************* Bit definition for TIM_CCMR1 register *******************************************/
#define TIM_CCMR1_CC1S_Pos                       (0U)
#define TIM_CCMR1_CC1S_Msk                       (0x3UL<<TIM_CCMR1_CC1S_Pos)                      /*!< 0x00000003 */
#define TIM_CCMR1_CC1S                           TIM_CCMR1_CC1S_Msk
#define TIM_CCMR1_CC1S_0                         (0x1UL<<TIM_CCMR1_CC1S_Pos)                      /*!< 0x00000001 */
#define TIM_CCMR1_CC1S_1                         (0x2UL<<TIM_CCMR1_CC1S_Pos)                      /*!< 0x00000002 */
#define TIM_CCMR1_OC1FE_Pos                      (2U)
#define TIM_CCMR1_OC1FE_Msk                      (0x1UL<<TIM_CCMR1_OC1FE_Pos)                     /*!< 0x00000004 */
#define TIM_CCMR1_OC1FE                          TIM_CCMR1_OC1FE_Msk                              
#define TIM_CCMR1_OC1PE_Pos                      (3U)
#define TIM_CCMR1_OC1PE_Msk                      (0x1UL<<TIM_CCMR1_OC1PE_Pos)                     /*!< 0x00000008 */
#define TIM_CCMR1_OC1PE                          TIM_CCMR1_OC1PE_Msk                              
#define TIM_CCMR1_OC1M_Pos                       (4U)
#define TIM_CCMR1_OC1M_Msk                       (0x1007UL<<TIM_CCMR1_OC1M_Pos)                   /*!< 0x00010070 */
#define TIM_CCMR1_OC1M                           TIM_CCMR1_OC1M_Msk
#define TIM_CCMR1_OC1M_0                         (0x1UL<<TIM_CCMR1_OC1M_Pos)                      /*!< 0x00000010 */
#define TIM_CCMR1_OC1M_1                         (0x2UL<<TIM_CCMR1_OC1M_Pos)                      /*!< 0x00000020 */
#define TIM_CCMR1_OC1M_2                         (0x4UL<<TIM_CCMR1_OC1M_Pos)                      /*!< 0x00000040 */
#define TIM_CCMR1_OC1M_3                         (0x1000UL<<TIM_CCMR1_OC1M_Pos)                   /*!< 0x00010000 */
#define TIM_CCMR1_OC1CE_Pos                      (7U)
#define TIM_CCMR1_OC1CE_Msk                      (0x1UL<<TIM_CCMR1_OC1CE_Pos)                     /*!< 0x00000080 */
#define TIM_CCMR1_OC1CE                          TIM_CCMR1_OC1CE_Msk                              
#define TIM_CCMR1_CC2S_Pos                       (8U)
#define TIM_CCMR1_CC2S_Msk                       (0x3UL<<TIM_CCMR1_CC2S_Pos)                      /*!< 0x00000300 */
#define TIM_CCMR1_CC2S                           TIM_CCMR1_CC2S_Msk
#define TIM_CCMR1_CC2S_0                         (0x1UL<<TIM_CCMR1_CC2S_Pos)                      /*!< 0x00000100 */
#define TIM_CCMR1_CC2S_1                         (0x2UL<<TIM_CCMR1_CC2S_Pos)                      /*!< 0x00000200 */
#define TIM_CCMR1_OC2FE_Pos                      (10U)
#define TIM_CCMR1_OC2FE_Msk                      (0x1UL<<TIM_CCMR1_OC2FE_Pos)                     /*!< 0x00000400 */
#define TIM_CCMR1_OC2FE                          TIM_CCMR1_OC2FE_Msk                              
#define TIM_CCMR1_OC2PE_Pos                      (11U)
#define TIM_CCMR1_OC2PE_Msk                      (0x1UL<<TIM_CCMR1_OC2PE_Pos)                     /*!< 0x00000800 */
#define TIM_CCMR1_OC2PE                          TIM_CCMR1_OC2PE_Msk                              
#define TIM_CCMR1_OC2M_Pos                       (12U)
#define TIM_CCMR1_OC2M_Msk                       (0x1007UL<<TIM_CCMR1_OC2M_Pos)                   /*!< 0x01007000 */
#define TIM_CCMR1_OC2M                           TIM_CCMR1_OC2M_Msk
#define TIM_CCMR1_OC2M_0                         (0x1UL<<TIM_CCMR1_OC2M_Pos)                      /*!< 0x00001000 */
#define TIM_CCMR1_OC2M_1                         (0x2UL<<TIM_CCMR1_OC2M_Pos)                      /*!< 0x00002000 */
#define TIM_CCMR1_OC2M_2                         (0x4UL<<TIM_CCMR1_OC2M_Pos)                      /*!< 0x00004000 */
#define TIM_CCMR1_OC2M_3                         (0x1000UL<<TIM_CCMR1_OC2M_Pos)                   /*!< 0x01000000 */
#define TIM_CCMR1_OC2CE_Pos                      (15U)
#define TIM_CCMR1_OC2CE_Msk                      (0x1UL<<TIM_CCMR1_OC2CE_Pos)                     /*!< 0x00008000 */
#define TIM_CCMR1_OC2CE                          TIM_CCMR1_OC2CE_Msk                              
/*---------------------------------------------------------------------------*/
#define TIM_CCMR1_IC1PSC_Pos                     (2U)
#define TIM_CCMR1_IC1PSC_Msk                     (0x3UL<<TIM_CCMR1_IC1PSC_Pos)                    /*!< 0x0000000C */
#define TIM_CCMR1_IC1PSC                         TIM_CCMR1_IC1PSC_Msk
#define TIM_CCMR1_IC1PSC_0                       (0x1UL<<TIM_CCMR1_IC1PSC_Pos)                    /*!< 0x00000004 */
#define TIM_CCMR1_IC1PSC_1                       (0x2UL<<TIM_CCMR1_IC1PSC_Pos)                    /*!< 0x00000008 */
#define TIM_CCMR1_IC1F_Pos                       (4U)
#define TIM_CCMR1_IC1F_Msk                       (0xFUL<<TIM_CCMR1_IC1F_Pos)                      /*!< 0x000000F0 */
#define TIM_CCMR1_IC1F                           TIM_CCMR1_IC1F_Msk
#define TIM_CCMR1_IC1F_0                         (0x1UL<<TIM_CCMR1_IC1F_Pos)                      /*!< 0x00000010 */
#define TIM_CCMR1_IC1F_1                         (0x2UL<<TIM_CCMR1_IC1F_Pos)                      /*!< 0x00000020 */
#define TIM_CCMR1_IC1F_2                         (0x4UL<<TIM_CCMR1_IC1F_Pos)                      /*!< 0x00000040 */
#define TIM_CCMR1_IC1F_3                         (0x8UL<<TIM_CCMR1_IC1F_Pos)                      /*!< 0x00000080 */

#define TIM_CCMR1_IC2PSC_Pos                     (10U)
#define TIM_CCMR1_IC2PSC_Msk                     (0x3UL<<TIM_CCMR1_IC2PSC_Pos)                    /*!< 0x00000C00 */
#define TIM_CCMR1_IC2PSC                         TIM_CCMR1_IC2PSC_Msk
#define TIM_CCMR1_IC2PSC_0                       (0x1UL<<TIM_CCMR1_IC2PSC_Pos)                    /*!< 0x00000400 */
#define TIM_CCMR1_IC2PSC_1                       (0x2UL<<TIM_CCMR1_IC2PSC_Pos)                    /*!< 0x00000800 */
#define TIM_CCMR1_IC2F_Pos                       (12U)
#define TIM_CCMR1_IC2F_Msk                       (0xFUL<<TIM_CCMR1_IC2F_Pos)                      /*!< 0x0000F000 */
#define TIM_CCMR1_IC2F                           TIM_CCMR1_IC2F_Msk
#define TIM_CCMR1_IC2F_0                         (0x1UL<<TIM_CCMR1_IC2F_Pos)                      /*!< 0x00001000 */
#define TIM_CCMR1_IC2F_1                         (0x2UL<<TIM_CCMR1_IC2F_Pos)                      /*!< 0x00002000 */
#define TIM_CCMR1_IC2F_2                         (0x4UL<<TIM_CCMR1_IC2F_Pos)                      /*!< 0x00004000 */
#define TIM_CCMR1_IC2F_3                         (0x8UL<<TIM_CCMR1_IC2F_Pos)                      /*!< 0x00008000 */

/********************************* Bit definition for TIM_CCMR2 register ********************************************/
#define TIM_CCMR2_CC3S_Pos                        (0U)
#define TIM_CCMR2_CC3S_Msk                        (0x3UL<<TIM_CCMR2_CC3S_Pos)                       /*!< 0x00000003 */
#define TIM_CCMR2_CC3S                            TIM_CCMR2_CC3S_Msk
#define TIM_CCMR2_CC3S_0                          (0x1UL<<TIM_CCMR2_CC3S_Pos)                       /*!< 0x00000001 */
#define TIM_CCMR2_CC3S_1                          (0x2UL<<TIM_CCMR2_CC3S_Pos)                       /*!< 0x00000002 */
#define TIM_CCMR2_OC3FE_Pos                       (2U)
#define TIM_CCMR2_OC3FE_Msk                       (0x1UL<<TIM_CCMR2_OC3FE_Pos)                      /*!< 0x00000004 */
#define TIM_CCMR2_OC3FE                           TIM_CCMR2_OC3FE_Msk                               
#define TIM_CCMR2_OC3PE_Pos                       (3U)
#define TIM_CCMR2_OC3PE_Msk                       (0x1UL<<TIM_CCMR2_OC3PE_Pos)                      /*!< 0x00000008 */
#define TIM_CCMR2_OC3PE                           TIM_CCMR2_OC3PE_Msk                               
#define TIM_CCMR2_OC3M_Pos                        (4U)
#define TIM_CCMR2_OC3M_Msk                        (0x1007UL<<TIM_CCMR2_OC3M_Pos)                    /*!< 0x00000070 */
#define TIM_CCMR2_OC3M                            TIM_CCMR2_OC3M_Msk
#define TIM_CCMR2_OC3M_0                          (0x1UL<<TIM_CCMR2_OC3M_Pos)                       /*!< 0x00000010 */
#define TIM_CCMR2_OC3M_1                          (0x2UL<<TIM_CCMR2_OC3M_Pos)                       /*!< 0x00000020 */
#define TIM_CCMR2_OC3M_2                          (0x4UL<<TIM_CCMR2_OC3M_Pos)                       /*!< 0x00000040 */
#define TIM_CCMR2_OC3M_3                          (0x1000UL<<TIM_CCMR2_OC3M_Pos)                    /*!< 0x00010000 */
#define TIM_CCMR2_OC3CE_Pos                       (7U)
#define TIM_CCMR2_OC3CE_Msk                       (0x1UL<<TIM_CCMR2_OC3CE_Pos)                      /*!< 0x00000080 */
#define TIM_CCMR2_OC3CE                           TIM_CCMR2_OC3CE_Msk                               
#define TIM_CCMR2_CC4S_Pos                        (8U)
#define TIM_CCMR2_CC4S_Msk                        (0x3UL<<TIM_CCMR2_CC4S_Pos)                       /*!< 0x00000300 */
#define TIM_CCMR2_CC4S                            TIM_CCMR2_CC4S_Msk
#define TIM_CCMR2_CC4S_0                          (0x1UL<<TIM_CCMR2_CC4S_Pos)                       /*!< 0x00000100 */
#define TIM_CCMR2_CC4S_1                          (0x2UL<<TIM_CCMR2_CC4S_Pos)                       /*!< 0x00000200 */
#define TIM_CCMR2_OC4FE_Pos                       (10U)
#define TIM_CCMR2_OC4FE_Msk                       (0x1UL<<TIM_CCMR2_OC4FE_Pos)                      /*!< 0x00000400 */
#define TIM_CCMR2_OC4FE                           TIM_CCMR2_OC4FE_Msk                               
#define TIM_CCMR2_OC4PE_Pos                       (11U)
#define TIM_CCMR2_OC4PE_Msk                       (0x1UL<<TIM_CCMR2_OC4PE_Pos)                      /*!< 0x00000800 */
#define TIM_CCMR2_OC4PE                           TIM_CCMR2_OC4PE_Msk                               
#define TIM_CCMR2_OC4M_Pos                        (12U)
#define TIM_CCMR2_OC4M_Msk                        (0x1007UL<<TIM_CCMR2_OC4M_Pos)                    /*!< 0x01007000 */
#define TIM_CCMR2_OC4M                            TIM_CCMR2_OC4M_Msk
#define TIM_CCMR2_OC4M_0                          (0x1UL<<TIM_CCMR2_OC4M_Pos)                       /*!< 0x00001000 */
#define TIM_CCMR2_OC4M_1                          (0x2UL<<TIM_CCMR2_OC4M_Pos)                       /*!< 0x00002000 */
#define TIM_CCMR2_OC4M_2                          (0x4UL<<TIM_CCMR2_OC4M_Pos)                       /*!< 0x00004000 */
#define TIM_CCMR2_OC4M_3                          (0x1000UL<<TIM_CCMR2_OC4M_Pos)                    /*!< 0x01000000 */
#define TIM_CCMR2_OC4CE_Pos                       (15U)
#define TIM_CCMR2_OC4CE_Msk                       (0x1UL<<TIM_CCMR2_OC4CE_Pos)                      /*!< 0x00008000 */
#define TIM_CCMR2_OC4CE                           TIM_CCMR2_OC4CE_Msk                               

/*---------------------------------------------------------------------------*/
#define TIM_CCMR2_IC3PSC_Pos                     (2U)
#define TIM_CCMR2_IC3PSC_Msk                      (0x3UL<<TIM_CCMR2_IC3PSC_Pos)                     /*!< 0x0000000C */
#define TIM_CCMR2_IC3PSC                          TIM_CCMR2_IC3PSC_Msk
#define TIM_CCMR2_IC3PSC_0                        (0x1UL<<TIM_CCMR2_IC3PSC_Pos)                     /*!< 0x00000004 */
#define TIM_CCMR2_IC3PSC_1                        (0x2UL<<TIM_CCMR2_IC3PSC_Pos)                     /*!< 0x00000008 */
#define TIM_CCMR2_IC3F_Pos                        (4U)
#define TIM_CCMR2_IC3F_Msk                        (0xFUL<<TIM_CCMR2_IC3F_Pos)                       /*!< 0x000000F0 */
#define TIM_CCMR2_IC3F                            TIM_CCMR2_IC3F_Msk
#define TIM_CCMR2_IC3F_0                          (0x1UL<<TIM_CCMR2_IC3F_Pos)                       /*!< 0x00000010 */
#define TIM_CCMR2_IC3F_1                          (0x2UL<<TIM_CCMR2_IC3F_Pos)                       /*!< 0x00000020 */
#define TIM_CCMR2_IC3F_2                          (0x4UL<<TIM_CCMR2_IC3F_Pos)                       /*!< 0x00000040 */
#define TIM_CCMR2_IC3F_3                          (0x8UL<<TIM_CCMR2_IC3F_Pos)                       /*!< 0x00000080 */
              
#define TIM_CCMR2_IC4PSC_Pos                     (10U)
#define TIM_CCMR2_IC4PSC_Msk                      (0x3UL<<TIM_CCMR2_IC4PSC_Pos)                     /*!< 0x00000C00 */
#define TIM_CCMR2_IC4PSC                          TIM_CCMR2_IC4PSC_Msk
#define TIM_CCMR2_IC4PSC_0                        (0x1UL<<TIM_CCMR2_IC4PSC_Pos)                     /*!< 0x00000400 */
#define TIM_CCMR2_IC4PSC_1                        (0x2UL<<TIM_CCMR2_IC4PSC_Pos)                     /*!< 0x00000800 */
#define TIM_CCMR2_IC4F_Pos                        (12U)
#define TIM_CCMR2_IC4F_Msk                        (0xFUL<<TIM_CCMR2_IC4F_Pos)                       /*!< 0x0000F000 */
#define TIM_CCMR2_IC4F                            TIM_CCMR2_IC4F_Msk
#define TIM_CCMR2_IC4F_0                          (0x1UL<<TIM_CCMR2_IC4F_Pos)                       /*!< 0x00001000 */
#define TIM_CCMR2_IC4F_1                          (0x2UL<<TIM_CCMR2_IC4F_Pos)                       /*!< 0x00002000 */
#define TIM_CCMR2_IC4F_2                          (0x4UL<<TIM_CCMR2_IC4F_Pos)                       /*!< 0x00004000 */
#define TIM_CCMR2_IC4F_3                          (0x8UL<<TIM_CCMR2_IC4F_Pos)                       /*!< 0x00008000 */

/********************************* Bit definition for TIM_CCER register *********************************************/
#define TIM_CCER_CC1E_Pos                         (0U)
#define TIM_CCER_CC1E_Msk                         (0x1UL<<TIM_CCER_CC1E_Pos)                        /*!< 0x00000001 */
#define TIM_CCER_CC1E                             TIM_CCER_CC1E_Msk                                 
#define TIM_CCER_CC1P_Pos                         (1U)
#define TIM_CCER_CC1P_Msk                         (0x1UL<<TIM_CCER_CC1P_Pos)                        /*!< 0x00000002 */
#define TIM_CCER_CC1P                             TIM_CCER_CC1P_Msk                                 
#define TIM_CCER_CC1NE_Pos                        (2U)
#define TIM_CCER_CC1NE_Msk                        (0x1UL<<TIM_CCER_CC1NE_Pos)                       /*!< 0x00000004 */
#define TIM_CCER_CC1NE                            TIM_CCER_CC1NE_Msk                                
#define TIM_CCER_CC1NP_Pos                        (3U)
#define TIM_CCER_CC1NP_Msk                        (0x1UL<<TIM_CCER_CC1NP_Pos)                       /*!< 0x00000008 */
#define TIM_CCER_CC1NP                            TIM_CCER_CC1NP_Msk                                
#define TIM_CCER_CC2E_Pos                         (4U)
#define TIM_CCER_CC2E_Msk                         (0x1UL<<TIM_CCER_CC2E_Pos)                        /*!< 0x00000010 */
#define TIM_CCER_CC2E                             TIM_CCER_CC2E_Msk                                 
#define TIM_CCER_CC2P_Pos                         (5U)
#define TIM_CCER_CC2P_Msk                         (0x1UL<<TIM_CCER_CC2P_Pos)                        /*!< 0x00000020 */
#define TIM_CCER_CC2P                             TIM_CCER_CC2P_Msk                                 
#define TIM_CCER_CC2NE_Pos                        (6U)
#define TIM_CCER_CC2NE_Msk                        (0x1UL<<TIM_CCER_CC2NE_Pos)                       /*!< 0x00000040 */
#define TIM_CCER_CC2NE                            TIM_CCER_CC2NE_Msk                                
#define TIM_CCER_CC2NP_Pos                        (7U)
#define TIM_CCER_CC2NP_Msk                        (0x1UL<<TIM_CCER_CC2NP_Pos)                       /*!< 0x00000080 */
#define TIM_CCER_CC2NP                            TIM_CCER_CC2NP_Msk                                
#define TIM_CCER_CC3E_Pos                         (8U)
#define TIM_CCER_CC3E_Msk                         (0x1UL<<TIM_CCER_CC3E_Pos)                        /*!< 0x00000100 */
#define TIM_CCER_CC3E                             TIM_CCER_CC3E_Msk                                 
#define TIM_CCER_CC3P_Pos                         (9U)
#define TIM_CCER_CC3P_Msk                         (0x1UL<<TIM_CCER_CC3P_Pos)                        /*!< 0x00000200 */
#define TIM_CCER_CC3P                             TIM_CCER_CC3P_Msk                                 
#define TIM_CCER_CC3NE_Pos                        (10U)
#define TIM_CCER_CC3NE_Msk                        (0x1UL<<TIM_CCER_CC3NE_Pos)                       /*!< 0x00000400 */
#define TIM_CCER_CC3NE                            TIM_CCER_CC3NE_Msk                                
#define TIM_CCER_CC3NP_Pos                        (11U)
#define TIM_CCER_CC3NP_Msk                        (0x1UL<<TIM_CCER_CC3NP_Pos)                       /*!< 0x00000800 */
#define TIM_CCER_CC3NP                            TIM_CCER_CC3NP_Msk                                
#define TIM_CCER_CC4E_Pos                         (12U)
#define TIM_CCER_CC4E_Msk                         (0x1UL<<TIM_CCER_CC4E_Pos)                        /*!< 0x00001000 */
#define TIM_CCER_CC4E                             TIM_CCER_CC4E_Msk                                 
#define TIM_CCER_CC4P_Pos                         (13U)
#define TIM_CCER_CC4P_Msk                         (0x1UL<<TIM_CCER_CC4P_Pos)                        /*!< 0x00002000 */
#define TIM_CCER_CC4P                             TIM_CCER_CC4P_Msk                                 
#define TIM_CCER_CC4NE_Pos                        (14U)
#define TIM_CCER_CC4NE_Msk                        (0x1UL<<TIM_CCER_CC4NE_Pos)                       /*!< 0x00004000 */
#define TIM_CCER_CC4NE                            TIM_CCER_CC4NE_Msk                                
#define TIM_CCER_CC4NP_Pos                        (15U)
#define TIM_CCER_CC4NP_Msk                        (0x1UL<<TIM_CCER_CC4NP_Pos)                       /*!< 0x00008000 */
#define TIM_CCER_CC4NP                            TIM_CCER_CC4NP_Msk                                
#define TIM_CCER_CC5E_Pos                         (16U)
#define TIM_CCER_CC5E_Msk                         (0x1UL<<TIM_CCER_CC5E_Pos)                        /*!< 0x00010000 */
#define TIM_CCER_CC5E                             TIM_CCER_CC5E_Msk                                 
#define TIM_CCER_CC5P_Pos                         (17U)
#define TIM_CCER_CC5P_Msk                         (0x1UL<<TIM_CCER_CC5P_Pos)                        /*!< 0x00020000 */
#define TIM_CCER_CC5P                             TIM_CCER_CC5P_Msk                                 
#define TIM_CCER_CC6E_Pos                         (20U)
#define TIM_CCER_CC6E_Msk                         (0x1UL<<TIM_CCER_CC6E_Pos)                        /*!< 0x00100000 */
#define TIM_CCER_CC6E                             TIM_CCER_CC6E_Msk                                 
#define TIM_CCER_CC6P_Pos                         (21U)
#define TIM_CCER_CC6P_Msk                         (0x1UL<<TIM_CCER_CC6P_Pos)                        /*!< 0x00200000 */
#define TIM_CCER_CC6P                             TIM_CCER_CC6P_Msk                                 

/********************************* Bit definition for TIM_CNT register **********************************************/
#define TIM_CNT_CNT_Pos                           (0U)
#define TIM_CNT_CNT_Msk                           (0xFFFFFFFFUL<<TIM_CNT_CNT_Pos)                   /*!< 0xFFFFFFFF */
#define TIM_CNT_CNT                               TIM_CNT_CNT_Msk

/********************************* Bit definition for TIM_PSC register *********************************************/
#define TIM_PSC_PSC_Pos                           (0U)
#define TIM_PSC_PSC_Msk                           (0xFFFFUL<<TIM_PSC_PSC_Pos)                       /*!< 0x0000FFFF */
#define TIM_PSC_PSC                               TIM_PSC_PSC_Msk

/********************************* Bit definition for TIM_ARR register **********************************************/
#define TIM_ARR_ARR_Pos                           (0U)
#define TIM_ARR_ARR_Msk                           (0xFFFFFFFFUL<<TIM_ARR_ARR_Pos)                   /*!< 0xFFFFFFFF */
#define TIM_ARR_ARR                               TIM_ARR_ARR_Msk

/********************************* Bit definition for TIM_RCR register **********************************************/
#define TIM_RCR_REP_Pos                           (0U)
#define TIM_RCR_REP_Msk                           (0xFFFFUL<<TIM_RCR_REP_Pos)                       /*!< 0x0000FFFF */
#define TIM_RCR_REP                               TIM_RCR_REP_Msk

/********************************* Bit definition for TIM_CCR1 register ********************************************/
#define TIM_CCR1_CCR1_Pos                        (0U)
#define TIM_CCR1_CCR1_Msk                        (0xFFFFUL<<TIM_CCR1_CCR1_Pos)                    /*!< 0x0000FFFF */
#define TIM_CCR1_CCR1                            TIM_CCR1_CCR1_Msk
#define TIM_CCR1_CCR1_H_Pos                      (16U)
#define TIM_CCR1_CCR1_H_Msk                      (0xFFFFUL<<TIM_CCR1_CCR1_H_Pos)                  /*!< 0xFFFF0000 */
#define TIM_CCR1_CCR1_H                          TIM_CCR1_CCR1_H_Msk

/********************************* Bit definition for TIM_CCR2 register ********************************************/
#define TIM_CCR2_CCR2_Pos                        (0U)
#define TIM_CCR2_CCR2_Msk                        (0xFFFFUL<<TIM_CCR2_CCR2_Pos)                    /*!< 0x0000FFFF */
#define TIM_CCR2_CCR2                            TIM_CCR2_CCR2_Msk
#define TIM_CCR2_CCR2_H_Pos                      (16U)
#define TIM_CCR2_CCR2_H_Msk                      (0xFFFFUL<<TIM_CCR2_CCR2_H_Pos)                  /*!< 0xFFFF0000 */
#define TIM_CCR2_CCR2_H                          TIM_CCR2_CCR2_H_Msk

/********************************* Bit definition for TIM_CCR3 register ********************************************/
#define TIM_CCR3_CCR3_Pos                        (0U)
#define TIM_CCR3_CCR3_Msk                        (0xFFFFUL<<TIM_CCR3_CCR3_Pos)                    /*!< 0x0000FFFF */
#define TIM_CCR3_CCR3                            TIM_CCR3_CCR3_Msk
#define TIM_CCR3_CCR3_H_Pos                      (16U)
#define TIM_CCR3_CCR3_H_Msk                      (0xFFFFUL<<TIM_CCR3_CCR3_H_Pos)                  /*!< 0xFFFF0000 */
#define TIM_CCR3_CCR3_H                          TIM_CCR3_CCR3_H_Msk

/********************************* Bit definition for TIM_CCR4 register ********************************************/
#define TIM_CCR4_CCR4_Pos                        (0U)
#define TIM_CCR4_CCR4_Msk                        (0xFFFFUL<<TIM_CCR4_CCR4_Pos)                    /*!< 0x0000FFFF */
#define TIM_CCR4_CCR4                            TIM_CCR4_CCR4_Msk
#define TIM_CCR4_CCR4_H_Pos                      (16U)
#define TIM_CCR4_CCR4_H_Msk                      (0xFFFFUL<<TIM_CCR4_CCR4_H_Pos)                  /*!< 0xFFFF0000 */
#define TIM_CCR4_CCR4_H                          TIM_CCR4_CCR4_H_Msk

/********************************* Bit definition for TIM_BDTR register *********************************************/
#define TIM_BDTR_DTG_Pos                          (0U)
#define TIM_BDTR_DTG_Msk                          (0xFFUL<<TIM_BDTR_DTG_Pos)                        /*!< 0x000000FF */
#define TIM_BDTR_DTG                              TIM_BDTR_DTG_Msk
#define TIM_BDTR_LOCK_Pos                         (8U)
#define TIM_BDTR_LOCK_Msk                         (0x3UL<<TIM_BDTR_LOCK_Pos)                        /*!< 0x00000300 */
#define TIM_BDTR_LOCK                             TIM_BDTR_LOCK_Msk
#define TIM_BDTR_LOCK_0                           (0x1UL<<TIM_BDTR_LOCK_Pos)                        /*!< 0x00000100 */
#define TIM_BDTR_LOCK_1                           (0x2UL<<TIM_BDTR_LOCK_Pos)                        /*!< 0x00000200 */
#define TIM_BDTR_OSSI_Pos                         (10U)
#define TIM_BDTR_OSSI_Msk                         (0x1UL<<TIM_BDTR_OSSI_Pos)                        /*!< 0x00000400 */
#define TIM_BDTR_OSSI                             TIM_BDTR_OSSI_Msk                                 
#define TIM_BDTR_OSSR_Pos                         (11U)
#define TIM_BDTR_OSSR_Msk                         (0x1UL<<TIM_BDTR_OSSR_Pos)                        /*!< 0x00000800 */
#define TIM_BDTR_OSSR                             TIM_BDTR_OSSR_Msk                                 
#define TIM_BDTR_BKE_Pos                          (12U)
#define TIM_BDTR_BKE_Msk                          (0x1UL<<TIM_BDTR_BKE_Pos)                         /*!< 0x00001000 */
#define TIM_BDTR_BKE                              TIM_BDTR_BKE_Msk                                  
#define TIM_BDTR_BKP_Pos                          (13U)
#define TIM_BDTR_BKP_Msk                          (0x1UL<<TIM_BDTR_BKP_Pos)                         /*!< 0x00002000 */
#define TIM_BDTR_BKP                              TIM_BDTR_BKP_Msk                                  
#define TIM_BDTR_AOE_Pos                          (14U)
#define TIM_BDTR_AOE_Msk                          (0x1UL<<TIM_BDTR_AOE_Pos)                         /*!< 0x00004000 */
#define TIM_BDTR_AOE                              TIM_BDTR_AOE_Msk                                  
#define TIM_BDTR_MOE_Pos                          (15U)
#define TIM_BDTR_MOE_Msk                          (0x1UL<<TIM_BDTR_MOE_Pos)                         /*!< 0x00008000 */
#define TIM_BDTR_MOE                              TIM_BDTR_MOE_Msk                                  
#define TIM_BDTR_BKF_Pos                          (16U)
#define TIM_BDTR_BKF_Msk                          (0xFUL<<TIM_BDTR_BKF_Pos)                         /*!< 0x000F0000 */
#define TIM_BDTR_BKF                              TIM_BDTR_BKF_Msk
#define TIM_BDTR_BKF_0                            (0x1UL<<TIM_BDTR_BKF_Pos)                         /*!< 0x00010000 */
#define TIM_BDTR_BKF_1                            (0x2UL<<TIM_BDTR_BKF_Pos)                         /*!< 0x00020000 */
#define TIM_BDTR_BKF_2                            (0x4UL<<TIM_BDTR_BKF_Pos)                         /*!< 0x00040000 */
#define TIM_BDTR_BKF_3                            (0x8UL<<TIM_BDTR_BKF_Pos)                         /*!< 0x00080000 */
#define TIM_BDTR_BK2F_Pos                         (20U)
#define TIM_BDTR_BK2F_Msk                         (0xFUL<<TIM_BDTR_BK2F_Pos)                        /*!< 0x00F00000 */
#define TIM_BDTR_BK2F                             TIM_BDTR_BK2F_Msk
#define TIM_BDTR_BK2F_0                           (0x1UL<<TIM_BDTR_BK2F_Pos)                        /*!< 0x00100000 */
#define TIM_BDTR_BK2F_1                           (0x2UL<<TIM_BDTR_BK2F_Pos)                        /*!< 0x00200000 */
#define TIM_BDTR_BK2F_2                           (0x4UL<<TIM_BDTR_BK2F_Pos)                        /*!< 0x00400000 */
#define TIM_BDTR_BK2F_3                           (0x8UL<<TIM_BDTR_BK2F_Pos)                        /*!< 0x00800000 */
#define TIM_BDTR_BK2E_Pos                         (24U)
#define TIM_BDTR_BK2E_Msk                         (0x1UL<<TIM_BDTR_BK2E_Pos)                        /*!< 0x01000000 */
#define TIM_BDTR_BK2E                             TIM_BDTR_BK2E_Msk                                 
#define TIM_BDTR_BK2P_Pos                         (25U)
#define TIM_BDTR_BK2P_Msk                         (0x1UL<<TIM_BDTR_BK2P_Pos)                        /*!< 0x02000000 */
#define TIM_BDTR_BK2P                             TIM_BDTR_BK2P_Msk                                 
#define TIM_BDTR_BKDSRM_Pos                       (26U)
#define TIM_BDTR_BKDSRM_Msk                       (0x1UL<<TIM_BDTR_BKDSRM_Pos)                      /*!< 0x04000000 */
#define TIM_BDTR_BKDSRM                           TIM_BDTR_BKDSRM_Msk                               
#define TIM_BDTR_BK2DSRM_Pos                      (27U)
#define TIM_BDTR_BK2DSRM_Msk                      (0x1UL<<TIM_BDTR_BK2DSRM_Pos)                     /*!< 0x08000000 */
#define TIM_BDTR_BK2DSRM                          TIM_BDTR_BK2DSRM_Msk                              
#define TIM_BDTR_BKBID_Pos                        (28U)
#define TIM_BDTR_BKBID_Msk                        (0x1UL<<TIM_BDTR_BKBID_Pos)                       /*!< 0x10000000 */
#define TIM_BDTR_BKBID                            TIM_BDTR_BKBID_Msk                                
#define TIM_BDTR_BK2BID_Pos                       (29U)
#define TIM_BDTR_BK2BID_Msk                       (0x1UL<<TIM_BDTR_BK2BID_Pos)                      /*!< 0x20000000 */
#define TIM_BDTR_BK2BID                           TIM_BDTR_BK2BID_Msk                               

/********************************* Bit definition for TIM_CCR5 register ********************************************/
#define TIM_CCR5_CCR5_Pos                        (0U)
#define TIM_CCR5_CCR5_Msk                        (0xFFFFUL<<TIM_CCR5_CCR5_Pos)                    /*!< 0x0000FFFF */
#define TIM_CCR5_CCR5                            TIM_CCR5_CCR5_Msk

/********************************* Bit definition for TIM_CCR6 register ********************************************/
#define TIM_CCR6_CCR6_Pos                        (0U)
#define TIM_CCR6_CCR6_Msk                        (0xFFFFUL<<TIM_CCR6_CCR6_Pos)                    /*!< 0x0000FFFF */
#define TIM_CCR6_CCR6                            TIM_CCR6_CCR6_Msk

/********************************* Bit definition for TIM_CCMR3 register ********************************************/
#define TIM_CCMR3_OC5FE_Pos                      (2U)
#define TIM_CCMR3_OC5FE_Msk                      (0x1UL<<TIM_CCMR3_OC5FE_Pos)                   /*!< 0x00010070 */
#define TIM_CCMR3_OC5FE                           TIM_CCMR3_OC5FE_Msk
#define TIM_CCMR3_OC5PE_Pos                      (3U)
#define TIM_CCMR3_OC5PE_Msk                      (0x1UL<<TIM_CCMR3_OC5PE_Pos)                   /*!< 0x00010070 */
#define TIM_CCMR3_OC5PE                           TIM_CCMR3_OC5PE_Msk
#define TIM_CCMR3_OC5M_Pos                       (4U)
#define TIM_CCMR3_OC5M_Msk                       (0x1007UL<<TIM_CCMR3_OC5M_Pos)                   /*!< 0x00010070 */
#define TIM_CCMR3_OC5M                           TIM_CCMR3_OC5M_Msk
#define TIM_CCMR3_OC5M_0                         (0x1UL<<TIM_CCMR3_OC5M_Pos)                      /*!< 0x00000010 */
#define TIM_CCMR3_OC5M_1                         (0x2UL<<TIM_CCMR3_OC5M_Pos)                      /*!< 0x00000020 */
#define TIM_CCMR3_OC5M_2                         (0x4UL<<TIM_CCMR3_OC5M_Pos)                      /*!< 0x00000040 */
#define TIM_CCMR3_OC5M_3                         (0x1000UL<<TIM_CCMR3_OC5M_Pos)                   /*!< 0x00010000 */
#define TIM_CCMR3_OC5CE_Pos                      (7U)
#define TIM_CCMR3_OC5CE_Msk                      (0x1UL<<TIM_CCMR3_OC5CE_Pos)                   /*!< 0x00010070 */
#define TIM_CCMR3_OC5CE                           TIM_CCMR3_OC5CE_Msk

#define TIM_CCMR3_OC6FE_Pos                      (10U)
#define TIM_CCMR3_OC6FE_Msk                      (0x1UL<<TIM_CCMR3_OC6FE_Pos)                   /*!< 0x00010070 */
#define TIM_CCMR3_OC6FE                           TIM_CCMR3_OC6FE_Msk
#define TIM_CCMR3_OC6PE_Pos                      (11U)
#define TIM_CCMR3_OC6PE_Msk                      (0x1UL<<TIM_CCMR3_OC6PE_Pos)                   /*!< 0x00010070 */
#define TIM_CCMR3_OC6PE                           TIM_CCMR3_OC6PE_Msk
#define TIM_CCMR3_OC6M_Pos                       (12U)
#define TIM_CCMR3_OC6M_Msk                       (0x1007UL<<TIM_CCMR3_OC6M_Pos)                   /*!< 0x01007000 */
#define TIM_CCMR3_OC6M                           TIM_CCMR3_OC6M_Msk
#define TIM_CCMR3_OC6M_0                         (0x1UL<<TIM_CCMR3_OC6M_Pos)                      /*!< 0x00001000 */
#define TIM_CCMR3_OC6M_1                         (0x2UL<<TIM_CCMR3_OC6M_Pos)                      /*!< 0x00002000 */
#define TIM_CCMR3_OC6M_2                         (0x4UL<<TIM_CCMR3_OC6M_Pos)                      /*!< 0x00004000 */
#define TIM_CCMR3_OC6M_3                         (0x1000UL<<TIM_CCMR3_OC6M_Pos)                   /*!< 0x01000000 */
#define TIM_CCMR3_OC6CE_Pos                      (15U)
#define TIM_CCMR3_OC6CE_Msk                      (0x1UL<<TIM_CCMR3_OC6CE_Pos)                   /*!< 0x00010070 */
#define TIM_CCMR3_OC6CE                           TIM_CCMR3_OC6CE_Msk

/********************************* Bit definition for TIM_DTR2 register *********************************************/
#define TIM_DTR2_DTGF_Pos                         (0U)
#define TIM_DTR2_DTGF_Msk                         (0xFFUL<<TIM_DTR2_DTGF_Pos)                       /*!< 0x000000FF */
#define TIM_DTR2_DTGF                             TIM_DTR2_DTGF_Msk
#define TIM_DTR2_DTAE_Pos                         (16U)
#define TIM_DTR2_DTAE_Msk                         (0x1UL<<TIM_DTR2_DTAE_Pos)                        /*!< 0x00010000 */
#define TIM_DTR2_DTAE                             TIM_DTR2_DTAE_Msk                                 
#define TIM_DTR2_DTPE_Pos                         (17U)
#define TIM_DTR2_DTPE_Msk                         (0x1UL<<TIM_DTR2_DTPE_Pos)                        /*!< 0x00020000 */
#define TIM_DTR2_DTPE                             TIM_DTR2_DTPE_Msk                                 

/********************************* Bit definition for TIM_ECR register **********************************************/
#define TIM_ECR_IE_Pos                            (0U)
#define TIM_ECR_IE_Msk                            (0x1UL<<TIM_ECR_IE_Pos)                           /*!< 0x00000001 */
#define TIM_ECR_IE                                TIM_ECR_IE_Msk                                    
#define TIM_ECR_IDIR_Pos                          (1U)
#define TIM_ECR_IDIR_Msk                          (0x3UL<<TIM_ECR_IDIR_Pos)                         /*!< 0x00000006 */
#define TIM_ECR_IDIR                              TIM_ECR_IDIR_Msk
#define TIM_ECR_IDIR_0                            (0x1UL<<TIM_ECR_IDIR_Pos)                         /*!< 0x00000002 */
#define TIM_ECR_IDIR_1                            (0x2UL<<TIM_ECR_IDIR_Pos)                         /*!< 0x00000004 */
#define TIM_ECR_FIDX_Pos                          (5U)
#define TIM_ECR_FIDX_Msk                          (0x1UL<<TIM_ECR_FIDX_Pos)                         /*!< 0x00000020 */
#define TIM_ECR_FIDX                              TIM_ECR_FIDX_Msk                                  
#define TIM_ECR_IPOS_Pos                          (6U)
#define TIM_ECR_IPOS_Msk                          (0x3UL<<TIM_ECR_IPOS_Pos)                         /*!< 0x000000C0 */
#define TIM_ECR_IPOS                              TIM_ECR_IPOS_Msk
#define TIM_ECR_IPOS_0                            (0x1UL<<TIM_ECR_IPOS_Pos)                         /*!< 0x00000040 */
#define TIM_ECR_IPOS_1                            (0x2UL<<TIM_ECR_IPOS_Pos)                         /*!< 0x00000080 */
#define TIM_ECR_PW_Pos                            (16U)
#define TIM_ECR_PW_Msk                            (0xFFUL<<TIM_ECR_PW_Pos)                          /*!< 0x00FF0000 */
#define TIM_ECR_PW                                TIM_ECR_PW_Msk
#define TIM_ECR_PWPRSC_Pos                        (24U)
#define TIM_ECR_PWPRSC_Msk                        (0x7UL<<TIM_ECR_PWPRSC_Pos)                       /*!< 0x07000000 */
#define TIM_ECR_PWPRSC                            TIM_ECR_PWPRSC_Msk
#define TIM_ECR_PWPRSC_0                          (0x1UL<<TIM_ECR_PWPRSC_Pos)                       /*!< 0x01000000 */
#define TIM_ECR_PWPRSC_1                          (0x2UL<<TIM_ECR_PWPRSC_Pos)                       /*!< 0x02000000 */
#define TIM_ECR_PWPRSC_2                          (0x4UL<<TIM_ECR_PWPRSC_Pos)                       /*!< 0x04000000 */

/********************************* Bit definition for TIM_TISEL register ********************************************/
#define TIM_TISEL_TI1SEL_Pos                      (0U)
#define TIM_TISEL_TI1SEL_Msk                      (0xFUL<<TIM_TISEL_TI1SEL_Pos)                     /*!< 0x0000000F */
#define TIM_TISEL_TI1SEL                          TIM_TISEL_TI1SEL_Msk
#define TIM_TISEL_TI1SEL_0                        (0x1UL<<TIM_TISEL_TI1SEL_Pos)                     /*!< 0x00000001 */
#define TIM_TISEL_TI1SEL_1                        (0x2UL<<TIM_TISEL_TI1SEL_Pos)                     /*!< 0x00000002 */
#define TIM_TISEL_TI1SEL_2                        (0x4UL<<TIM_TISEL_TI1SEL_Pos)                     /*!< 0x00000004 */
#define TIM_TISEL_TI1SEL_3                        (0x8UL<<TIM_TISEL_TI1SEL_Pos)                     /*!< 0x00000008 */
#define TIM_TISEL_TI2SEL_Pos                      (8U)
#define TIM_TISEL_TI2SEL_Msk                      (0xFUL<<TIM_TISEL_TI2SEL_Pos)                     /*!< 0x00000F00 */
#define TIM_TISEL_TI2SEL                          TIM_TISEL_TI2SEL_Msk
#define TIM_TISEL_TI2SEL_0                        (0x1UL<<TIM_TISEL_TI2SEL_Pos)                     /*!< 0x00000100 */
#define TIM_TISEL_TI2SEL_1                        (0x2UL<<TIM_TISEL_TI2SEL_Pos)                     /*!< 0x00000200 */
#define TIM_TISEL_TI2SEL_2                        (0x4UL<<TIM_TISEL_TI2SEL_Pos)                     /*!< 0x00000400 */
#define TIM_TISEL_TI2SEL_3                        (0x8UL<<TIM_TISEL_TI2SEL_Pos)                     /*!< 0x00000800 */
#define TIM_TISEL_TI3SEL_Pos                      (16U)
#define TIM_TISEL_TI3SEL_Msk                      (0xFUL<<TIM_TISEL_TI3SEL_Pos)                     /*!< 0x000F0000 */
#define TIM_TISEL_TI3SEL                          TIM_TISEL_TI3SEL_Msk
#define TIM_TISEL_TI3SEL_0                        (0x1UL<<TIM_TISEL_TI3SEL_Pos)                     /*!< 0x00010000 */
#define TIM_TISEL_TI3SEL_1                        (0x2UL<<TIM_TISEL_TI3SEL_Pos)                     /*!< 0x00020000 */
#define TIM_TISEL_TI3SEL_2                        (0x4UL<<TIM_TISEL_TI3SEL_Pos)                     /*!< 0x00040000 */
#define TIM_TISEL_TI3SEL_3                        (0x8UL<<TIM_TISEL_TI3SEL_Pos)                     /*!< 0x00080000 */
#define TIM_TISEL_TI4SEL_Pos                      (24U)
#define TIM_TISEL_TI4SEL_Msk                      (0xFUL<<TIM_TISEL_TI4SEL_Pos)                     /*!< 0x0F000000 */
#define TIM_TISEL_TI4SEL                          TIM_TISEL_TI4SEL_Msk
#define TIM_TISEL_TI4SEL_0                        (0x1UL<<TIM_TISEL_TI4SEL_Pos)                     /*!< 0x01000000 */
#define TIM_TISEL_TI4SEL_1                        (0x2UL<<TIM_TISEL_TI4SEL_Pos)                     /*!< 0x02000000 */
#define TIM_TISEL_TI4SEL_2                        (0x4UL<<TIM_TISEL_TI4SEL_Pos)                     /*!< 0x04000000 */
#define TIM_TISEL_TI4SEL_3                        (0x8UL<<TIM_TISEL_TI4SEL_Pos)                     /*!< 0x08000000 */

/********************************* Bit definition for TIM_AF1 register **********************************************/
#define TIM_AF1_BKINE_Pos                         (0U)
#define TIM_AF1_BKINE_Msk                         (0x1UL<<TIM_AF1_BKINE_Pos)                        /*!< 0x00000001 */
#define TIM_AF1_BKINE                             TIM_AF1_BKINE_Msk                                 
#define TIM_AF1_BKCMP1E_Pos                       (1U)
#define TIM_AF1_BKCMP1E_Msk                       (0x1UL<<TIM_AF1_BKCMP1E_Pos)                      /*!< 0x00000002 */
#define TIM_AF1_BKCMP1E                           TIM_AF1_BKCMP1E_Msk                               
#define TIM_AF1_BKCMP2E_Pos                       (2U)
#define TIM_AF1_BKCMP2E_Msk                       (0x1UL<<TIM_AF1_BKCMP2E_Pos)                      /*!< 0x00000004 */
#define TIM_AF1_BKCMP2E                           TIM_AF1_BKCMP2E_Msk                               
#define TIM_AF1_BKCMP3E_Pos                       (3U)
#define TIM_AF1_BKCMP3E_Msk                       (0x1UL<<TIM_AF1_BKCMP3E_Pos)                      /*!< 0x00000008 */
#define TIM_AF1_BKCMP3E                           TIM_AF1_BKCMP3E_Msk                               
#define TIM_AF1_BKCMP4E_Pos                       (4U)
#define TIM_AF1_BKCMP4E_Msk                       (0x1UL<<TIM_AF1_BKCMP4E_Pos)                      /*!< 0x00000010 */
#define TIM_AF1_BKCMP4E                           TIM_AF1_BKCMP4E_Msk                               
#define TIM_AF1_BKINP_Pos                         (9U)
#define TIM_AF1_BKINP_Msk                         (0x1UL<<TIM_AF1_BKINP_Pos)                        /*!< 0x00000200 */
#define TIM_AF1_BKINP                             TIM_AF1_BKINP_Msk                                 
#define TIM_AF1_BKCMP1P_Pos                       (10U)
#define TIM_AF1_BKCMP1P_Msk                       (0x1UL<<TIM_AF1_BKCMP1P_Pos)                      /*!< 0x00000400 */
#define TIM_AF1_BKCMP1P                           TIM_AF1_BKCMP1P_Msk                               
#define TIM_AF1_BKCMP2P_Pos                       (11U)
#define TIM_AF1_BKCMP2P_Msk                       (0x1UL<<TIM_AF1_BKCMP2P_Pos)                      /*!< 0x00000800 */
#define TIM_AF1_BKCMP2P                           TIM_AF1_BKCMP2P_Msk                               
#define TIM_AF1_BKCMP3P_Pos                       (12U)
#define TIM_AF1_BKCMP3P_Msk                       (0x1UL<<TIM_AF1_BKCMP3P_Pos)                      /*!< 0x00001000 */
#define TIM_AF1_BKCMP3P                           TIM_AF1_BKCMP3P_Msk                               
#define TIM_AF1_BKCMP4P_Pos                       (13U)
#define TIM_AF1_BKCMP4P_Msk                       (0x1UL<<TIM_AF1_BKCMP4P_Pos)                      /*!< 0x00002000 */
#define TIM_AF1_BKCMP4P                           TIM_AF1_BKCMP4P_Msk                               
#define TIM_AF1_ETRSEL_Pos                        (14U)
#define TIM_AF1_ETRSEL_Msk                        (0xFUL<<TIM_AF1_ETRSEL_Pos)                       /*!< 0x0003C000 */
#define TIM_AF1_ETRSEL                            TIM_AF1_ETRSEL_Msk
#define TIM_AF1_ETRSEL_0                          (0x1UL<<TIM_AF1_ETRSEL_Pos)                       /*!< 0x00004000 */
#define TIM_AF1_ETRSEL_1                          (0x2UL<<TIM_AF1_ETRSEL_Pos)                       /*!< 0x00008000 */
#define TIM_AF1_ETRSEL_2                          (0x4UL<<TIM_AF1_ETRSEL_Pos)                       /*!< 0x00010000 */
#define TIM_AF1_ETRSEL_3                          (0x8UL<<TIM_AF1_ETRSEL_Pos)                       /*!< 0x00020000 */
#define TIM_AF1_INTR_SEL_Pos                      (18U)
#define TIM_AF1_INTR_SEL_Msk                      (0x3UL<<TIM_AF1_INTR_SEL_Pos)                     /*!< 0x000C0000 */
#define TIM_AF1_INTR_SEL                          TIM_AF1_INTR_SEL_Msk
#define TIM_AF1_INTR_SEL_0                        (0x1UL<<TIM_AF1_INTR_SEL_Pos)                     /*!< 0x00040000 */
#define TIM_AF1_INTR_SEL_1                        (0x2UL<<TIM_AF1_INTR_SEL_Pos)                     /*!< 0x00080000 */
#define TIM_AF1_PWM_PHS_EN_Pos                    (20U)
#define TIM_AF1_PWM_PHS_EN_Msk                    (0x1UL<<TIM_AF1_PWM_PHS_EN_Pos)                   /*!< 0x00100000 */
#define TIM_AF1_PWM_PHS_EN                        TIM_AF1_PWM_PHS_EN_Msk                            

/********************************* Bit definition for TIM_AF2 register **********************************************/
#define TIM_AF2_BK2INE_Pos                        (0U)
#define TIM_AF2_BK2INE_Msk                        (0x1UL<<TIM_AF2_BK2INE_Pos)                       /*!< 0x00000001 */
#define TIM_AF2_BK2INE                            TIM_AF2_BK2INE_Msk                                
#define TIM_AF2_BK2CMP1E_Pos                      (1U)
#define TIM_AF2_BK2CMP1E_Msk                      (0x1UL<<TIM_AF2_BK2CMP1E_Pos)                     /*!< 0x00000002 */
#define TIM_AF2_BK2CMP1E                          TIM_AF2_BK2CMP1E_Msk                              
#define TIM_AF2_BK2CMP2E_Pos                      (2U)
#define TIM_AF2_BK2CMP2E_Msk                      (0x1UL<<TIM_AF2_BK2CMP2E_Pos)                     /*!< 0x00000004 */
#define TIM_AF2_BK2CMP2E                          TIM_AF2_BK2CMP2E_Msk                              
#define TIM_AF2_BK2CMP3E_Pos                      (3U)
#define TIM_AF2_BK2CMP3E_Msk                      (0x1UL<<TIM_AF2_BK2CMP3E_Pos)                     /*!< 0x00000008 */
#define TIM_AF2_BK2CMP3E                          TIM_AF2_BK2CMP3E_Msk                              
#define TIM_AF2_BK2CMP4E_Pos                      (4U)
#define TIM_AF2_BK2CMP4E_Msk                      (0x1UL<<TIM_AF2_BK2CMP4E_Pos)                     /*!< 0x00000010 */
#define TIM_AF2_BK2CMP4E                          TIM_AF2_BK2CMP4E_Msk                              
#define TIM_AF2_BK2INP_Pos                        (9U)
#define TIM_AF2_BK2INP_Msk                        (0x1UL<<TIM_AF2_BK2INP_Pos)                       /*!< 0x00000200 */
#define TIM_AF2_BK2INP                            TIM_AF2_BK2INP_Msk                                
#define TIM_AF2_BK2CMP1P_Pos                      (10U)
#define TIM_AF2_BK2CMP1P_Msk                      (0x1UL<<TIM_AF2_BK2CMP1P_Pos)                     /*!< 0x00000400 */
#define TIM_AF2_BK2CMP1P                          TIM_AF2_BK2CMP1P_Msk                              
#define TIM_AF2_BK2CMP2P_Pos                      (11U)
#define TIM_AF2_BK2CMP2P_Msk                      (0x1UL<<TIM_AF2_BK2CMP2P_Pos)                     /*!< 0x00000800 */
#define TIM_AF2_BK2CMP2P                          TIM_AF2_BK2CMP2P_Msk                              
#define TIM_AF2_BK2CMP3P_Pos                      (12U)
#define TIM_AF2_BK2CMP3P_Msk                      (0x1UL<<TIM_AF2_BK2CMP3P_Pos)                     /*!< 0x00001000 */
#define TIM_AF2_BK2CMP3P                          TIM_AF2_BK2CMP3P_Msk                              
#define TIM_AF2_BK2CMP4P_Pos                      (13U)
#define TIM_AF2_BK2CMP4P_Msk                      (0x1UL<<TIM_AF2_BK2CMP4P_Pos)                     /*!< 0x00002000 */
#define TIM_AF2_BK2CMP4P                          TIM_AF2_BK2CMP4P_Msk                              
#define TIM_AF2_OCRSEL_Pos                        (16U)
#define TIM_AF2_OCRSEL_Msk                        (0x7UL<<TIM_AF2_OCRSEL_Pos)                       /*!< 0x00070000 */
#define TIM_AF2_OCRSEL                            TIM_AF2_OCRSEL_Msk
#define TIM_AF2_OCRSEL_0                          (0x1UL<<TIM_AF2_OCRSEL_Pos)                       /*!< 0x00010000 */
#define TIM_AF2_OCRSEL_1                          (0x2UL<<TIM_AF2_OCRSEL_Pos)                       /*!< 0x00020000 */
#define TIM_AF2_OCRSEL_2                          (0x4UL<<TIM_AF2_OCRSEL_Pos)                       /*!< 0x00040000 */

/********************************* Bit definition for TIM_MTADCCR register ******************************************/
#define TIM_MTADCCR_MTZEROE_Pos                   (0U)
#define TIM_MTADCCR_MTZEROE_Msk                   (0x1UL<<TIM_MTADCCR_MTZEROE_Pos)                  /*!< 0x00000001 */
#define TIM_MTADCCR_MTZEROE                       TIM_MTADCCR_MTZEROE_Msk                           
#define TIM_MTADCCR_MTARRE_Pos                    (1U)
#define TIM_MTADCCR_MTARRE_Msk                    (0x1UL<<TIM_MTADCCR_MTARRE_Pos)                   /*!< 0x00000002 */
#define TIM_MTADCCR_MTARRE                        TIM_MTADCCR_MTARRE_Msk                            
#define TIM_MTADCCR_UMTCCR1E_Pos                  (2U)
#define TIM_MTADCCR_UMTCCR1E_Msk                  (0x1UL<<TIM_MTADCCR_UMTCCR1E_Pos)                 /*!< 0x00000004 */
#define TIM_MTADCCR_UMTCCR1E                      TIM_MTADCCR_UMTCCR1E_Msk                          
#define TIM_MTADCCR_UMTCCR1HE_Pos                 (3U)
#define TIM_MTADCCR_UMTCCR1HE_Msk                 (0x1UL<<TIM_MTADCCR_UMTCCR1HE_Pos)                /*!< 0x00000008 */
#define TIM_MTADCCR_UMTCCR1HE                     TIM_MTADCCR_UMTCCR1HE_Msk                         
#define TIM_MTADCCR_UMTCCR2E_Pos                  (4U)
#define TIM_MTADCCR_UMTCCR2E_Msk                  (0x1UL<<TIM_MTADCCR_UMTCCR2E_Pos)                 /*!< 0x00000010 */
#define TIM_MTADCCR_UMTCCR2E                      TIM_MTADCCR_UMTCCR2E_Msk                          
#define TIM_MTADCCR_UMTCCR2HE_Pos                 (5U)
#define TIM_MTADCCR_UMTCCR2HE_Msk                 (0x1UL<<TIM_MTADCCR_UMTCCR2HE_Pos)                /*!< 0x00000020 */
#define TIM_MTADCCR_UMTCCR2HE                     TIM_MTADCCR_UMTCCR2HE_Msk                         
#define TIM_MTADCCR_UMTCCR3E_Pos                  (6U)
#define TIM_MTADCCR_UMTCCR3E_Msk                  (0x1UL<<TIM_MTADCCR_UMTCCR3E_Pos)                 /*!< 0x00000040 */
#define TIM_MTADCCR_UMTCCR3E                      TIM_MTADCCR_UMTCCR3E_Msk                          
#define TIM_MTADCCR_UMTCCR3HE_Pos                 (7U)
#define TIM_MTADCCR_UMTCCR3HE_Msk                 (0x1UL<<TIM_MTADCCR_UMTCCR3HE_Pos)                /*!< 0x00000080 */
#define TIM_MTADCCR_UMTCCR3HE                     TIM_MTADCCR_UMTCCR3HE_Msk                         
#define TIM_MTADCCR_UMTCCR4E_Pos                  (8U)
#define TIM_MTADCCR_UMTCCR4E_Msk                  (0x1UL<<TIM_MTADCCR_UMTCCR4E_Pos)                 /*!< 0x00000100 */
#define TIM_MTADCCR_UMTCCR4E                      TIM_MTADCCR_UMTCCR4E_Msk                          
#define TIM_MTADCCR_UMTCCR4HE_Pos                 (9U)
#define TIM_MTADCCR_UMTCCR4HE_Msk                 (0x1UL<<TIM_MTADCCR_UMTCCR4HE_Pos)                /*!< 0x00000200 */
#define TIM_MTADCCR_UMTCCR4HE                     TIM_MTADCCR_UMTCCR4HE_Msk                         
#define TIM_MTADCCR_DMTCCR1E_Pos                  (10U)
#define TIM_MTADCCR_DMTCCR1E_Msk                  (0x1UL<<TIM_MTADCCR_DMTCCR1E_Pos)                 /*!< 0x00000400 */
#define TIM_MTADCCR_DMTCCR1E                      TIM_MTADCCR_DMTCCR1E_Msk                          
#define TIM_MTADCCR_DMTCCR1HE_Pos                 (11U)
#define TIM_MTADCCR_DMTCCR1HE_Msk                 (0x1UL<<TIM_MTADCCR_DMTCCR1HE_Pos)                /*!< 0x00000800 */
#define TIM_MTADCCR_DMTCCR1HE                     TIM_MTADCCR_DMTCCR1HE_Msk                         
#define TIM_MTADCCR_DMTCCR2E_Pos                  (12U)
#define TIM_MTADCCR_DMTCCR2E_Msk                  (0x1UL<<TIM_MTADCCR_DMTCCR2E_Pos)                 /*!< 0x00001000 */
#define TIM_MTADCCR_DMTCCR2E                      TIM_MTADCCR_DMTCCR2E_Msk                          
#define TIM_MTADCCR_DMTCCR2HE_Pos                 (13U)
#define TIM_MTADCCR_DMTCCR2HE_Msk                 (0x1UL<<TIM_MTADCCR_DMTCCR2HE_Pos)                /*!< 0x00002000 */
#define TIM_MTADCCR_DMTCCR2HE                     TIM_MTADCCR_DMTCCR2HE_Msk                         
#define TIM_MTADCCR_DMTCCR3E_Pos                  (14U)
#define TIM_MTADCCR_DMTCCR3E_Msk                  (0x1UL<<TIM_MTADCCR_DMTCCR3E_Pos)                 /*!< 0x00004000 */
#define TIM_MTADCCR_DMTCCR3E                      TIM_MTADCCR_DMTCCR3E_Msk                          
#define TIM_MTADCCR_DMTCCR3HE_Pos                 (15U)
#define TIM_MTADCCR_DMTCCR3HE_Msk                 (0x1UL<<TIM_MTADCCR_DMTCCR3HE_Pos)                /*!< 0x00008000 */
#define TIM_MTADCCR_DMTCCR3HE                     TIM_MTADCCR_DMTCCR3HE_Msk                         
#define TIM_MTADCCR_DMTCCR4E_Pos                  (16U)
#define TIM_MTADCCR_DMTCCR4E_Msk                  (0x1UL<<TIM_MTADCCR_DMTCCR4E_Pos)                 /*!< 0x00010000 */
#define TIM_MTADCCR_DMTCCR4E                      TIM_MTADCCR_DMTCCR4E_Msk                          
#define TIM_MTADCCR_DMTCCR4HE_Pos                 (17U)
#define TIM_MTADCCR_DMTCCR4HE_Msk                 (0x1UL<<TIM_MTADCCR_DMTCCR4HE_Pos)                /*!< 0x00020000 */
#define TIM_MTADCCR_DMTCCR4HE                     TIM_MTADCCR_DMTCCR4HE_Msk                         
#define TIM_MTADCCR_MTADCE_Pos                    (18U)
#define TIM_MTADCCR_MTADCE_Msk                    (0x1UL<<TIM_MTADCCR_MTADCE_Pos)                   /*!< 0x00040000 */
#define TIM_MTADCCR_MTADCE                        TIM_MTADCCR_MTADCE_Msk                            

/********************************* Bit definition for TIM_DCR register **********************************************/
#define TIM_DCR_DBA_Pos                           (0U)
#define TIM_DCR_DBA_Msk                           (0x1FUL<<TIM_DCR_DBA_Pos)                         /*!< 0x0000001F */
#define TIM_DCR_DBA                               TIM_DCR_DBA_Msk
#define TIM_DCR_DBA_0                             (0x1UL<<TIM_DCR_DBA_Pos)                          /*!< 0x00000001 */
#define TIM_DCR_DBA_1                             (0x2UL<<TIM_DCR_DBA_Pos)                          /*!< 0x00000002 */
#define TIM_DCR_DBA_2                             (0x4UL<<TIM_DCR_DBA_Pos)                          /*!< 0x00000004 */
#define TIM_DCR_DBA_3                             (0x8UL<<TIM_DCR_DBA_Pos)                          /*!< 0x00000008 */
#define TIM_DCR_DBA_4                             (0x10UL<<TIM_DCR_DBA_Pos)                         /*!< 0x00000010 */
#define TIM_DCR_DBL_Pos                           (8U)
#define TIM_DCR_DBL_Msk                           (0x1FUL<<TIM_DCR_DBL_Pos)                         /*!< 0x00001F00 */
#define TIM_DCR_DBL                               TIM_DCR_DBL_Msk
#define TIM_DCR_DBL_0                             (0x1UL<<TIM_DCR_DBL_Pos)                          /*!< 0x00000100 */
#define TIM_DCR_DBL_1                             (0x2UL<<TIM_DCR_DBL_Pos)                          /*!< 0x00000200 */
#define TIM_DCR_DBL_2                             (0x4UL<<TIM_DCR_DBL_Pos)                          /*!< 0x00000400 */
#define TIM_DCR_DBL_3                             (0x8UL<<TIM_DCR_DBL_Pos)                          /*!< 0x00000800 */
#define TIM_DCR_DBL_4                             (0x10UL<<TIM_DCR_DBL_Pos)                         /*!< 0x00001000 */

/********************************* Bit definition for TIM_DMAR register *********************************************/
#define TIM_DMAR_DMAB_Pos                         (0U)
#define TIM_DMAR_DMAB_Msk                         (0xFFFFFFFFUL<<TIM_DMAR_DMAB_Pos)                 /*!< 0xFFFFFFFF */
#define TIM_DMAR_DMAB                             TIM_DMAR_DMAB_Msk

/********************************************************************************************************************/
/********************************* EPWM ****************************************************************************/
/********************************************************************************************************************/
#define EPWM_HR_SUPPORT       /*!< EPWM HighResolution support */

/********************************* Bit definition for EPWM_IXBSEL1_2 register **************************************/
#define EPWM_IXBSEL1_2_INPUTSEL1_Pos             (0U)
#define EPWM_IXBSEL1_2_INPUTSEL1_Msk             (0x3FUL<<EPWM_IXBSEL1_2_INPUTSEL1_Pos)           /*!< 0x0000003F */
#define EPWM_IXBSEL1_2_INPUTSEL1                 EPWM_IXBSEL1_2_INPUTSEL1_Msk                     /*!< eallow, INPUTLOCKx */
#define EPWM_IXBSEL1_2_INPUTSEL1_0               (0x1UL<<EPWM_IXBSEL1_2_INPUTSEL1_Pos)            /*!< 0x00000001 */
#define EPWM_IXBSEL1_2_INPUTSEL1_1               (0x2UL<<EPWM_IXBSEL1_2_INPUTSEL1_Pos)            /*!< 0x00000002 */
#define EPWM_IXBSEL1_2_INPUTSEL1_2               (0x4UL<<EPWM_IXBSEL1_2_INPUTSEL1_Pos)            /*!< 0x00000004 */
#define EPWM_IXBSEL1_2_INPUTSEL1_3               (0x8UL<<EPWM_IXBSEL1_2_INPUTSEL1_Pos)            /*!< 0x00000008 */
#define EPWM_IXBSEL1_2_INPUTSEL1_4               (0x10UL<<EPWM_IXBSEL1_2_INPUTSEL1_Pos)           /*!< 0x00000010 */
#define EPWM_IXBSEL1_2_INPUTSEL1_5               (0x20UL<<EPWM_IXBSEL1_2_INPUTSEL1_Pos)           /*!< 0x00000020 */
#define EPWM_IXBSEL1_2_INPUTSEL2_Pos             (16U)
#define EPWM_IXBSEL1_2_INPUTSEL2_Msk             (0x3FUL<<EPWM_IXBSEL1_2_INPUTSEL2_Pos)           /*!< 0x003F0000 */
#define EPWM_IXBSEL1_2_INPUTSEL2                 EPWM_IXBSEL1_2_INPUTSEL2_Msk                     /*!< eallow, INPUTLOCKx */
#define EPWM_IXBSEL1_2_INPUTSEL2_0               (0x1UL<<EPWM_IXBSEL1_2_INPUTSEL2_Pos)            /*!< 0x00010000 */
#define EPWM_IXBSEL1_2_INPUTSEL2_1               (0x2UL<<EPWM_IXBSEL1_2_INPUTSEL2_Pos)            /*!< 0x00020000 */
#define EPWM_IXBSEL1_2_INPUTSEL2_2               (0x4UL<<EPWM_IXBSEL1_2_INPUTSEL2_Pos)            /*!< 0x00040000 */
#define EPWM_IXBSEL1_2_INPUTSEL2_3               (0x8UL<<EPWM_IXBSEL1_2_INPUTSEL2_Pos)            /*!< 0x00080000 */
#define EPWM_IXBSEL1_2_INPUTSEL2_4               (0x10UL<<EPWM_IXBSEL1_2_INPUTSEL2_Pos)           /*!< 0x00100000 */
#define EPWM_IXBSEL1_2_INPUTSEL2_5               (0x20UL<<EPWM_IXBSEL1_2_INPUTSEL2_Pos)           /*!< 0x00200000 */

/********************************* Bit definition for EPWM_IXBSEL3_4 register **************************************/
#define EPWM_IXBSEL3_4_INPUTSEL3_Pos             (0U)
#define EPWM_IXBSEL3_4_INPUTSEL3_Msk             (0x3FUL<<EPWM_IXBSEL3_4_INPUTSEL3_Pos)           /*!< 0x0000003F */
#define EPWM_IXBSEL3_4_INPUTSEL3                 EPWM_IXBSEL3_4_INPUTSEL3_Msk                     /*!< eallow, INPUTLOCKx */
#define EPWM_IXBSEL3_4_INPUTSEL3_0               (0x1UL<<EPWM_IXBSEL3_4_INPUTSEL3_Pos)            /*!< 0x00000001 */
#define EPWM_IXBSEL3_4_INPUTSEL3_1               (0x2UL<<EPWM_IXBSEL3_4_INPUTSEL3_Pos)            /*!< 0x00000002 */
#define EPWM_IXBSEL3_4_INPUTSEL3_2               (0x4UL<<EPWM_IXBSEL3_4_INPUTSEL3_Pos)            /*!< 0x00000004 */
#define EPWM_IXBSEL3_4_INPUTSEL3_3               (0x8UL<<EPWM_IXBSEL3_4_INPUTSEL3_Pos)            /*!< 0x00000008 */
#define EPWM_IXBSEL3_4_INPUTSEL3_4               (0x10UL<<EPWM_IXBSEL3_4_INPUTSEL3_Pos)           /*!< 0x00000010 */
#define EPWM_IXBSEL3_4_INPUTSEL3_5               (0x20UL<<EPWM_IXBSEL3_4_INPUTSEL3_Pos)           /*!< 0x00000020 */
#define EPWM_IXBSEL3_4_INPUTSEL4_Pos             (16U)
#define EPWM_IXBSEL3_4_INPUTSEL4_Msk             (0x3FUL<<EPWM_IXBSEL3_4_INPUTSEL4_Pos)           /*!< 0x003F0000 */
#define EPWM_IXBSEL3_4_INPUTSEL4                 EPWM_IXBSEL3_4_INPUTSEL4_Msk                     /*!< eallow, INPUTLOCKx */
#define EPWM_IXBSEL3_4_INPUTSEL4_0               (0x1UL<<EPWM_IXBSEL3_4_INPUTSEL4_Pos)            /*!< 0x00010000 */
#define EPWM_IXBSEL3_4_INPUTSEL4_1               (0x2UL<<EPWM_IXBSEL3_4_INPUTSEL4_Pos)            /*!< 0x00020000 */
#define EPWM_IXBSEL3_4_INPUTSEL4_2               (0x4UL<<EPWM_IXBSEL3_4_INPUTSEL4_Pos)            /*!< 0x00040000 */
#define EPWM_IXBSEL3_4_INPUTSEL4_3               (0x8UL<<EPWM_IXBSEL3_4_INPUTSEL4_Pos)            /*!< 0x00080000 */
#define EPWM_IXBSEL3_4_INPUTSEL4_4               (0x10UL<<EPWM_IXBSEL3_4_INPUTSEL4_Pos)           /*!< 0x00100000 */
#define EPWM_IXBSEL3_4_INPUTSEL4_5               (0x20UL<<EPWM_IXBSEL3_4_INPUTSEL4_Pos)           /*!< 0x00200000 */

/********************************* Bit definition for EPWM_IXBSEL5_6 register **************************************/
#define EPWM_IXBSEL5_6_INPUTSEL5_Pos             (0U)
#define EPWM_IXBSEL5_6_INPUTSEL5_Msk             (0x3FUL<<EPWM_IXBSEL5_6_INPUTSEL5_Pos)           /*!< 0x0000003F */
#define EPWM_IXBSEL5_6_INPUTSEL5                 EPWM_IXBSEL5_6_INPUTSEL5_Msk                     /*!< eallow, INPUTLOCKx */
#define EPWM_IXBSEL5_6_INPUTSEL5_0               (0x1UL<<EPWM_IXBSEL5_6_INPUTSEL5_Pos)            /*!< 0x00000001 */
#define EPWM_IXBSEL5_6_INPUTSEL5_1               (0x2UL<<EPWM_IXBSEL5_6_INPUTSEL5_Pos)            /*!< 0x00000002 */
#define EPWM_IXBSEL5_6_INPUTSEL5_2               (0x4UL<<EPWM_IXBSEL5_6_INPUTSEL5_Pos)            /*!< 0x00000004 */
#define EPWM_IXBSEL5_6_INPUTSEL5_3               (0x8UL<<EPWM_IXBSEL5_6_INPUTSEL5_Pos)            /*!< 0x00000008 */
#define EPWM_IXBSEL5_6_INPUTSEL5_4               (0x10UL<<EPWM_IXBSEL5_6_INPUTSEL5_Pos)           /*!< 0x00000010 */
#define EPWM_IXBSEL5_6_INPUTSEL5_5               (0x20UL<<EPWM_IXBSEL5_6_INPUTSEL5_Pos)           /*!< 0x00000020 */
#define EPWM_IXBSEL5_6_INPUTSEL6_Pos             (16U)
#define EPWM_IXBSEL5_6_INPUTSEL6_Msk             (0x3FUL<<EPWM_IXBSEL5_6_INPUTSEL6_Pos)           /*!< 0x003F0000 */
#define EPWM_IXBSEL5_6_INPUTSEL6                 EPWM_IXBSEL5_6_INPUTSEL6_Msk                     /*!< eallow, INPUTLOCKx */
#define EPWM_IXBSEL5_6_INPUTSEL6_0               (0x1UL<<EPWM_IXBSEL5_6_INPUTSEL6_Pos)            /*!< 0x00010000 */
#define EPWM_IXBSEL5_6_INPUTSEL6_1               (0x2UL<<EPWM_IXBSEL5_6_INPUTSEL6_Pos)            /*!< 0x00020000 */
#define EPWM_IXBSEL5_6_INPUTSEL6_2               (0x4UL<<EPWM_IXBSEL5_6_INPUTSEL6_Pos)            /*!< 0x00040000 */
#define EPWM_IXBSEL5_6_INPUTSEL6_3               (0x8UL<<EPWM_IXBSEL5_6_INPUTSEL6_Pos)            /*!< 0x00080000 */
#define EPWM_IXBSEL5_6_INPUTSEL6_4               (0x10UL<<EPWM_IXBSEL5_6_INPUTSEL6_Pos)           /*!< 0x00100000 */
#define EPWM_IXBSEL5_6_INPUTSEL6_5               (0x20UL<<EPWM_IXBSEL5_6_INPUTSEL6_Pos)           /*!< 0x00200000 */

/********************************* Bit definition for EPWM_IXBSEL7_8 register **************************************/
#define EPWM_IXBSEL7_8_INPUTSEL7_Pos             (0U)
#define EPWM_IXBSEL7_8_INPUTSEL7_Msk             (0x3FUL<<EPWM_IXBSEL7_8_INPUTSEL7_Pos)           /*!< 0x0000003F */
#define EPWM_IXBSEL7_8_INPUTSEL7                 EPWM_IXBSEL7_8_INPUTSEL7_Msk                     /*!< eallow, INPUTLOCKx */
#define EPWM_IXBSEL7_8_INPUTSEL7_0               (0x1UL<<EPWM_IXBSEL7_8_INPUTSEL7_Pos)            /*!< 0x00000001 */
#define EPWM_IXBSEL7_8_INPUTSEL7_1               (0x2UL<<EPWM_IXBSEL7_8_INPUTSEL7_Pos)            /*!< 0x00000002 */
#define EPWM_IXBSEL7_8_INPUTSEL7_2               (0x4UL<<EPWM_IXBSEL7_8_INPUTSEL7_Pos)            /*!< 0x00000004 */
#define EPWM_IXBSEL7_8_INPUTSEL7_3               (0x8UL<<EPWM_IXBSEL7_8_INPUTSEL7_Pos)            /*!< 0x00000008 */
#define EPWM_IXBSEL7_8_INPUTSEL7_4               (0x10UL<<EPWM_IXBSEL7_8_INPUTSEL7_Pos)           /*!< 0x00000010 */
#define EPWM_IXBSEL7_8_INPUTSEL7_5               (0x20UL<<EPWM_IXBSEL7_8_INPUTSEL7_Pos)           /*!< 0x00000020 */
#define EPWM_IXBSEL7_8_INPUTSEL8_Pos             (16U)
#define EPWM_IXBSEL7_8_INPUTSEL8_Msk             (0x3FUL<<EPWM_IXBSEL7_8_INPUTSEL8_Pos)           /*!< 0x003F0000 */
#define EPWM_IXBSEL7_8_INPUTSEL8                 EPWM_IXBSEL7_8_INPUTSEL8_Msk                     /*!< eallow, INPUTLOCKx */
#define EPWM_IXBSEL7_8_INPUTSEL8_0               (0x1UL<<EPWM_IXBSEL7_8_INPUTSEL8_Pos)            /*!< 0x00010000 */
#define EPWM_IXBSEL7_8_INPUTSEL8_1               (0x2UL<<EPWM_IXBSEL7_8_INPUTSEL8_Pos)            /*!< 0x00020000 */
#define EPWM_IXBSEL7_8_INPUTSEL8_2               (0x4UL<<EPWM_IXBSEL7_8_INPUTSEL8_Pos)            /*!< 0x00040000 */
#define EPWM_IXBSEL7_8_INPUTSEL8_3               (0x8UL<<EPWM_IXBSEL7_8_INPUTSEL8_Pos)            /*!< 0x00080000 */
#define EPWM_IXBSEL7_8_INPUTSEL8_4               (0x10UL<<EPWM_IXBSEL7_8_INPUTSEL8_Pos)           /*!< 0x00100000 */
#define EPWM_IXBSEL7_8_INPUTSEL8_5               (0x20UL<<EPWM_IXBSEL7_8_INPUTSEL8_Pos)           /*!< 0x00200000 */

/********************************* Bit definition for EPWM_IXBSEL9_10 register *************************************/
#define EPWM_IXBSEL9_10_INPUTSEL9_Pos            (0U)
#define EPWM_IXBSEL9_10_INPUTSEL9_Msk            (0x3FUL<<EPWM_IXBSEL9_10_INPUTSEL9_Pos)          /*!< 0x0000003F */
#define EPWM_IXBSEL9_10_INPUTSEL9                EPWM_IXBSEL9_10_INPUTSEL9_Msk                    /*!< eallow, INPUTLOCKx */
#define EPWM_IXBSEL9_10_INPUTSEL9_0              (0x1UL<<EPWM_IXBSEL9_10_INPUTSEL9_Pos)           /*!< 0x00000001 */
#define EPWM_IXBSEL9_10_INPUTSEL9_1              (0x2UL<<EPWM_IXBSEL9_10_INPUTSEL9_Pos)           /*!< 0x00000002 */
#define EPWM_IXBSEL9_10_INPUTSEL9_2              (0x4UL<<EPWM_IXBSEL9_10_INPUTSEL9_Pos)           /*!< 0x00000004 */
#define EPWM_IXBSEL9_10_INPUTSEL9_3              (0x8UL<<EPWM_IXBSEL9_10_INPUTSEL9_Pos)           /*!< 0x00000008 */
#define EPWM_IXBSEL9_10_INPUTSEL9_4              (0x10UL<<EPWM_IXBSEL9_10_INPUTSEL9_Pos)          /*!< 0x00000010 */
#define EPWM_IXBSEL9_10_INPUTSEL9_5              (0x20UL<<EPWM_IXBSEL9_10_INPUTSEL9_Pos)          /*!< 0x00000020 */
#define EPWM_IXBSEL9_10_INPUTSEL10_Pos           (16U)
#define EPWM_IXBSEL9_10_INPUTSEL10_Msk           (0x3FUL<<EPWM_IXBSEL9_10_INPUTSEL10_Pos)         /*!< 0x003F0000 */
#define EPWM_IXBSEL9_10_INPUTSEL10               EPWM_IXBSEL9_10_INPUTSEL10_Msk                   /*!< eallow, INPUTLOCKx */
#define EPWM_IXBSEL9_10_INPUTSEL10_0             (0x1UL<<EPWM_IXBSEL9_10_INPUTSEL10_Pos)          /*!< 0x00010000 */
#define EPWM_IXBSEL9_10_INPUTSEL10_1             (0x2UL<<EPWM_IXBSEL9_10_INPUTSEL10_Pos)          /*!< 0x00020000 */
#define EPWM_IXBSEL9_10_INPUTSEL10_2             (0x4UL<<EPWM_IXBSEL9_10_INPUTSEL10_Pos)          /*!< 0x00040000 */
#define EPWM_IXBSEL9_10_INPUTSEL10_3             (0x8UL<<EPWM_IXBSEL9_10_INPUTSEL10_Pos)          /*!< 0x00080000 */
#define EPWM_IXBSEL9_10_INPUTSEL10_4             (0x10UL<<EPWM_IXBSEL9_10_INPUTSEL10_Pos)         /*!< 0x00100000 */
#define EPWM_IXBSEL9_10_INPUTSEL10_5             (0x20UL<<EPWM_IXBSEL9_10_INPUTSEL10_Pos)         /*!< 0x00200000 */

/********************************* Bit definition for EPWM_IXBSEL11_12 register ************************************/
#define EPWM_IXBSEL11_12_INPUTSEL11_Pos          (0U)
#define EPWM_IXBSEL11_12_INPUTSEL11_Msk          (0x3FUL<<EPWM_IXBSEL11_12_INPUTSEL11_Pos)        /*!< 0x0000003F */
#define EPWM_IXBSEL11_12_INPUTSEL11              EPWM_IXBSEL11_12_INPUTSEL11_Msk                  /*!< eallow, INPUTLOCKx */
#define EPWM_IXBSEL11_12_INPUTSEL11_0            (0x1UL<<EPWM_IXBSEL11_12_INPUTSEL11_Pos)         /*!< 0x00000001 */
#define EPWM_IXBSEL11_12_INPUTSEL11_1            (0x2UL<<EPWM_IXBSEL11_12_INPUTSEL11_Pos)         /*!< 0x00000002 */
#define EPWM_IXBSEL11_12_INPUTSEL11_2            (0x4UL<<EPWM_IXBSEL11_12_INPUTSEL11_Pos)         /*!< 0x00000004 */
#define EPWM_IXBSEL11_12_INPUTSEL11_3            (0x8UL<<EPWM_IXBSEL11_12_INPUTSEL11_Pos)         /*!< 0x00000008 */
#define EPWM_IXBSEL11_12_INPUTSEL11_4            (0x10UL<<EPWM_IXBSEL11_12_INPUTSEL11_Pos)        /*!< 0x00000010 */
#define EPWM_IXBSEL11_12_INPUTSEL11_5            (0x20UL<<EPWM_IXBSEL11_12_INPUTSEL11_Pos)        /*!< 0x00000020 */
#define EPWM_IXBSEL11_12_INPUTSEL12_Pos          (16U)
#define EPWM_IXBSEL11_12_INPUTSEL12_Msk          (0x3FUL<<EPWM_IXBSEL11_12_INPUTSEL12_Pos)        /*!< 0x003F0000 */
#define EPWM_IXBSEL11_12_INPUTSEL12              EPWM_IXBSEL11_12_INPUTSEL12_Msk                  /*!< eallow, INPUTLOCKx */
#define EPWM_IXBSEL11_12_INPUTSEL12_0            (0x1UL<<EPWM_IXBSEL11_12_INPUTSEL12_Pos)         /*!< 0x00010000 */
#define EPWM_IXBSEL11_12_INPUTSEL12_1            (0x2UL<<EPWM_IXBSEL11_12_INPUTSEL12_Pos)         /*!< 0x00020000 */
#define EPWM_IXBSEL11_12_INPUTSEL12_2            (0x4UL<<EPWM_IXBSEL11_12_INPUTSEL12_Pos)         /*!< 0x00040000 */
#define EPWM_IXBSEL11_12_INPUTSEL12_3            (0x8UL<<EPWM_IXBSEL11_12_INPUTSEL12_Pos)         /*!< 0x00080000 */
#define EPWM_IXBSEL11_12_INPUTSEL12_4            (0x10UL<<EPWM_IXBSEL11_12_INPUTSEL12_Pos)        /*!< 0x00100000 */
#define EPWM_IXBSEL11_12_INPUTSEL12_5            (0x20UL<<EPWM_IXBSEL11_12_INPUTSEL12_Pos)        /*!< 0x00200000 */

/********************************* Bit definition for EPWM_IXBSEL13_14 register ************************************/
#define EPWM_IXBSEL13_14_INPUTSEL13_Pos          (0U)
#define EPWM_IXBSEL13_14_INPUTSEL13_Msk          (0x3FUL<<EPWM_IXBSEL13_14_INPUTSEL13_Pos)        /*!< 0x0000003F */
#define EPWM_IXBSEL13_14_INPUTSEL13              EPWM_IXBSEL13_14_INPUTSEL13_Msk                  /*!< eallow, INPUTLOCKx */
#define EPWM_IXBSEL13_14_INPUTSEL13_0            (0x1UL<<EPWM_IXBSEL13_14_INPUTSEL13_Pos)         /*!< 0x00000001 */
#define EPWM_IXBSEL13_14_INPUTSEL13_1            (0x2UL<<EPWM_IXBSEL13_14_INPUTSEL13_Pos)         /*!< 0x00000002 */
#define EPWM_IXBSEL13_14_INPUTSEL13_2            (0x4UL<<EPWM_IXBSEL13_14_INPUTSEL13_Pos)         /*!< 0x00000004 */
#define EPWM_IXBSEL13_14_INPUTSEL13_3            (0x8UL<<EPWM_IXBSEL13_14_INPUTSEL13_Pos)         /*!< 0x00000008 */
#define EPWM_IXBSEL13_14_INPUTSEL13_4            (0x10UL<<EPWM_IXBSEL13_14_INPUTSEL13_Pos)        /*!< 0x00000010 */
#define EPWM_IXBSEL13_14_INPUTSEL13_5            (0x20UL<<EPWM_IXBSEL13_14_INPUTSEL13_Pos)        /*!< 0x00000020 */
#define EPWM_IXBSEL13_14_INPUTSEL14_Pos          (16U)
#define EPWM_IXBSEL13_14_INPUTSEL14_Msk          (0x3FUL<<EPWM_IXBSEL13_14_INPUTSEL14_Pos)        /*!< 0x003F0000 */
#define EPWM_IXBSEL13_14_INPUTSEL14              EPWM_IXBSEL13_14_INPUTSEL14_Msk                  /*!< eallow, INPUTLOCKx */
#define EPWM_IXBSEL13_14_INPUTSEL14_0            (0x1UL<<EPWM_IXBSEL13_14_INPUTSEL14_Pos)         /*!< 0x00010000 */
#define EPWM_IXBSEL13_14_INPUTSEL14_1            (0x2UL<<EPWM_IXBSEL13_14_INPUTSEL14_Pos)         /*!< 0x00020000 */
#define EPWM_IXBSEL13_14_INPUTSEL14_2            (0x4UL<<EPWM_IXBSEL13_14_INPUTSEL14_Pos)         /*!< 0x00040000 */
#define EPWM_IXBSEL13_14_INPUTSEL14_3            (0x8UL<<EPWM_IXBSEL13_14_INPUTSEL14_Pos)         /*!< 0x00080000 */
#define EPWM_IXBSEL13_14_INPUTSEL14_4            (0x10UL<<EPWM_IXBSEL13_14_INPUTSEL14_Pos)        /*!< 0x00100000 */
#define EPWM_IXBSEL13_14_INPUTSEL14_5            (0x20UL<<EPWM_IXBSEL13_14_INPUTSEL14_Pos)        /*!< 0x00200000 */

/********************************* Bit definition for EPWM_IXBAQSEL register ***************************************/
#define EPWM_IXBAQSEL_AQSEL1_Pos                 (0U)
#define EPWM_IXBAQSEL_AQSEL1_Msk                 (0x3UL<<EPWM_IXBAQSEL_AQSEL1_Pos)                /*!< 0x00000003 */
#define EPWM_IXBAQSEL_AQSEL1                     EPWM_IXBAQSEL_AQSEL1_Msk                         /*!< eallow, FILTERLOCK */
#define EPWM_IXBAQSEL_AQSEL1_0                   (0x1UL<<EPWM_IXBAQSEL_AQSEL1_Pos)                /*!< 0x00000001 */
#define EPWM_IXBAQSEL_AQSEL1_1                   (0x2UL<<EPWM_IXBAQSEL_AQSEL1_Pos)                /*!< 0x00000002 */
#define EPWM_IXBAQSEL_AQSEL2_Pos                 (2U)
#define EPWM_IXBAQSEL_AQSEL2_Msk                 (0x3UL<<EPWM_IXBAQSEL_AQSEL2_Pos)                /*!< 0x0000000C */
#define EPWM_IXBAQSEL_AQSEL2                     EPWM_IXBAQSEL_AQSEL2_Msk                         /*!< eallow, FILTERLOCK */
#define EPWM_IXBAQSEL_AQSEL2_0                   (0x1UL<<EPWM_IXBAQSEL_AQSEL2_Pos)                /*!< 0x00000004 */
#define EPWM_IXBAQSEL_AQSEL2_1                   (0x2UL<<EPWM_IXBAQSEL_AQSEL2_Pos)                /*!< 0x00000008 */
#define EPWM_IXBAQSEL_AQSEL3_Pos                 (4U)
#define EPWM_IXBAQSEL_AQSEL3_Msk                 (0x3UL<<EPWM_IXBAQSEL_AQSEL3_Pos)                /*!< 0x00000030 */
#define EPWM_IXBAQSEL_AQSEL3                     EPWM_IXBAQSEL_AQSEL3_Msk                         /*!< eallow, FILTERLOCK */
#define EPWM_IXBAQSEL_AQSEL3_0                   (0x1UL<<EPWM_IXBAQSEL_AQSEL3_Pos)                /*!< 0x00000010 */
#define EPWM_IXBAQSEL_AQSEL3_1                   (0x2UL<<EPWM_IXBAQSEL_AQSEL3_Pos)                /*!< 0x00000020 */
#define EPWM_IXBAQSEL_AQSEL4_Pos                 (6U)
#define EPWM_IXBAQSEL_AQSEL4_Msk                 (0x3UL<<EPWM_IXBAQSEL_AQSEL4_Pos)                /*!< 0x000000C0 */
#define EPWM_IXBAQSEL_AQSEL4                     EPWM_IXBAQSEL_AQSEL4_Msk                         /*!< eallow, FILTERLOCK */
#define EPWM_IXBAQSEL_AQSEL4_0                   (0x1UL<<EPWM_IXBAQSEL_AQSEL4_Pos)                /*!< 0x00000040 */
#define EPWM_IXBAQSEL_AQSEL4_1                   (0x2UL<<EPWM_IXBAQSEL_AQSEL4_Pos)                /*!< 0x00000080 */
#define EPWM_IXBAQSEL_AQSEL5_Pos                 (8U)
#define EPWM_IXBAQSEL_AQSEL5_Msk                 (0x3UL<<EPWM_IXBAQSEL_AQSEL5_Pos)                /*!< 0x00000300 */
#define EPWM_IXBAQSEL_AQSEL5                     EPWM_IXBAQSEL_AQSEL5_Msk                         /*!< eallow, FILTERLOCK */
#define EPWM_IXBAQSEL_AQSEL5_0                   (0x1UL<<EPWM_IXBAQSEL_AQSEL5_Pos)                /*!< 0x00000100 */
#define EPWM_IXBAQSEL_AQSEL5_1                   (0x2UL<<EPWM_IXBAQSEL_AQSEL5_Pos)                /*!< 0x00000200 */
#define EPWM_IXBAQSEL_AQSEL6_Pos                 (10U)
#define EPWM_IXBAQSEL_AQSEL6_Msk                 (0x3UL<<EPWM_IXBAQSEL_AQSEL6_Pos)                /*!< 0x00000C00 */
#define EPWM_IXBAQSEL_AQSEL6                     EPWM_IXBAQSEL_AQSEL6_Msk                         /*!< eallow, FILTERLOCK */
#define EPWM_IXBAQSEL_AQSEL6_0                   (0x1UL<<EPWM_IXBAQSEL_AQSEL6_Pos)                /*!< 0x00000400 */
#define EPWM_IXBAQSEL_AQSEL6_1                   (0x2UL<<EPWM_IXBAQSEL_AQSEL6_Pos)                /*!< 0x00000800 */
#define EPWM_IXBAQSEL_AQSEL7_Pos                 (12U)
#define EPWM_IXBAQSEL_AQSEL7_Msk                 (0x3UL<<EPWM_IXBAQSEL_AQSEL7_Pos)                /*!< 0x00003000 */
#define EPWM_IXBAQSEL_AQSEL7                     EPWM_IXBAQSEL_AQSEL7_Msk                         /*!< eallow, FILTERLOCK */
#define EPWM_IXBAQSEL_AQSEL7_0                   (0x1UL<<EPWM_IXBAQSEL_AQSEL7_Pos)                /*!< 0x00001000 */
#define EPWM_IXBAQSEL_AQSEL7_1                   (0x2UL<<EPWM_IXBAQSEL_AQSEL7_Pos)                /*!< 0x00002000 */
#define EPWM_IXBAQSEL_AQSEL8_Pos                 (14U)
#define EPWM_IXBAQSEL_AQSEL8_Msk                 (0x3UL<<EPWM_IXBAQSEL_AQSEL8_Pos)                /*!< 0x0000C000 */
#define EPWM_IXBAQSEL_AQSEL8                     EPWM_IXBAQSEL_AQSEL8_Msk                         /*!< eallow, FILTERLOCK */
#define EPWM_IXBAQSEL_AQSEL8_0                   (0x1UL<<EPWM_IXBAQSEL_AQSEL8_Pos)                /*!< 0x00004000 */
#define EPWM_IXBAQSEL_AQSEL8_1                   (0x2UL<<EPWM_IXBAQSEL_AQSEL8_Pos)                /*!< 0x00008000 */
#define EPWM_IXBAQSEL_AQSEL9_Pos                 (16U)
#define EPWM_IXBAQSEL_AQSEL9_Msk                 (0x3UL<<EPWM_IXBAQSEL_AQSEL9_Pos)                /*!< 0x00030000 */
#define EPWM_IXBAQSEL_AQSEL9                     EPWM_IXBAQSEL_AQSEL9_Msk                         /*!< eallow, FILTERLOCK */
#define EPWM_IXBAQSEL_AQSEL9_0                   (0x1UL<<EPWM_IXBAQSEL_AQSEL9_Pos)                /*!< 0x00010000 */
#define EPWM_IXBAQSEL_AQSEL9_1                   (0x2UL<<EPWM_IXBAQSEL_AQSEL9_Pos)                /*!< 0x00020000 */
#define EPWM_IXBAQSEL_AQSEL10_Pos                (18U)
#define EPWM_IXBAQSEL_AQSEL10_Msk                (0x3UL<<EPWM_IXBAQSEL_AQSEL10_Pos)               /*!< 0x000C0000 */
#define EPWM_IXBAQSEL_AQSEL10                    EPWM_IXBAQSEL_AQSEL10_Msk                        /*!< eallow, FILTERLOCK */
#define EPWM_IXBAQSEL_AQSEL10_0                  (0x1UL<<EPWM_IXBAQSEL_AQSEL10_Pos)               /*!< 0x00040000 */
#define EPWM_IXBAQSEL_AQSEL10_1                  (0x2UL<<EPWM_IXBAQSEL_AQSEL10_Pos)               /*!< 0x00080000 */
#define EPWM_IXBAQSEL_AQSEL11_Pos                (20U)
#define EPWM_IXBAQSEL_AQSEL11_Msk                (0x3UL<<EPWM_IXBAQSEL_AQSEL11_Pos)               /*!< 0x00300000 */
#define EPWM_IXBAQSEL_AQSEL11                    EPWM_IXBAQSEL_AQSEL11_Msk                        /*!< eallow, FILTERLOCK */
#define EPWM_IXBAQSEL_AQSEL11_0                  (0x1UL<<EPWM_IXBAQSEL_AQSEL11_Pos)               /*!< 0x00100000 */
#define EPWM_IXBAQSEL_AQSEL11_1                  (0x2UL<<EPWM_IXBAQSEL_AQSEL11_Pos)               /*!< 0x00200000 */
#define EPWM_IXBAQSEL_AQSEL12_Pos                (22U)
#define EPWM_IXBAQSEL_AQSEL12_Msk                (0x3UL<<EPWM_IXBAQSEL_AQSEL12_Pos)               /*!< 0x00C00000 */
#define EPWM_IXBAQSEL_AQSEL12                    EPWM_IXBAQSEL_AQSEL12_Msk                        /*!< eallow, FILTERLOCK */
#define EPWM_IXBAQSEL_AQSEL12_0                  (0x1UL<<EPWM_IXBAQSEL_AQSEL12_Pos)               /*!< 0x00400000 */
#define EPWM_IXBAQSEL_AQSEL12_1                  (0x2UL<<EPWM_IXBAQSEL_AQSEL12_Pos)               /*!< 0x00800000 */
#define EPWM_IXBAQSEL_AQSEL13_Pos                (24U)
#define EPWM_IXBAQSEL_AQSEL13_Msk                (0x3UL<<EPWM_IXBAQSEL_AQSEL13_Pos)               /*!< 0x03000000 */
#define EPWM_IXBAQSEL_AQSEL13                    EPWM_IXBAQSEL_AQSEL13_Msk                        /*!< eallow, FILTERLOCK */
#define EPWM_IXBAQSEL_AQSEL13_0                  (0x1UL<<EPWM_IXBAQSEL_AQSEL13_Pos)               /*!< 0x01000000 */
#define EPWM_IXBAQSEL_AQSEL13_1                  (0x2UL<<EPWM_IXBAQSEL_AQSEL13_Pos)               /*!< 0x02000000 */
#define EPWM_IXBAQSEL_AQSEL14_Pos                (26U)
#define EPWM_IXBAQSEL_AQSEL14_Msk                (0x3UL<<EPWM_IXBAQSEL_AQSEL14_Pos)               /*!< 0x0C000000 */
#define EPWM_IXBAQSEL_AQSEL14                    EPWM_IXBAQSEL_AQSEL14_Msk                        /*!< eallow, FILTERLOCK */
#define EPWM_IXBAQSEL_AQSEL14_0                  (0x1UL<<EPWM_IXBAQSEL_AQSEL14_Pos)               /*!< 0x04000000 */
#define EPWM_IXBAQSEL_AQSEL14_1                  (0x2UL<<EPWM_IXBAQSEL_AQSEL14_Pos)               /*!< 0x08000000 */

/********************************* Bit definition for EPWM_IXBSEL_LOCK register ************************************/
#define EPWM_IXBSEL_LOCK_INPUTLOCK1_Pos          (0U)
#define EPWM_IXBSEL_LOCK_INPUTLOCK1_Msk          (0x1UL<<EPWM_IXBSEL_LOCK_INPUTLOCK1_Pos)         /*!< 0x00000001 */
#define EPWM_IXBSEL_LOCK_INPUTLOCK1              EPWM_IXBSEL_LOCK_INPUTLOCK1_Msk                  /*!< eallow */
#define EPWM_IXBSEL_LOCK_INPUTLOCK2_Pos          (1U)
#define EPWM_IXBSEL_LOCK_INPUTLOCK2_Msk          (0x1UL<<EPWM_IXBSEL_LOCK_INPUTLOCK2_Pos)         /*!< 0x00000002 */
#define EPWM_IXBSEL_LOCK_INPUTLOCK2              EPWM_IXBSEL_LOCK_INPUTLOCK2_Msk                  /*!< eallow */
#define EPWM_IXBSEL_LOCK_INPUTLOCK3_Pos          (2U)
#define EPWM_IXBSEL_LOCK_INPUTLOCK3_Msk          (0x1UL<<EPWM_IXBSEL_LOCK_INPUTLOCK3_Pos)         /*!< 0x00000004 */
#define EPWM_IXBSEL_LOCK_INPUTLOCK3              EPWM_IXBSEL_LOCK_INPUTLOCK3_Msk                  /*!< eallow */
#define EPWM_IXBSEL_LOCK_INPUTLOCK4_Pos          (3U)
#define EPWM_IXBSEL_LOCK_INPUTLOCK4_Msk          (0x1UL<<EPWM_IXBSEL_LOCK_INPUTLOCK4_Pos)         /*!< 0x00000008 */
#define EPWM_IXBSEL_LOCK_INPUTLOCK4              EPWM_IXBSEL_LOCK_INPUTLOCK4_Msk                  /*!< eallow */
#define EPWM_IXBSEL_LOCK_INPUTLOCK5_Pos          (4U)
#define EPWM_IXBSEL_LOCK_INPUTLOCK5_Msk          (0x1UL<<EPWM_IXBSEL_LOCK_INPUTLOCK5_Pos)         /*!< 0x00000010 */
#define EPWM_IXBSEL_LOCK_INPUTLOCK5              EPWM_IXBSEL_LOCK_INPUTLOCK5_Msk                  /*!< eallow */
#define EPWM_IXBSEL_LOCK_INPUTLOCK6_Pos          (5U)
#define EPWM_IXBSEL_LOCK_INPUTLOCK6_Msk          (0x1UL<<EPWM_IXBSEL_LOCK_INPUTLOCK6_Pos)         /*!< 0x00000020 */
#define EPWM_IXBSEL_LOCK_INPUTLOCK6              EPWM_IXBSEL_LOCK_INPUTLOCK6_Msk                  /*!< eallow */
#define EPWM_IXBSEL_LOCK_INPUTLOCK7_Pos          (6U)
#define EPWM_IXBSEL_LOCK_INPUTLOCK7_Msk          (0x1UL<<EPWM_IXBSEL_LOCK_INPUTLOCK7_Pos)         /*!< 0x00000040 */
#define EPWM_IXBSEL_LOCK_INPUTLOCK7              EPWM_IXBSEL_LOCK_INPUTLOCK7_Msk                  /*!< eallow */
#define EPWM_IXBSEL_LOCK_INPUTLOCK8_Pos          (7U)
#define EPWM_IXBSEL_LOCK_INPUTLOCK8_Msk          (0x1UL<<EPWM_IXBSEL_LOCK_INPUTLOCK8_Pos)         /*!< 0x00000080 */
#define EPWM_IXBSEL_LOCK_INPUTLOCK8              EPWM_IXBSEL_LOCK_INPUTLOCK8_Msk                  /*!< eallow */
#define EPWM_IXBSEL_LOCK_INPUTLOCK9_Pos          (8U)
#define EPWM_IXBSEL_LOCK_INPUTLOCK9_Msk          (0x1UL<<EPWM_IXBSEL_LOCK_INPUTLOCK9_Pos)         /*!< 0x00000100 */
#define EPWM_IXBSEL_LOCK_INPUTLOCK9              EPWM_IXBSEL_LOCK_INPUTLOCK9_Msk                  /*!< eallow */
#define EPWM_IXBSEL_LOCK_INPUTLOCK10_Pos         (9U)
#define EPWM_IXBSEL_LOCK_INPUTLOCK10_Msk         (0x1UL<<EPWM_IXBSEL_LOCK_INPUTLOCK10_Pos)        /*!< 0x00000200 */
#define EPWM_IXBSEL_LOCK_INPUTLOCK10             EPWM_IXBSEL_LOCK_INPUTLOCK10_Msk                 /*!< eallow */
#define EPWM_IXBSEL_LOCK_INPUTLOCK11_Pos         (10U)
#define EPWM_IXBSEL_LOCK_INPUTLOCK11_Msk         (0x1UL<<EPWM_IXBSEL_LOCK_INPUTLOCK11_Pos)        /*!< 0x00000400 */
#define EPWM_IXBSEL_LOCK_INPUTLOCK11             EPWM_IXBSEL_LOCK_INPUTLOCK11_Msk                 /*!< eallow */
#define EPWM_IXBSEL_LOCK_INPUTLOCK12_Pos         (11U)
#define EPWM_IXBSEL_LOCK_INPUTLOCK12_Msk         (0x1UL<<EPWM_IXBSEL_LOCK_INPUTLOCK12_Pos)        /*!< 0x00000800 */
#define EPWM_IXBSEL_LOCK_INPUTLOCK12             EPWM_IXBSEL_LOCK_INPUTLOCK12_Msk                 /*!< eallow */
#define EPWM_IXBSEL_LOCK_INPUTLOCK13_Pos         (12U)
#define EPWM_IXBSEL_LOCK_INPUTLOCK13_Msk         (0x1UL<<EPWM_IXBSEL_LOCK_INPUTLOCK13_Pos)        /*!< 0x00001000 */
#define EPWM_IXBSEL_LOCK_INPUTLOCK13             EPWM_IXBSEL_LOCK_INPUTLOCK13_Msk                 /*!< eallow */
#define EPWM_IXBSEL_LOCK_INPUTLOCK14_Pos         (13U)
#define EPWM_IXBSEL_LOCK_INPUTLOCK14_Msk         (0x1UL<<EPWM_IXBSEL_LOCK_INPUTLOCK14_Pos)        /*!< 0x00002000 */
#define EPWM_IXBSEL_LOCK_INPUTLOCK14             EPWM_IXBSEL_LOCK_INPUTLOCK14_Msk                 /*!< eallow */
#define EPWM_IXBSEL_LOCK_FILTERLOCK_Pos          (31U)
#define EPWM_IXBSEL_LOCK_FILTERLOCK_Msk          (0x1UL<<EPWM_IXBSEL_LOCK_FILTERLOCK_Pos)         /*!< 0x80000000 */
#define EPWM_IXBSEL_LOCK_FILTERLOCK              EPWM_IXBSEL_LOCK_FILTERLOCK_Msk                  /*!< eallow */

/********************************* Bit definition for EPWM_IXBCTRL register ****************************************/
#define EPWM_IXBCTRL_ISAPRD0_Pos                 (0U)
#define EPWM_IXBCTRL_ISAPRD0_Msk                 (0xFFUL<<EPWM_IXBCTRL_ISAPRD0_Pos)               /*!< 0x000000FF */
#define EPWM_IXBCTRL_ISAPRD0                     EPWM_IXBCTRL_ISAPRD0_Msk                         /*!< eallow, FILTERLOCK */
#define EPWM_IXBCTRL_ISAPRD1_Pos                 (8U)
#define EPWM_IXBCTRL_ISAPRD1_Msk                 (0xFFUL<<EPWM_IXBCTRL_ISAPRD1_Pos)               /*!< 0x0000FF00 */
#define EPWM_IXBCTRL_ISAPRD1                     EPWM_IXBCTRL_ISAPRD1_Msk                         /*!< eallow, FILTERLOCK */

/********************************* Bit definition for EPWM_HXB4_0 register *****************************************/
#define EPWM_HXB4_0_MUX0_Pos                     (0U)
#define EPWM_HXB4_0_MUX0_Msk                     (0x3UL<<EPWM_HXB4_0_MUX0_Pos)                    /*!< 0x00000003 */
#define EPWM_HXB4_0_MUX0                         EPWM_HXB4_0_MUX0_Msk                             /*!< eallow, HXBLOCK */
#define EPWM_HXB4_0_MUX0_0                       (0x1UL<<EPWM_HXB4_0_MUX0_Pos)                    /*!< 0x00000001 */
#define EPWM_HXB4_0_MUX0_1                       (0x2UL<<EPWM_HXB4_0_MUX0_Pos)                    /*!< 0x00000002 */
#define EPWM_HXB4_0_MUX1_Pos                     (2U)
#define EPWM_HXB4_0_MUX1_Msk                     (0x3UL<<EPWM_HXB4_0_MUX1_Pos)                    /*!< 0x0000000C */
#define EPWM_HXB4_0_MUX1                         EPWM_HXB4_0_MUX1_Msk                             /*!< eallow, HXBLOCK */
#define EPWM_HXB4_0_MUX1_0                       (0x1UL<<EPWM_HXB4_0_MUX1_Pos)                    /*!< 0x00000004 */
#define EPWM_HXB4_0_MUX1_1                       (0x2UL<<EPWM_HXB4_0_MUX1_Pos)                    /*!< 0x00000008 */
#define EPWM_HXB4_0_MUX2_Pos                     (4U)
#define EPWM_HXB4_0_MUX2_Msk                     (0x3UL<<EPWM_HXB4_0_MUX2_Pos)                    /*!< 0x00000030 */
#define EPWM_HXB4_0_MUX2                         EPWM_HXB4_0_MUX2_Msk                             /*!< eallow, HXBLOCK */
#define EPWM_HXB4_0_MUX2_0                       (0x1UL<<EPWM_HXB4_0_MUX2_Pos)                    /*!< 0x00000010 */
#define EPWM_HXB4_0_MUX2_1                       (0x2UL<<EPWM_HXB4_0_MUX2_Pos)                    /*!< 0x00000020 */
#define EPWM_HXB4_0_MUX3_Pos                     (6U)
#define EPWM_HXB4_0_MUX3_Msk                     (0x3UL<<EPWM_HXB4_0_MUX3_Pos)                    /*!< 0x000000C0 */
#define EPWM_HXB4_0_MUX3                         EPWM_HXB4_0_MUX3_Msk                             /*!< eallow, HXBLOCK */
#define EPWM_HXB4_0_MUX3_0                       (0x1UL<<EPWM_HXB4_0_MUX3_Pos)                    /*!< 0x00000040 */
#define EPWM_HXB4_0_MUX3_1                       (0x2UL<<EPWM_HXB4_0_MUX3_Pos)                    /*!< 0x00000080 */
#define EPWM_HXB4_0_MUX4_Pos                     (8U)
#define EPWM_HXB4_0_MUX4_Msk                     (0x3UL<<EPWM_HXB4_0_MUX4_Pos)                    /*!< 0x00000300 */
#define EPWM_HXB4_0_MUX4                         EPWM_HXB4_0_MUX4_Msk                             /*!< eallow, HXBLOCK */
#define EPWM_HXB4_0_MUX4_0                       (0x1UL<<EPWM_HXB4_0_MUX4_Pos)                    /*!< 0x00000100 */
#define EPWM_HXB4_0_MUX4_1                       (0x2UL<<EPWM_HXB4_0_MUX4_Pos)                    /*!< 0x00000200 */
#define EPWM_HXB4_0_MUX5_Pos                     (10U)
#define EPWM_HXB4_0_MUX5_Msk                     (0x3UL<<EPWM_HXB4_0_MUX5_Pos)                    /*!< 0x00000C00 */
#define EPWM_HXB4_0_MUX5                         EPWM_HXB4_0_MUX5_Msk                             /*!< eallow, HXBLOCK */
#define EPWM_HXB4_0_MUX5_0                       (0x1UL<<EPWM_HXB4_0_MUX5_Pos)                    /*!< 0x00000400 */
#define EPWM_HXB4_0_MUX5_1                       (0x2UL<<EPWM_HXB4_0_MUX5_Pos)                    /*!< 0x00000800 */
#define EPWM_HXB4_0_MUX6_Pos                     (12U)
#define EPWM_HXB4_0_MUX6_Msk                     (0x3UL<<EPWM_HXB4_0_MUX6_Pos)                    /*!< 0x00003000 */
#define EPWM_HXB4_0_MUX6                         EPWM_HXB4_0_MUX6_Msk                             /*!< eallow, HXBLOCK */
#define EPWM_HXB4_0_MUX6_0                       (0x1UL<<EPWM_HXB4_0_MUX6_Pos)                    /*!< 0x00001000 */
#define EPWM_HXB4_0_MUX6_1                       (0x2UL<<EPWM_HXB4_0_MUX6_Pos)                    /*!< 0x00002000 */
#define EPWM_HXB4_0_MUX7_Pos                     (14U)
#define EPWM_HXB4_0_MUX7_Msk                     (0x3UL<<EPWM_HXB4_0_MUX7_Pos)                    /*!< 0x0000C000 */
#define EPWM_HXB4_0_MUX7                         EPWM_HXB4_0_MUX7_Msk                             /*!< eallow, HXBLOCK */
#define EPWM_HXB4_0_MUX7_0                       (0x1UL<<EPWM_HXB4_0_MUX7_Pos)                    /*!< 0x00004000 */
#define EPWM_HXB4_0_MUX7_1                       (0x2UL<<EPWM_HXB4_0_MUX7_Pos)                    /*!< 0x00008000 */
#define EPWM_HXB4_0_MUX8_Pos                     (16U)
#define EPWM_HXB4_0_MUX8_Msk                     (0x3UL<<EPWM_HXB4_0_MUX8_Pos)                    /*!< 0x00030000 */
#define EPWM_HXB4_0_MUX8                         EPWM_HXB4_0_MUX8_Msk                             /*!< eallow, HXBLOCK */
#define EPWM_HXB4_0_MUX8_0                       (0x1UL<<EPWM_HXB4_0_MUX8_Pos)                    /*!< 0x00010000 */
#define EPWM_HXB4_0_MUX8_1                       (0x2UL<<EPWM_HXB4_0_MUX8_Pos)                    /*!< 0x00020000 */
#define EPWM_HXB4_0_MUX9_Pos                     (18U)
#define EPWM_HXB4_0_MUX9_Msk                     (0x3UL<<EPWM_HXB4_0_MUX9_Pos)                    /*!< 0x000C0000 */
#define EPWM_HXB4_0_MUX9                         EPWM_HXB4_0_MUX9_Msk                             /*!< eallow, HXBLOCK */
#define EPWM_HXB4_0_MUX9_0                       (0x1UL<<EPWM_HXB4_0_MUX9_Pos)                    /*!< 0x00040000 */
#define EPWM_HXB4_0_MUX9_1                       (0x2UL<<EPWM_HXB4_0_MUX9_Pos)                    /*!< 0x00080000 */
#define EPWM_HXB4_0_MUX10_Pos                    (20U)
#define EPWM_HXB4_0_MUX10_Msk                    (0x3UL<<EPWM_HXB4_0_MUX10_Pos)                   /*!< 0x00300000 */
#define EPWM_HXB4_0_MUX10                        EPWM_HXB4_0_MUX10_Msk                            /*!< eallow, HXBLOCK */
#define EPWM_HXB4_0_MUX10_0                      (0x1UL<<EPWM_HXB4_0_MUX10_Pos)                   /*!< 0x00100000 */
#define EPWM_HXB4_0_MUX10_1                      (0x2UL<<EPWM_HXB4_0_MUX10_Pos)                   /*!< 0x00200000 */
#define EPWM_HXB4_0_MUX11_Pos                    (22U)
#define EPWM_HXB4_0_MUX11_Msk                    (0x3UL<<EPWM_HXB4_0_MUX11_Pos)                   /*!< 0x00C00000 */
#define EPWM_HXB4_0_MUX11                        EPWM_HXB4_0_MUX11_Msk                            /*!< eallow, HXBLOCK */
#define EPWM_HXB4_0_MUX11_0                      (0x1UL<<EPWM_HXB4_0_MUX11_Pos)                   /*!< 0x00400000 */
#define EPWM_HXB4_0_MUX11_1                      (0x2UL<<EPWM_HXB4_0_MUX11_Pos)                   /*!< 0x00800000 */
#define EPWM_HXB4_0_MUX12_Pos                    (24U)
#define EPWM_HXB4_0_MUX12_Msk                    (0x3UL<<EPWM_HXB4_0_MUX12_Pos)                   /*!< 0x03000000 */
#define EPWM_HXB4_0_MUX12                        EPWM_HXB4_0_MUX12_Msk                            /*!< eallow, HXBLOCK */
#define EPWM_HXB4_0_MUX12_0                      (0x1UL<<EPWM_HXB4_0_MUX12_Pos)                   /*!< 0x01000000 */
#define EPWM_HXB4_0_MUX12_1                      (0x2UL<<EPWM_HXB4_0_MUX12_Pos)                   /*!< 0x02000000 */
#define EPWM_HXB4_0_MUX13_Pos                    (26U)
#define EPWM_HXB4_0_MUX13_Msk                    (0x3UL<<EPWM_HXB4_0_MUX13_Pos)                   /*!< 0x0C000000 */
#define EPWM_HXB4_0_MUX13                        EPWM_HXB4_0_MUX13_Msk                            /*!< eallow, HXBLOCK */
#define EPWM_HXB4_0_MUX13_0                      (0x1UL<<EPWM_HXB4_0_MUX13_Pos)                   /*!< 0x04000000 */
#define EPWM_HXB4_0_MUX13_1                      (0x2UL<<EPWM_HXB4_0_MUX13_Pos)                   /*!< 0x08000000 */
#define EPWM_HXB4_0_MUX14_Pos                    (28U)
#define EPWM_HXB4_0_MUX14_Msk                    (0x3UL<<EPWM_HXB4_0_MUX14_Pos)                   /*!< 0x30000000 */
#define EPWM_HXB4_0_MUX14                        EPWM_HXB4_0_MUX14_Msk                            /*!< eallow, HXBLOCK */
#define EPWM_HXB4_0_MUX14_0                      (0x1UL<<EPWM_HXB4_0_MUX14_Pos)                   /*!< 0x10000000 */
#define EPWM_HXB4_0_MUX14_1                      (0x2UL<<EPWM_HXB4_0_MUX14_Pos)                   /*!< 0x20000000 */
#define EPWM_HXB4_0_MUX15_Pos                    (30U)
#define EPWM_HXB4_0_MUX15_Msk                    (0x3UL<<EPWM_HXB4_0_MUX15_Pos)                   /*!< 0xC0000000 */
#define EPWM_HXB4_0_MUX15                        EPWM_HXB4_0_MUX15_Msk                            /*!< eallow, HXBLOCK */
#define EPWM_HXB4_0_MUX15_0                      (0x1UL<<EPWM_HXB4_0_MUX15_Pos)                   /*!< 0x40000000 */
#define EPWM_HXB4_0_MUX15_1                      (0x2UL<<EPWM_HXB4_0_MUX15_Pos)                   /*!< 0x80000000 */

/********************************* Bit definition for EPWM_HXB4_1 register *****************************************/
#define EPWM_HXB4_1_MUX16_Pos                    (0U)
#define EPWM_HXB4_1_MUX16_Msk                    (0x3UL<<EPWM_HXB4_1_MUX16_Pos)                   /*!< 0x00000003 */
#define EPWM_HXB4_1_MUX16                        EPWM_HXB4_1_MUX16_Msk                            /*!< eallow, HXBLOCK */
#define EPWM_HXB4_1_MUX16_0                      (0x1UL<<EPWM_HXB4_1_MUX16_Pos)                   /*!< 0x00000001 */
#define EPWM_HXB4_1_MUX16_1                      (0x2UL<<EPWM_HXB4_1_MUX16_Pos)                   /*!< 0x00000002 */
#define EPWM_HXB4_1_MUX17_Pos                    (2U)
#define EPWM_HXB4_1_MUX17_Msk                    (0x3UL<<EPWM_HXB4_1_MUX17_Pos)                   /*!< 0x0000000C */
#define EPWM_HXB4_1_MUX17                        EPWM_HXB4_1_MUX17_Msk                            /*!< eallow, HXBLOCK */
#define EPWM_HXB4_1_MUX17_0                      (0x1UL<<EPWM_HXB4_1_MUX17_Pos)                   /*!< 0x00000004 */
#define EPWM_HXB4_1_MUX17_1                      (0x2UL<<EPWM_HXB4_1_MUX17_Pos)                   /*!< 0x00000008 */
#define EPWM_HXB4_1_MUX18_Pos                    (4U)
#define EPWM_HXB4_1_MUX18_Msk                    (0x3UL<<EPWM_HXB4_1_MUX18_Pos)                   /*!< 0x00000030 */
#define EPWM_HXB4_1_MUX18                        EPWM_HXB4_1_MUX18_Msk                            /*!< eallow, HXBLOCK */
#define EPWM_HXB4_1_MUX18_0                      (0x1UL<<EPWM_HXB4_1_MUX18_Pos)                   /*!< 0x00000010 */
#define EPWM_HXB4_1_MUX18_1                      (0x2UL<<EPWM_HXB4_1_MUX18_Pos)                   /*!< 0x00000020 */
#define EPWM_HXB4_1_MUX19_Pos                    (6U)
#define EPWM_HXB4_1_MUX19_Msk                    (0x3UL<<EPWM_HXB4_1_MUX19_Pos)                   /*!< 0x000000C0 */
#define EPWM_HXB4_1_MUX19                        EPWM_HXB4_1_MUX19_Msk                            /*!< eallow, HXBLOCK */
#define EPWM_HXB4_1_MUX19_0                      (0x1UL<<EPWM_HXB4_1_MUX19_Pos)                   /*!< 0x00000040 */
#define EPWM_HXB4_1_MUX19_1                      (0x2UL<<EPWM_HXB4_1_MUX19_Pos)                   /*!< 0x00000080 */
#define EPWM_HXB4_1_MUX20_Pos                    (8U)
#define EPWM_HXB4_1_MUX20_Msk                    (0x3UL<<EPWM_HXB4_1_MUX20_Pos)                   /*!< 0x00000300 */
#define EPWM_HXB4_1_MUX20                        EPWM_HXB4_1_MUX20_Msk                            /*!< eallow, HXBLOCK */
#define EPWM_HXB4_1_MUX20_0                      (0x1UL<<EPWM_HXB4_1_MUX20_Pos)                   /*!< 0x00000100 */
#define EPWM_HXB4_1_MUX20_1                      (0x2UL<<EPWM_HXB4_1_MUX20_Pos)                   /*!< 0x00000200 */
#define EPWM_HXB4_1_MUX21_Pos                    (10U)
#define EPWM_HXB4_1_MUX21_Msk                    (0x3UL<<EPWM_HXB4_1_MUX21_Pos)                   /*!< 0x00000C00 */
#define EPWM_HXB4_1_MUX21                        EPWM_HXB4_1_MUX21_Msk                            /*!< eallow, HXBLOCK */
#define EPWM_HXB4_1_MUX21_0                      (0x1UL<<EPWM_HXB4_1_MUX21_Pos)                   /*!< 0x00000400 */
#define EPWM_HXB4_1_MUX21_1                      (0x2UL<<EPWM_HXB4_1_MUX21_Pos)                   /*!< 0x00000800 */
#define EPWM_HXB4_1_MUX22_Pos                    (12U)
#define EPWM_HXB4_1_MUX22_Msk                    (0x3UL<<EPWM_HXB4_1_MUX22_Pos)                   /*!< 0x00003000 */
#define EPWM_HXB4_1_MUX22                        EPWM_HXB4_1_MUX22_Msk                            /*!< eallow, HXBLOCK */
#define EPWM_HXB4_1_MUX22_0                      (0x1UL<<EPWM_HXB4_1_MUX22_Pos)                   /*!< 0x00001000 */
#define EPWM_HXB4_1_MUX22_1                      (0x2UL<<EPWM_HXB4_1_MUX22_Pos)                   /*!< 0x00002000 */
#define EPWM_HXB4_1_MUX23_Pos                    (14U)
#define EPWM_HXB4_1_MUX23_Msk                    (0x3UL<<EPWM_HXB4_1_MUX23_Pos)                   /*!< 0x0000C000 */
#define EPWM_HXB4_1_MUX23                        EPWM_HXB4_1_MUX23_Msk                            /*!< eallow, HXBLOCK */
#define EPWM_HXB4_1_MUX23_0                      (0x1UL<<EPWM_HXB4_1_MUX23_Pos)                   /*!< 0x00004000 */
#define EPWM_HXB4_1_MUX23_1                      (0x2UL<<EPWM_HXB4_1_MUX23_Pos)                   /*!< 0x00008000 */
#define EPWM_HXB4_1_MUX24_Pos                    (16U)
#define EPWM_HXB4_1_MUX24_Msk                    (0x3UL<<EPWM_HXB4_1_MUX24_Pos)                   /*!< 0x00030000 */
#define EPWM_HXB4_1_MUX24                        EPWM_HXB4_1_MUX24_Msk                            /*!< eallow, HXBLOCK */
#define EPWM_HXB4_1_MUX24_0                      (0x1UL<<EPWM_HXB4_1_MUX24_Pos)                   /*!< 0x00010000 */
#define EPWM_HXB4_1_MUX24_1                      (0x2UL<<EPWM_HXB4_1_MUX24_Pos)                   /*!< 0x00020000 */
#define EPWM_HXB4_1_MUX25_Pos                    (18U)
#define EPWM_HXB4_1_MUX25_Msk                    (0x3UL<<EPWM_HXB4_1_MUX25_Pos)                   /*!< 0x000C0000 */
#define EPWM_HXB4_1_MUX25                        EPWM_HXB4_1_MUX25_Msk                            /*!< eallow, HXBLOCK */
#define EPWM_HXB4_1_MUX25_0                      (0x1UL<<EPWM_HXB4_1_MUX25_Pos)                   /*!< 0x00040000 */
#define EPWM_HXB4_1_MUX25_1                      (0x2UL<<EPWM_HXB4_1_MUX25_Pos)                   /*!< 0x00080000 */
#define EPWM_HXB4_1_MUX26_Pos                    (20U)
#define EPWM_HXB4_1_MUX26_Msk                    (0x3UL<<EPWM_HXB4_1_MUX26_Pos)                   /*!< 0x00300000 */
#define EPWM_HXB4_1_MUX26                        EPWM_HXB4_1_MUX26_Msk                            /*!< eallow, HXBLOCK */
#define EPWM_HXB4_1_MUX26_0                      (0x1UL<<EPWM_HXB4_1_MUX26_Pos)                   /*!< 0x00100000 */
#define EPWM_HXB4_1_MUX26_1                      (0x2UL<<EPWM_HXB4_1_MUX26_Pos)                   /*!< 0x00200000 */
#define EPWM_HXB4_1_MUX27_Pos                    (22U)
#define EPWM_HXB4_1_MUX27_Msk                    (0x3UL<<EPWM_HXB4_1_MUX27_Pos)                   /*!< 0x00C00000 */
#define EPWM_HXB4_1_MUX27                        EPWM_HXB4_1_MUX27_Msk                            /*!< eallow, HXBLOCK */
#define EPWM_HXB4_1_MUX27_0                      (0x1UL<<EPWM_HXB4_1_MUX27_Pos)                   /*!< 0x00400000 */
#define EPWM_HXB4_1_MUX27_1                      (0x2UL<<EPWM_HXB4_1_MUX27_Pos)                   /*!< 0x00800000 */
#define EPWM_HXB4_1_MUX28_Pos                    (24U)
#define EPWM_HXB4_1_MUX28_Msk                    (0x3UL<<EPWM_HXB4_1_MUX28_Pos)                   /*!< 0x03000000 */
#define EPWM_HXB4_1_MUX28                        EPWM_HXB4_1_MUX28_Msk                            /*!< eallow, HXBLOCK */
#define EPWM_HXB4_1_MUX28_0                      (0x1UL<<EPWM_HXB4_1_MUX28_Pos)                   /*!< 0x01000000 */
#define EPWM_HXB4_1_MUX28_1                      (0x2UL<<EPWM_HXB4_1_MUX28_Pos)                   /*!< 0x02000000 */
#define EPWM_HXB4_1_MUX29_Pos                    (26U)
#define EPWM_HXB4_1_MUX29_Msk                    (0x3UL<<EPWM_HXB4_1_MUX29_Pos)                   /*!< 0x0C000000 */
#define EPWM_HXB4_1_MUX29                        EPWM_HXB4_1_MUX29_Msk                            /*!< eallow, HXBLOCK */
#define EPWM_HXB4_1_MUX29_0                      (0x1UL<<EPWM_HXB4_1_MUX29_Pos)                   /*!< 0x04000000 */
#define EPWM_HXB4_1_MUX29_1                      (0x2UL<<EPWM_HXB4_1_MUX29_Pos)                   /*!< 0x08000000 */
#define EPWM_HXB4_1_MUX30_Pos                    (28U)
#define EPWM_HXB4_1_MUX30_Msk                    (0x3UL<<EPWM_HXB4_1_MUX30_Pos)                   /*!< 0x30000000 */
#define EPWM_HXB4_1_MUX30                        EPWM_HXB4_1_MUX30_Msk                            /*!< eallow, HXBLOCK */
#define EPWM_HXB4_1_MUX30_0                      (0x1UL<<EPWM_HXB4_1_MUX30_Pos)                   /*!< 0x10000000 */
#define EPWM_HXB4_1_MUX30_1                      (0x2UL<<EPWM_HXB4_1_MUX30_Pos)                   /*!< 0x20000000 */
#define EPWM_HXB4_1_MUX31_Pos                    (30U)
#define EPWM_HXB4_1_MUX31_Msk                    (0x3UL<<EPWM_HXB4_1_MUX31_Pos)                   /*!< 0xC0000000 */
#define EPWM_HXB4_1_MUX31                        EPWM_HXB4_1_MUX31_Msk                            /*!< eallow, HXBLOCK */
#define EPWM_HXB4_1_MUX31_0                      (0x1UL<<EPWM_HXB4_1_MUX31_Pos)                   /*!< 0x40000000 */
#define EPWM_HXB4_1_MUX31_1                      (0x2UL<<EPWM_HXB4_1_MUX31_Pos)                   /*!< 0x80000000 */

/********************************* Bit definition for EPWM_HXB5_0 register *****************************************/
#define EPWM_HXB5_0_MUX0_Pos                     (0U)
#define EPWM_HXB5_0_MUX0_Msk                     (0x3UL<<EPWM_HXB5_0_MUX0_Pos)                    /*!< 0x00000003 */
#define EPWM_HXB5_0_MUX0                         EPWM_HXB5_0_MUX0_Msk                             /*!< eallow, HXBLOCK */
#define EPWM_HXB5_0_MUX0_0                       (0x1UL<<EPWM_HXB5_0_MUX0_Pos)                    /*!< 0x00000001 */
#define EPWM_HXB5_0_MUX0_1                       (0x2UL<<EPWM_HXB5_0_MUX0_Pos)                    /*!< 0x00000002 */
#define EPWM_HXB5_0_MUX1_Pos                     (2U)
#define EPWM_HXB5_0_MUX1_Msk                     (0x3UL<<EPWM_HXB5_0_MUX1_Pos)                    /*!< 0x0000000C */
#define EPWM_HXB5_0_MUX1                         EPWM_HXB5_0_MUX1_Msk                             /*!< eallow, HXBLOCK */
#define EPWM_HXB5_0_MUX1_0                       (0x1UL<<EPWM_HXB5_0_MUX1_Pos)                    /*!< 0x00000004 */
#define EPWM_HXB5_0_MUX1_1                       (0x2UL<<EPWM_HXB5_0_MUX1_Pos)                    /*!< 0x00000008 */
#define EPWM_HXB5_0_MUX2_Pos                     (4U)
#define EPWM_HXB5_0_MUX2_Msk                     (0x3UL<<EPWM_HXB5_0_MUX2_Pos)                    /*!< 0x00000030 */
#define EPWM_HXB5_0_MUX2                         EPWM_HXB5_0_MUX2_Msk                             /*!< eallow, HXBLOCK */
#define EPWM_HXB5_0_MUX2_0                       (0x1UL<<EPWM_HXB5_0_MUX2_Pos)                    /*!< 0x00000010 */
#define EPWM_HXB5_0_MUX2_1                       (0x2UL<<EPWM_HXB5_0_MUX2_Pos)                    /*!< 0x00000020 */
#define EPWM_HXB5_0_MUX3_Pos                     (6U)
#define EPWM_HXB5_0_MUX3_Msk                     (0x3UL<<EPWM_HXB5_0_MUX3_Pos)                    /*!< 0x000000C0 */
#define EPWM_HXB5_0_MUX3                         EPWM_HXB5_0_MUX3_Msk                             /*!< eallow, HXBLOCK */
#define EPWM_HXB5_0_MUX3_0                       (0x1UL<<EPWM_HXB5_0_MUX3_Pos)                    /*!< 0x00000040 */
#define EPWM_HXB5_0_MUX3_1                       (0x2UL<<EPWM_HXB5_0_MUX3_Pos)                    /*!< 0x00000080 */
#define EPWM_HXB5_0_MUX4_Pos                     (8U)
#define EPWM_HXB5_0_MUX4_Msk                     (0x3UL<<EPWM_HXB5_0_MUX4_Pos)                    /*!< 0x00000300 */
#define EPWM_HXB5_0_MUX4                         EPWM_HXB5_0_MUX4_Msk                             /*!< eallow, HXBLOCK */
#define EPWM_HXB5_0_MUX4_0                       (0x1UL<<EPWM_HXB5_0_MUX4_Pos)                    /*!< 0x00000100 */
#define EPWM_HXB5_0_MUX4_1                       (0x2UL<<EPWM_HXB5_0_MUX4_Pos)                    /*!< 0x00000200 */
#define EPWM_HXB5_0_MUX5_Pos                     (10U)
#define EPWM_HXB5_0_MUX5_Msk                     (0x3UL<<EPWM_HXB5_0_MUX5_Pos)                    /*!< 0x00000C00 */
#define EPWM_HXB5_0_MUX5                         EPWM_HXB5_0_MUX5_Msk                             /*!< eallow, HXBLOCK */
#define EPWM_HXB5_0_MUX5_0                       (0x1UL<<EPWM_HXB5_0_MUX5_Pos)                    /*!< 0x00000400 */
#define EPWM_HXB5_0_MUX5_1                       (0x2UL<<EPWM_HXB5_0_MUX5_Pos)                    /*!< 0x00000800 */
#define EPWM_HXB5_0_MUX6_Pos                     (12U)
#define EPWM_HXB5_0_MUX6_Msk                     (0x3UL<<EPWM_HXB5_0_MUX6_Pos)                    /*!< 0x00003000 */
#define EPWM_HXB5_0_MUX6                         EPWM_HXB5_0_MUX6_Msk                             /*!< eallow, HXBLOCK */
#define EPWM_HXB5_0_MUX6_0                       (0x1UL<<EPWM_HXB5_0_MUX6_Pos)                    /*!< 0x00001000 */
#define EPWM_HXB5_0_MUX6_1                       (0x2UL<<EPWM_HXB5_0_MUX6_Pos)                    /*!< 0x00002000 */
#define EPWM_HXB5_0_MUX7_Pos                     (14U)
#define EPWM_HXB5_0_MUX7_Msk                     (0x3UL<<EPWM_HXB5_0_MUX7_Pos)                    /*!< 0x0000C000 */
#define EPWM_HXB5_0_MUX7                         EPWM_HXB5_0_MUX7_Msk                             /*!< eallow, HXBLOCK */
#define EPWM_HXB5_0_MUX7_0                       (0x1UL<<EPWM_HXB5_0_MUX7_Pos)                    /*!< 0x00004000 */
#define EPWM_HXB5_0_MUX7_1                       (0x2UL<<EPWM_HXB5_0_MUX7_Pos)                    /*!< 0x00008000 */
#define EPWM_HXB5_0_MUX8_Pos                     (16U)
#define EPWM_HXB5_0_MUX8_Msk                     (0x3UL<<EPWM_HXB5_0_MUX8_Pos)                    /*!< 0x00030000 */
#define EPWM_HXB5_0_MUX8                         EPWM_HXB5_0_MUX8_Msk                             /*!< eallow, HXBLOCK */
#define EPWM_HXB5_0_MUX8_0                       (0x1UL<<EPWM_HXB5_0_MUX8_Pos)                    /*!< 0x00010000 */
#define EPWM_HXB5_0_MUX8_1                       (0x2UL<<EPWM_HXB5_0_MUX8_Pos)                    /*!< 0x00020000 */
#define EPWM_HXB5_0_MUX9_Pos                     (18U)
#define EPWM_HXB5_0_MUX9_Msk                     (0x3UL<<EPWM_HXB5_0_MUX9_Pos)                    /*!< 0x000C0000 */
#define EPWM_HXB5_0_MUX9                         EPWM_HXB5_0_MUX9_Msk                             /*!< eallow, HXBLOCK */
#define EPWM_HXB5_0_MUX9_0                       (0x1UL<<EPWM_HXB5_0_MUX9_Pos)                    /*!< 0x00040000 */
#define EPWM_HXB5_0_MUX9_1                       (0x2UL<<EPWM_HXB5_0_MUX9_Pos)                    /*!< 0x00080000 */
#define EPWM_HXB5_0_MUX10_Pos                    (20U)
#define EPWM_HXB5_0_MUX10_Msk                    (0x3UL<<EPWM_HXB5_0_MUX10_Pos)                   /*!< 0x00300000 */
#define EPWM_HXB5_0_MUX10                        EPWM_HXB5_0_MUX10_Msk                            /*!< eallow, HXBLOCK */
#define EPWM_HXB5_0_MUX10_0                      (0x1UL<<EPWM_HXB5_0_MUX10_Pos)                   /*!< 0x00100000 */
#define EPWM_HXB5_0_MUX10_1                      (0x2UL<<EPWM_HXB5_0_MUX10_Pos)                   /*!< 0x00200000 */
#define EPWM_HXB5_0_MUX11_Pos                    (22U)
#define EPWM_HXB5_0_MUX11_Msk                    (0x3UL<<EPWM_HXB5_0_MUX11_Pos)                   /*!< 0x00C00000 */
#define EPWM_HXB5_0_MUX11                        EPWM_HXB5_0_MUX11_Msk                            /*!< eallow, HXBLOCK */
#define EPWM_HXB5_0_MUX11_0                      (0x1UL<<EPWM_HXB5_0_MUX11_Pos)                   /*!< 0x00400000 */
#define EPWM_HXB5_0_MUX11_1                      (0x2UL<<EPWM_HXB5_0_MUX11_Pos)                   /*!< 0x00800000 */
#define EPWM_HXB5_0_MUX12_Pos                    (24U)
#define EPWM_HXB5_0_MUX12_Msk                    (0x3UL<<EPWM_HXB5_0_MUX12_Pos)                   /*!< 0x03000000 */
#define EPWM_HXB5_0_MUX12                        EPWM_HXB5_0_MUX12_Msk                            /*!< eallow, HXBLOCK */
#define EPWM_HXB5_0_MUX12_0                      (0x1UL<<EPWM_HXB5_0_MUX12_Pos)                   /*!< 0x01000000 */
#define EPWM_HXB5_0_MUX12_1                      (0x2UL<<EPWM_HXB5_0_MUX12_Pos)                   /*!< 0x02000000 */
#define EPWM_HXB5_0_MUX13_Pos                    (26U)
#define EPWM_HXB5_0_MUX13_Msk                    (0x3UL<<EPWM_HXB5_0_MUX13_Pos)                   /*!< 0x0C000000 */
#define EPWM_HXB5_0_MUX13                        EPWM_HXB5_0_MUX13_Msk                            /*!< eallow, HXBLOCK */
#define EPWM_HXB5_0_MUX13_0                      (0x1UL<<EPWM_HXB5_0_MUX13_Pos)                   /*!< 0x04000000 */
#define EPWM_HXB5_0_MUX13_1                      (0x2UL<<EPWM_HXB5_0_MUX13_Pos)                   /*!< 0x08000000 */
#define EPWM_HXB5_0_MUX14_Pos                    (28U)
#define EPWM_HXB5_0_MUX14_Msk                    (0x3UL<<EPWM_HXB5_0_MUX14_Pos)                   /*!< 0x30000000 */
#define EPWM_HXB5_0_MUX14                        EPWM_HXB5_0_MUX14_Msk                            /*!< eallow, HXBLOCK */
#define EPWM_HXB5_0_MUX14_0                      (0x1UL<<EPWM_HXB5_0_MUX14_Pos)                   /*!< 0x10000000 */
#define EPWM_HXB5_0_MUX14_1                      (0x2UL<<EPWM_HXB5_0_MUX14_Pos)                   /*!< 0x20000000 */
#define EPWM_HXB5_0_MUX15_Pos                    (30U)
#define EPWM_HXB5_0_MUX15_Msk                    (0x3UL<<EPWM_HXB5_0_MUX15_Pos)                   /*!< 0xC0000000 */
#define EPWM_HXB5_0_MUX15                        EPWM_HXB5_0_MUX15_Msk                            /*!< eallow, HXBLOCK */
#define EPWM_HXB5_0_MUX15_0                      (0x1UL<<EPWM_HXB5_0_MUX15_Pos)                   /*!< 0x40000000 */
#define EPWM_HXB5_0_MUX15_1                      (0x2UL<<EPWM_HXB5_0_MUX15_Pos)                   /*!< 0x80000000 */

/********************************* Bit definition for EPWM_HXB5_1 register *****************************************/
#define EPWM_HXB5_1_MUX16_Pos                    (0U)
#define EPWM_HXB5_1_MUX16_Msk                    (0x3UL<<EPWM_HXB5_1_MUX16_Pos)                   /*!< 0x00000003 */
#define EPWM_HXB5_1_MUX16                        EPWM_HXB5_1_MUX16_Msk                            /*!< eallow, HXBLOCK */
#define EPWM_HXB5_1_MUX16_0                      (0x1UL<<EPWM_HXB5_1_MUX16_Pos)                   /*!< 0x00000001 */
#define EPWM_HXB5_1_MUX16_1                      (0x2UL<<EPWM_HXB5_1_MUX16_Pos)                   /*!< 0x00000002 */
#define EPWM_HXB5_1_MUX17_Pos                    (2U)
#define EPWM_HXB5_1_MUX17_Msk                    (0x3UL<<EPWM_HXB5_1_MUX17_Pos)                   /*!< 0x0000000C */
#define EPWM_HXB5_1_MUX17                        EPWM_HXB5_1_MUX17_Msk                            /*!< eallow, HXBLOCK */
#define EPWM_HXB5_1_MUX17_0                      (0x1UL<<EPWM_HXB5_1_MUX17_Pos)                   /*!< 0x00000004 */
#define EPWM_HXB5_1_MUX17_1                      (0x2UL<<EPWM_HXB5_1_MUX17_Pos)                   /*!< 0x00000008 */
#define EPWM_HXB5_1_MUX18_Pos                    (4U)
#define EPWM_HXB5_1_MUX18_Msk                    (0x3UL<<EPWM_HXB5_1_MUX18_Pos)                   /*!< 0x00000030 */
#define EPWM_HXB5_1_MUX18                        EPWM_HXB5_1_MUX18_Msk                            /*!< eallow, HXBLOCK */
#define EPWM_HXB5_1_MUX18_0                      (0x1UL<<EPWM_HXB5_1_MUX18_Pos)                   /*!< 0x00000010 */
#define EPWM_HXB5_1_MUX18_1                      (0x2UL<<EPWM_HXB5_1_MUX18_Pos)                   /*!< 0x00000020 */
#define EPWM_HXB5_1_MUX19_Pos                    (6U)
#define EPWM_HXB5_1_MUX19_Msk                    (0x3UL<<EPWM_HXB5_1_MUX19_Pos)                   /*!< 0x000000C0 */
#define EPWM_HXB5_1_MUX19                        EPWM_HXB5_1_MUX19_Msk                            /*!< eallow, HXBLOCK */
#define EPWM_HXB5_1_MUX19_0                      (0x1UL<<EPWM_HXB5_1_MUX19_Pos)                   /*!< 0x00000040 */
#define EPWM_HXB5_1_MUX19_1                      (0x2UL<<EPWM_HXB5_1_MUX19_Pos)                   /*!< 0x00000080 */
#define EPWM_HXB5_1_MUX20_Pos                    (8U)
#define EPWM_HXB5_1_MUX20_Msk                    (0x3UL<<EPWM_HXB5_1_MUX20_Pos)                   /*!< 0x00000300 */
#define EPWM_HXB5_1_MUX20                        EPWM_HXB5_1_MUX20_Msk                            /*!< eallow, HXBLOCK */
#define EPWM_HXB5_1_MUX20_0                      (0x1UL<<EPWM_HXB5_1_MUX20_Pos)                   /*!< 0x00000100 */
#define EPWM_HXB5_1_MUX20_1                      (0x2UL<<EPWM_HXB5_1_MUX20_Pos)                   /*!< 0x00000200 */
#define EPWM_HXB5_1_MUX21_Pos                    (10U)
#define EPWM_HXB5_1_MUX21_Msk                    (0x3UL<<EPWM_HXB5_1_MUX21_Pos)                   /*!< 0x00000C00 */
#define EPWM_HXB5_1_MUX21                        EPWM_HXB5_1_MUX21_Msk                            /*!< eallow, HXBLOCK */
#define EPWM_HXB5_1_MUX21_0                      (0x1UL<<EPWM_HXB5_1_MUX21_Pos)                   /*!< 0x00000400 */
#define EPWM_HXB5_1_MUX21_1                      (0x2UL<<EPWM_HXB5_1_MUX21_Pos)                   /*!< 0x00000800 */
#define EPWM_HXB5_1_MUX22_Pos                    (12U)
#define EPWM_HXB5_1_MUX22_Msk                    (0x3UL<<EPWM_HXB5_1_MUX22_Pos)                   /*!< 0x00003000 */
#define EPWM_HXB5_1_MUX22                        EPWM_HXB5_1_MUX22_Msk                            /*!< eallow, HXBLOCK */
#define EPWM_HXB5_1_MUX22_0                      (0x1UL<<EPWM_HXB5_1_MUX22_Pos)                   /*!< 0x00001000 */
#define EPWM_HXB5_1_MUX22_1                      (0x2UL<<EPWM_HXB5_1_MUX22_Pos)                   /*!< 0x00002000 */
#define EPWM_HXB5_1_MUX23_Pos                    (14U)
#define EPWM_HXB5_1_MUX23_Msk                    (0x3UL<<EPWM_HXB5_1_MUX23_Pos)                   /*!< 0x0000C000 */
#define EPWM_HXB5_1_MUX23                        EPWM_HXB5_1_MUX23_Msk                            /*!< eallow, HXBLOCK */
#define EPWM_HXB5_1_MUX23_0                      (0x1UL<<EPWM_HXB5_1_MUX23_Pos)                   /*!< 0x00004000 */
#define EPWM_HXB5_1_MUX23_1                      (0x2UL<<EPWM_HXB5_1_MUX23_Pos)                   /*!< 0x00008000 */
#define EPWM_HXB5_1_MUX24_Pos                    (16U)
#define EPWM_HXB5_1_MUX24_Msk                    (0x3UL<<EPWM_HXB5_1_MUX24_Pos)                   /*!< 0x00030000 */
#define EPWM_HXB5_1_MUX24                        EPWM_HXB5_1_MUX24_Msk                            /*!< eallow, HXBLOCK */
#define EPWM_HXB5_1_MUX24_0                      (0x1UL<<EPWM_HXB5_1_MUX24_Pos)                   /*!< 0x00010000 */
#define EPWM_HXB5_1_MUX24_1                      (0x2UL<<EPWM_HXB5_1_MUX24_Pos)                   /*!< 0x00020000 */
#define EPWM_HXB5_1_MUX25_Pos                    (18U)
#define EPWM_HXB5_1_MUX25_Msk                    (0x3UL<<EPWM_HXB5_1_MUX25_Pos)                   /*!< 0x000C0000 */
#define EPWM_HXB5_1_MUX25                        EPWM_HXB5_1_MUX25_Msk                            /*!< eallow, HXBLOCK */
#define EPWM_HXB5_1_MUX25_0                      (0x1UL<<EPWM_HXB5_1_MUX25_Pos)                   /*!< 0x00040000 */
#define EPWM_HXB5_1_MUX25_1                      (0x2UL<<EPWM_HXB5_1_MUX25_Pos)                   /*!< 0x00080000 */
#define EPWM_HXB5_1_MUX26_Pos                    (20U)
#define EPWM_HXB5_1_MUX26_Msk                    (0x3UL<<EPWM_HXB5_1_MUX26_Pos)                   /*!< 0x00300000 */
#define EPWM_HXB5_1_MUX26                        EPWM_HXB5_1_MUX26_Msk                            /*!< eallow, HXBLOCK */
#define EPWM_HXB5_1_MUX26_0                      (0x1UL<<EPWM_HXB5_1_MUX26_Pos)                   /*!< 0x00100000 */
#define EPWM_HXB5_1_MUX26_1                      (0x2UL<<EPWM_HXB5_1_MUX26_Pos)                   /*!< 0x00200000 */
#define EPWM_HXB5_1_MUX27_Pos                    (22U)
#define EPWM_HXB5_1_MUX27_Msk                    (0x3UL<<EPWM_HXB5_1_MUX27_Pos)                   /*!< 0x00C00000 */
#define EPWM_HXB5_1_MUX27                        EPWM_HXB5_1_MUX27_Msk                            /*!< eallow, HXBLOCK */
#define EPWM_HXB5_1_MUX27_0                      (0x1UL<<EPWM_HXB5_1_MUX27_Pos)                   /*!< 0x00400000 */
#define EPWM_HXB5_1_MUX27_1                      (0x2UL<<EPWM_HXB5_1_MUX27_Pos)                   /*!< 0x00800000 */
#define EPWM_HXB5_1_MUX28_Pos                    (24U)
#define EPWM_HXB5_1_MUX28_Msk                    (0x3UL<<EPWM_HXB5_1_MUX28_Pos)                   /*!< 0x03000000 */
#define EPWM_HXB5_1_MUX28                        EPWM_HXB5_1_MUX28_Msk                            /*!< eallow, HXBLOCK */
#define EPWM_HXB5_1_MUX28_0                      (0x1UL<<EPWM_HXB5_1_MUX28_Pos)                   /*!< 0x01000000 */
#define EPWM_HXB5_1_MUX28_1                      (0x2UL<<EPWM_HXB5_1_MUX28_Pos)                   /*!< 0x02000000 */
#define EPWM_HXB5_1_MUX29_Pos                    (26U)
#define EPWM_HXB5_1_MUX29_Msk                    (0x3UL<<EPWM_HXB5_1_MUX29_Pos)                   /*!< 0x0C000000 */
#define EPWM_HXB5_1_MUX29                        EPWM_HXB5_1_MUX29_Msk                            /*!< eallow, HXBLOCK */
#define EPWM_HXB5_1_MUX29_0                      (0x1UL<<EPWM_HXB5_1_MUX29_Pos)                   /*!< 0x04000000 */
#define EPWM_HXB5_1_MUX29_1                      (0x2UL<<EPWM_HXB5_1_MUX29_Pos)                   /*!< 0x08000000 */
#define EPWM_HXB5_1_MUX30_Pos                    (28U)
#define EPWM_HXB5_1_MUX30_Msk                    (0x3UL<<EPWM_HXB5_1_MUX30_Pos)                   /*!< 0x30000000 */
#define EPWM_HXB5_1_MUX30                        EPWM_HXB5_1_MUX30_Msk                            /*!< eallow, HXBLOCK */
#define EPWM_HXB5_1_MUX30_0                      (0x1UL<<EPWM_HXB5_1_MUX30_Pos)                   /*!< 0x10000000 */
#define EPWM_HXB5_1_MUX30_1                      (0x2UL<<EPWM_HXB5_1_MUX30_Pos)                   /*!< 0x20000000 */
#define EPWM_HXB5_1_MUX31_Pos                    (30U)
#define EPWM_HXB5_1_MUX31_Msk                    (0x3UL<<EPWM_HXB5_1_MUX31_Pos)                   /*!< 0xC0000000 */
#define EPWM_HXB5_1_MUX31                        EPWM_HXB5_1_MUX31_Msk                            /*!< eallow, HXBLOCK */
#define EPWM_HXB5_1_MUX31_0                      (0x1UL<<EPWM_HXB5_1_MUX31_Pos)                   /*!< 0x40000000 */
#define EPWM_HXB5_1_MUX31_1                      (0x2UL<<EPWM_HXB5_1_MUX31_Pos)                   /*!< 0x80000000 */

/********************************* Bit definition for EPWM_HXB7_0 register *****************************************/
#define EPWM_HXB7_0_MUX0_Pos                     (0U)
#define EPWM_HXB7_0_MUX0_Msk                     (0x3UL<<EPWM_HXB7_0_MUX0_Pos)                    /*!< 0x00000003 */
#define EPWM_HXB7_0_MUX0                         EPWM_HXB7_0_MUX0_Msk                             /*!< eallow, HXBLOCK */
#define EPWM_HXB7_0_MUX0_0                       (0x1UL<<EPWM_HXB7_0_MUX0_Pos)                    /*!< 0x00000001 */
#define EPWM_HXB7_0_MUX0_1                       (0x2UL<<EPWM_HXB7_0_MUX0_Pos)                    /*!< 0x00000002 */
#define EPWM_HXB7_0_MUX1_Pos                     (2U)
#define EPWM_HXB7_0_MUX1_Msk                     (0x3UL<<EPWM_HXB7_0_MUX1_Pos)                    /*!< 0x0000000C */
#define EPWM_HXB7_0_MUX1                         EPWM_HXB7_0_MUX1_Msk                             /*!< eallow, HXBLOCK */
#define EPWM_HXB7_0_MUX1_0                       (0x1UL<<EPWM_HXB7_0_MUX1_Pos)                    /*!< 0x00000004 */
#define EPWM_HXB7_0_MUX1_1                       (0x2UL<<EPWM_HXB7_0_MUX1_Pos)                    /*!< 0x00000008 */
#define EPWM_HXB7_0_MUX2_Pos                     (4U)
#define EPWM_HXB7_0_MUX2_Msk                     (0x3UL<<EPWM_HXB7_0_MUX2_Pos)                    /*!< 0x00000030 */
#define EPWM_HXB7_0_MUX2                         EPWM_HXB7_0_MUX2_Msk                             /*!< eallow, HXBLOCK */
#define EPWM_HXB7_0_MUX2_0                       (0x1UL<<EPWM_HXB7_0_MUX2_Pos)                    /*!< 0x00000010 */
#define EPWM_HXB7_0_MUX2_1                       (0x2UL<<EPWM_HXB7_0_MUX2_Pos)                    /*!< 0x00000020 */
#define EPWM_HXB7_0_MUX3_Pos                     (6U)
#define EPWM_HXB7_0_MUX3_Msk                     (0x3UL<<EPWM_HXB7_0_MUX3_Pos)                    /*!< 0x000000C0 */
#define EPWM_HXB7_0_MUX3                         EPWM_HXB7_0_MUX3_Msk                             /*!< eallow, HXBLOCK */
#define EPWM_HXB7_0_MUX3_0                       (0x1UL<<EPWM_HXB7_0_MUX3_Pos)                    /*!< 0x00000040 */
#define EPWM_HXB7_0_MUX3_1                       (0x2UL<<EPWM_HXB7_0_MUX3_Pos)                    /*!< 0x00000080 */
#define EPWM_HXB7_0_MUX4_Pos                     (8U)
#define EPWM_HXB7_0_MUX4_Msk                     (0x3UL<<EPWM_HXB7_0_MUX4_Pos)                    /*!< 0x00000300 */
#define EPWM_HXB7_0_MUX4                         EPWM_HXB7_0_MUX4_Msk                             /*!< eallow, HXBLOCK */
#define EPWM_HXB7_0_MUX4_0                       (0x1UL<<EPWM_HXB7_0_MUX4_Pos)                    /*!< 0x00000100 */
#define EPWM_HXB7_0_MUX4_1                       (0x2UL<<EPWM_HXB7_0_MUX4_Pos)                    /*!< 0x00000200 */
#define EPWM_HXB7_0_MUX5_Pos                     (10U)
#define EPWM_HXB7_0_MUX5_Msk                     (0x3UL<<EPWM_HXB7_0_MUX5_Pos)                    /*!< 0x00000C00 */
#define EPWM_HXB7_0_MUX5                         EPWM_HXB7_0_MUX5_Msk                             /*!< eallow, HXBLOCK */
#define EPWM_HXB7_0_MUX5_0                       (0x1UL<<EPWM_HXB7_0_MUX5_Pos)                    /*!< 0x00000400 */
#define EPWM_HXB7_0_MUX5_1                       (0x2UL<<EPWM_HXB7_0_MUX5_Pos)                    /*!< 0x00000800 */
#define EPWM_HXB7_0_MUX6_Pos                     (12U)
#define EPWM_HXB7_0_MUX6_Msk                     (0x3UL<<EPWM_HXB7_0_MUX6_Pos)                    /*!< 0x00003000 */
#define EPWM_HXB7_0_MUX6                         EPWM_HXB7_0_MUX6_Msk                             /*!< eallow, HXBLOCK */
#define EPWM_HXB7_0_MUX6_0                       (0x1UL<<EPWM_HXB7_0_MUX6_Pos)                    /*!< 0x00001000 */
#define EPWM_HXB7_0_MUX6_1                       (0x2UL<<EPWM_HXB7_0_MUX6_Pos)                    /*!< 0x00002000 */
#define EPWM_HXB7_0_MUX7_Pos                     (14U)
#define EPWM_HXB7_0_MUX7_Msk                     (0x3UL<<EPWM_HXB7_0_MUX7_Pos)                    /*!< 0x0000C000 */
#define EPWM_HXB7_0_MUX7                         EPWM_HXB7_0_MUX7_Msk                             /*!< eallow, HXBLOCK */
#define EPWM_HXB7_0_MUX7_0                       (0x1UL<<EPWM_HXB7_0_MUX7_Pos)                    /*!< 0x00004000 */
#define EPWM_HXB7_0_MUX7_1                       (0x2UL<<EPWM_HXB7_0_MUX7_Pos)                    /*!< 0x00008000 */
#define EPWM_HXB7_0_MUX8_Pos                     (16U)
#define EPWM_HXB7_0_MUX8_Msk                     (0x3UL<<EPWM_HXB7_0_MUX8_Pos)                    /*!< 0x00030000 */
#define EPWM_HXB7_0_MUX8                         EPWM_HXB7_0_MUX8_Msk                             /*!< eallow, HXBLOCK */
#define EPWM_HXB7_0_MUX8_0                       (0x1UL<<EPWM_HXB7_0_MUX8_Pos)                    /*!< 0x00010000 */
#define EPWM_HXB7_0_MUX8_1                       (0x2UL<<EPWM_HXB7_0_MUX8_Pos)                    /*!< 0x00020000 */
#define EPWM_HXB7_0_MUX9_Pos                     (18U)
#define EPWM_HXB7_0_MUX9_Msk                     (0x3UL<<EPWM_HXB7_0_MUX9_Pos)                    /*!< 0x000C0000 */
#define EPWM_HXB7_0_MUX9                         EPWM_HXB7_0_MUX9_Msk                             /*!< eallow, HXBLOCK */
#define EPWM_HXB7_0_MUX9_0                       (0x1UL<<EPWM_HXB7_0_MUX9_Pos)                    /*!< 0x00040000 */
#define EPWM_HXB7_0_MUX9_1                       (0x2UL<<EPWM_HXB7_0_MUX9_Pos)                    /*!< 0x00080000 */
#define EPWM_HXB7_0_MUX10_Pos                    (20U)
#define EPWM_HXB7_0_MUX10_Msk                    (0x3UL<<EPWM_HXB7_0_MUX10_Pos)                   /*!< 0x00300000 */
#define EPWM_HXB7_0_MUX10                        EPWM_HXB7_0_MUX10_Msk                            /*!< eallow, HXBLOCK */
#define EPWM_HXB7_0_MUX10_0                      (0x1UL<<EPWM_HXB7_0_MUX10_Pos)                   /*!< 0x00100000 */
#define EPWM_HXB7_0_MUX10_1                      (0x2UL<<EPWM_HXB7_0_MUX10_Pos)                   /*!< 0x00200000 */
#define EPWM_HXB7_0_MUX11_Pos                    (22U)
#define EPWM_HXB7_0_MUX11_Msk                    (0x3UL<<EPWM_HXB7_0_MUX11_Pos)                   /*!< 0x00C00000 */
#define EPWM_HXB7_0_MUX11                        EPWM_HXB7_0_MUX11_Msk                            /*!< eallow, HXBLOCK */
#define EPWM_HXB7_0_MUX11_0                      (0x1UL<<EPWM_HXB7_0_MUX11_Pos)                   /*!< 0x00400000 */
#define EPWM_HXB7_0_MUX11_1                      (0x2UL<<EPWM_HXB7_0_MUX11_Pos)                   /*!< 0x00800000 */
#define EPWM_HXB7_0_MUX12_Pos                    (24U)
#define EPWM_HXB7_0_MUX12_Msk                    (0x3UL<<EPWM_HXB7_0_MUX12_Pos)                   /*!< 0x03000000 */
#define EPWM_HXB7_0_MUX12                        EPWM_HXB7_0_MUX12_Msk                            /*!< eallow, HXBLOCK */
#define EPWM_HXB7_0_MUX12_0                      (0x1UL<<EPWM_HXB7_0_MUX12_Pos)                   /*!< 0x01000000 */
#define EPWM_HXB7_0_MUX12_1                      (0x2UL<<EPWM_HXB7_0_MUX12_Pos)                   /*!< 0x02000000 */
#define EPWM_HXB7_0_MUX13_Pos                    (26U)
#define EPWM_HXB7_0_MUX13_Msk                    (0x3UL<<EPWM_HXB7_0_MUX13_Pos)                   /*!< 0x0C000000 */
#define EPWM_HXB7_0_MUX13                        EPWM_HXB7_0_MUX13_Msk                            /*!< eallow, HXBLOCK */
#define EPWM_HXB7_0_MUX13_0                      (0x1UL<<EPWM_HXB7_0_MUX13_Pos)                   /*!< 0x04000000 */
#define EPWM_HXB7_0_MUX13_1                      (0x2UL<<EPWM_HXB7_0_MUX13_Pos)                   /*!< 0x08000000 */
#define EPWM_HXB7_0_MUX14_Pos                    (28U)
#define EPWM_HXB7_0_MUX14_Msk                    (0x3UL<<EPWM_HXB7_0_MUX14_Pos)                   /*!< 0x30000000 */
#define EPWM_HXB7_0_MUX14                        EPWM_HXB7_0_MUX14_Msk                            /*!< eallow, HXBLOCK */
#define EPWM_HXB7_0_MUX14_0                      (0x1UL<<EPWM_HXB7_0_MUX14_Pos)                   /*!< 0x10000000 */
#define EPWM_HXB7_0_MUX14_1                      (0x2UL<<EPWM_HXB7_0_MUX14_Pos)                   /*!< 0x20000000 */
#define EPWM_HXB7_0_MUX15_Pos                    (30U)
#define EPWM_HXB7_0_MUX15_Msk                    (0x3UL<<EPWM_HXB7_0_MUX15_Pos)                   /*!< 0xC0000000 */
#define EPWM_HXB7_0_MUX15                        EPWM_HXB7_0_MUX15_Msk                            /*!< eallow, HXBLOCK */
#define EPWM_HXB7_0_MUX15_0                      (0x1UL<<EPWM_HXB7_0_MUX15_Pos)                   /*!< 0x40000000 */
#define EPWM_HXB7_0_MUX15_1                      (0x2UL<<EPWM_HXB7_0_MUX15_Pos)                   /*!< 0x80000000 */

/********************************* Bit definition for EPWM_HXB7_1 register *****************************************/
#define EPWM_HXB7_1_MUX16_Pos                    (0U)
#define EPWM_HXB7_1_MUX16_Msk                    (0x3UL<<EPWM_HXB7_1_MUX16_Pos)                   /*!< 0x00000003 */
#define EPWM_HXB7_1_MUX16                        EPWM_HXB7_1_MUX16_Msk                            /*!< eallow, HXBLOCK */
#define EPWM_HXB7_1_MUX16_0                      (0x1UL<<EPWM_HXB7_1_MUX16_Pos)                   /*!< 0x00000001 */
#define EPWM_HXB7_1_MUX16_1                      (0x2UL<<EPWM_HXB7_1_MUX16_Pos)                   /*!< 0x00000002 */
#define EPWM_HXB7_1_MUX17_Pos                    (2U)
#define EPWM_HXB7_1_MUX17_Msk                    (0x3UL<<EPWM_HXB7_1_MUX17_Pos)                   /*!< 0x0000000C */
#define EPWM_HXB7_1_MUX17                        EPWM_HXB7_1_MUX17_Msk                            /*!< eallow, HXBLOCK */
#define EPWM_HXB7_1_MUX17_0                      (0x1UL<<EPWM_HXB7_1_MUX17_Pos)                   /*!< 0x00000004 */
#define EPWM_HXB7_1_MUX17_1                      (0x2UL<<EPWM_HXB7_1_MUX17_Pos)                   /*!< 0x00000008 */
#define EPWM_HXB7_1_MUX18_Pos                    (4U)
#define EPWM_HXB7_1_MUX18_Msk                    (0x3UL<<EPWM_HXB7_1_MUX18_Pos)                   /*!< 0x00000030 */
#define EPWM_HXB7_1_MUX18                        EPWM_HXB7_1_MUX18_Msk                            /*!< eallow, HXBLOCK */
#define EPWM_HXB7_1_MUX18_0                      (0x1UL<<EPWM_HXB7_1_MUX18_Pos)                   /*!< 0x00000010 */
#define EPWM_HXB7_1_MUX18_1                      (0x2UL<<EPWM_HXB7_1_MUX18_Pos)                   /*!< 0x00000020 */
#define EPWM_HXB7_1_MUX19_Pos                    (6U)
#define EPWM_HXB7_1_MUX19_Msk                    (0x3UL<<EPWM_HXB7_1_MUX19_Pos)                   /*!< 0x000000C0 */
#define EPWM_HXB7_1_MUX19                        EPWM_HXB7_1_MUX19_Msk                            /*!< eallow, HXBLOCK */
#define EPWM_HXB7_1_MUX19_0                      (0x1UL<<EPWM_HXB7_1_MUX19_Pos)                   /*!< 0x00000040 */
#define EPWM_HXB7_1_MUX19_1                      (0x2UL<<EPWM_HXB7_1_MUX19_Pos)                   /*!< 0x00000080 */
#define EPWM_HXB7_1_MUX20_Pos                    (8U)
#define EPWM_HXB7_1_MUX20_Msk                    (0x3UL<<EPWM_HXB7_1_MUX20_Pos)                   /*!< 0x00000300 */
#define EPWM_HXB7_1_MUX20                        EPWM_HXB7_1_MUX20_Msk                            /*!< eallow, HXBLOCK */
#define EPWM_HXB7_1_MUX20_0                      (0x1UL<<EPWM_HXB7_1_MUX20_Pos)                   /*!< 0x00000100 */
#define EPWM_HXB7_1_MUX20_1                      (0x2UL<<EPWM_HXB7_1_MUX20_Pos)                   /*!< 0x00000200 */
#define EPWM_HXB7_1_MUX21_Pos                    (10U)
#define EPWM_HXB7_1_MUX21_Msk                    (0x3UL<<EPWM_HXB7_1_MUX21_Pos)                   /*!< 0x00000C00 */
#define EPWM_HXB7_1_MUX21                        EPWM_HXB7_1_MUX21_Msk                            /*!< eallow, HXBLOCK */
#define EPWM_HXB7_1_MUX21_0                      (0x1UL<<EPWM_HXB7_1_MUX21_Pos)                   /*!< 0x00000400 */
#define EPWM_HXB7_1_MUX21_1                      (0x2UL<<EPWM_HXB7_1_MUX21_Pos)                   /*!< 0x00000800 */
#define EPWM_HXB7_1_MUX22_Pos                    (12U)
#define EPWM_HXB7_1_MUX22_Msk                    (0x3UL<<EPWM_HXB7_1_MUX22_Pos)                   /*!< 0x00003000 */
#define EPWM_HXB7_1_MUX22                        EPWM_HXB7_1_MUX22_Msk                            /*!< eallow, HXBLOCK */
#define EPWM_HXB7_1_MUX22_0                      (0x1UL<<EPWM_HXB7_1_MUX22_Pos)                   /*!< 0x00001000 */
#define EPWM_HXB7_1_MUX22_1                      (0x2UL<<EPWM_HXB7_1_MUX22_Pos)                   /*!< 0x00002000 */
#define EPWM_HXB7_1_MUX23_Pos                    (14U)
#define EPWM_HXB7_1_MUX23_Msk                    (0x3UL<<EPWM_HXB7_1_MUX23_Pos)                   /*!< 0x0000C000 */
#define EPWM_HXB7_1_MUX23                        EPWM_HXB7_1_MUX23_Msk                            /*!< eallow, HXBLOCK */
#define EPWM_HXB7_1_MUX23_0                      (0x1UL<<EPWM_HXB7_1_MUX23_Pos)                   /*!< 0x00004000 */
#define EPWM_HXB7_1_MUX23_1                      (0x2UL<<EPWM_HXB7_1_MUX23_Pos)                   /*!< 0x00008000 */
#define EPWM_HXB7_1_MUX24_Pos                    (16U)
#define EPWM_HXB7_1_MUX24_Msk                    (0x3UL<<EPWM_HXB7_1_MUX24_Pos)                   /*!< 0x00030000 */
#define EPWM_HXB7_1_MUX24                        EPWM_HXB7_1_MUX24_Msk                            /*!< eallow, HXBLOCK */
#define EPWM_HXB7_1_MUX24_0                      (0x1UL<<EPWM_HXB7_1_MUX24_Pos)                   /*!< 0x00010000 */
#define EPWM_HXB7_1_MUX24_1                      (0x2UL<<EPWM_HXB7_1_MUX24_Pos)                   /*!< 0x00020000 */
#define EPWM_HXB7_1_MUX25_Pos                    (18U)
#define EPWM_HXB7_1_MUX25_Msk                    (0x3UL<<EPWM_HXB7_1_MUX25_Pos)                   /*!< 0x000C0000 */
#define EPWM_HXB7_1_MUX25                        EPWM_HXB7_1_MUX25_Msk                            /*!< eallow, HXBLOCK */
#define EPWM_HXB7_1_MUX25_0                      (0x1UL<<EPWM_HXB7_1_MUX25_Pos)                   /*!< 0x00040000 */
#define EPWM_HXB7_1_MUX25_1                      (0x2UL<<EPWM_HXB7_1_MUX25_Pos)                   /*!< 0x00080000 */
#define EPWM_HXB7_1_MUX26_Pos                    (20U)
#define EPWM_HXB7_1_MUX26_Msk                    (0x3UL<<EPWM_HXB7_1_MUX26_Pos)                   /*!< 0x00300000 */
#define EPWM_HXB7_1_MUX26                        EPWM_HXB7_1_MUX26_Msk                            /*!< eallow, HXBLOCK */
#define EPWM_HXB7_1_MUX26_0                      (0x1UL<<EPWM_HXB7_1_MUX26_Pos)                   /*!< 0x00100000 */
#define EPWM_HXB7_1_MUX26_1                      (0x2UL<<EPWM_HXB7_1_MUX26_Pos)                   /*!< 0x00200000 */
#define EPWM_HXB7_1_MUX27_Pos                    (22U)
#define EPWM_HXB7_1_MUX27_Msk                    (0x3UL<<EPWM_HXB7_1_MUX27_Pos)                   /*!< 0x00C00000 */
#define EPWM_HXB7_1_MUX27                        EPWM_HXB7_1_MUX27_Msk                            /*!< eallow, HXBLOCK */
#define EPWM_HXB7_1_MUX27_0                      (0x1UL<<EPWM_HXB7_1_MUX27_Pos)                   /*!< 0x00400000 */
#define EPWM_HXB7_1_MUX27_1                      (0x2UL<<EPWM_HXB7_1_MUX27_Pos)                   /*!< 0x00800000 */
#define EPWM_HXB7_1_MUX28_Pos                    (24U)
#define EPWM_HXB7_1_MUX28_Msk                    (0x3UL<<EPWM_HXB7_1_MUX28_Pos)                   /*!< 0x03000000 */
#define EPWM_HXB7_1_MUX28                        EPWM_HXB7_1_MUX28_Msk                            /*!< eallow, HXBLOCK */
#define EPWM_HXB7_1_MUX28_0                      (0x1UL<<EPWM_HXB7_1_MUX28_Pos)                   /*!< 0x01000000 */
#define EPWM_HXB7_1_MUX28_1                      (0x2UL<<EPWM_HXB7_1_MUX28_Pos)                   /*!< 0x02000000 */
#define EPWM_HXB7_1_MUX29_Pos                    (26U)
#define EPWM_HXB7_1_MUX29_Msk                    (0x3UL<<EPWM_HXB7_1_MUX29_Pos)                   /*!< 0x0C000000 */
#define EPWM_HXB7_1_MUX29                        EPWM_HXB7_1_MUX29_Msk                            /*!< eallow, HXBLOCK */
#define EPWM_HXB7_1_MUX29_0                      (0x1UL<<EPWM_HXB7_1_MUX29_Pos)                   /*!< 0x04000000 */
#define EPWM_HXB7_1_MUX29_1                      (0x2UL<<EPWM_HXB7_1_MUX29_Pos)                   /*!< 0x08000000 */
#define EPWM_HXB7_1_MUX30_Pos                    (28U)
#define EPWM_HXB7_1_MUX30_Msk                    (0x3UL<<EPWM_HXB7_1_MUX30_Pos)                   /*!< 0x30000000 */
#define EPWM_HXB7_1_MUX30                        EPWM_HXB7_1_MUX30_Msk                            /*!< eallow, HXBLOCK */
#define EPWM_HXB7_1_MUX30_0                      (0x1UL<<EPWM_HXB7_1_MUX30_Pos)                   /*!< 0x10000000 */
#define EPWM_HXB7_1_MUX30_1                      (0x2UL<<EPWM_HXB7_1_MUX30_Pos)                   /*!< 0x20000000 */
#define EPWM_HXB7_1_MUX31_Pos                    (30U)
#define EPWM_HXB7_1_MUX31_Msk                    (0x3UL<<EPWM_HXB7_1_MUX31_Pos)                   /*!< 0xC0000000 */
#define EPWM_HXB7_1_MUX31                        EPWM_HXB7_1_MUX31_Msk                            /*!< eallow, HXBLOCK */
#define EPWM_HXB7_1_MUX31_0                      (0x1UL<<EPWM_HXB7_1_MUX31_Pos)                   /*!< 0x40000000 */
#define EPWM_HXB7_1_MUX31_1                      (0x2UL<<EPWM_HXB7_1_MUX31_Pos)                   /*!< 0x80000000 */

/********************************* Bit definition for EPWM_HXB8_0 register *****************************************/
#define EPWM_HXB8_0_MUX0_Pos                     (0U)
#define EPWM_HXB8_0_MUX0_Msk                     (0x3UL<<EPWM_HXB8_0_MUX0_Pos)                    /*!< 0x00000003 */
#define EPWM_HXB8_0_MUX0                         EPWM_HXB8_0_MUX0_Msk                             /*!< eallow, HXBLOCK */
#define EPWM_HXB8_0_MUX0_0                       (0x1UL<<EPWM_HXB8_0_MUX0_Pos)                    /*!< 0x00000001 */
#define EPWM_HXB8_0_MUX0_1                       (0x2UL<<EPWM_HXB8_0_MUX0_Pos)                    /*!< 0x00000002 */
#define EPWM_HXB8_0_MUX1_Pos                     (2U)
#define EPWM_HXB8_0_MUX1_Msk                     (0x3UL<<EPWM_HXB8_0_MUX1_Pos)                    /*!< 0x0000000C */
#define EPWM_HXB8_0_MUX1                         EPWM_HXB8_0_MUX1_Msk                             /*!< eallow, HXBLOCK */
#define EPWM_HXB8_0_MUX1_0                       (0x1UL<<EPWM_HXB8_0_MUX1_Pos)                    /*!< 0x00000004 */
#define EPWM_HXB8_0_MUX1_1                       (0x2UL<<EPWM_HXB8_0_MUX1_Pos)                    /*!< 0x00000008 */
#define EPWM_HXB8_0_MUX2_Pos                     (4U)
#define EPWM_HXB8_0_MUX2_Msk                     (0x3UL<<EPWM_HXB8_0_MUX2_Pos)                    /*!< 0x00000030 */
#define EPWM_HXB8_0_MUX2                         EPWM_HXB8_0_MUX2_Msk                             /*!< eallow, HXBLOCK */
#define EPWM_HXB8_0_MUX2_0                       (0x1UL<<EPWM_HXB8_0_MUX2_Pos)                    /*!< 0x00000010 */
#define EPWM_HXB8_0_MUX2_1                       (0x2UL<<EPWM_HXB8_0_MUX2_Pos)                    /*!< 0x00000020 */
#define EPWM_HXB8_0_MUX3_Pos                     (6U)
#define EPWM_HXB8_0_MUX3_Msk                     (0x3UL<<EPWM_HXB8_0_MUX3_Pos)                    /*!< 0x000000C0 */
#define EPWM_HXB8_0_MUX3                         EPWM_HXB8_0_MUX3_Msk                             /*!< eallow, HXBLOCK */
#define EPWM_HXB8_0_MUX3_0                       (0x1UL<<EPWM_HXB8_0_MUX3_Pos)                    /*!< 0x00000040 */
#define EPWM_HXB8_0_MUX3_1                       (0x2UL<<EPWM_HXB8_0_MUX3_Pos)                    /*!< 0x00000080 */
#define EPWM_HXB8_0_MUX4_Pos                     (8U)
#define EPWM_HXB8_0_MUX4_Msk                     (0x3UL<<EPWM_HXB8_0_MUX4_Pos)                    /*!< 0x00000300 */
#define EPWM_HXB8_0_MUX4                         EPWM_HXB8_0_MUX4_Msk                             /*!< eallow, HXBLOCK */
#define EPWM_HXB8_0_MUX4_0                       (0x1UL<<EPWM_HXB8_0_MUX4_Pos)                    /*!< 0x00000100 */
#define EPWM_HXB8_0_MUX4_1                       (0x2UL<<EPWM_HXB8_0_MUX4_Pos)                    /*!< 0x00000200 */
#define EPWM_HXB8_0_MUX5_Pos                     (10U)
#define EPWM_HXB8_0_MUX5_Msk                     (0x3UL<<EPWM_HXB8_0_MUX5_Pos)                    /*!< 0x00000C00 */
#define EPWM_HXB8_0_MUX5                         EPWM_HXB8_0_MUX5_Msk                             /*!< eallow, HXBLOCK */
#define EPWM_HXB8_0_MUX5_0                       (0x1UL<<EPWM_HXB8_0_MUX5_Pos)                    /*!< 0x00000400 */
#define EPWM_HXB8_0_MUX5_1                       (0x2UL<<EPWM_HXB8_0_MUX5_Pos)                    /*!< 0x00000800 */
#define EPWM_HXB8_0_MUX6_Pos                     (12U)
#define EPWM_HXB8_0_MUX6_Msk                     (0x3UL<<EPWM_HXB8_0_MUX6_Pos)                    /*!< 0x00003000 */
#define EPWM_HXB8_0_MUX6                         EPWM_HXB8_0_MUX6_Msk                             /*!< eallow, HXBLOCK */
#define EPWM_HXB8_0_MUX6_0                       (0x1UL<<EPWM_HXB8_0_MUX6_Pos)                    /*!< 0x00001000 */
#define EPWM_HXB8_0_MUX6_1                       (0x2UL<<EPWM_HXB8_0_MUX6_Pos)                    /*!< 0x00002000 */
#define EPWM_HXB8_0_MUX7_Pos                     (14U)
#define EPWM_HXB8_0_MUX7_Msk                     (0x3UL<<EPWM_HXB8_0_MUX7_Pos)                    /*!< 0x0000C000 */
#define EPWM_HXB8_0_MUX7                         EPWM_HXB8_0_MUX7_Msk                             /*!< eallow, HXBLOCK */
#define EPWM_HXB8_0_MUX7_0                       (0x1UL<<EPWM_HXB8_0_MUX7_Pos)                    /*!< 0x00004000 */
#define EPWM_HXB8_0_MUX7_1                       (0x2UL<<EPWM_HXB8_0_MUX7_Pos)                    /*!< 0x00008000 */
#define EPWM_HXB8_0_MUX8_Pos                     (16U)
#define EPWM_HXB8_0_MUX8_Msk                     (0x3UL<<EPWM_HXB8_0_MUX8_Pos)                    /*!< 0x00030000 */
#define EPWM_HXB8_0_MUX8                         EPWM_HXB8_0_MUX8_Msk                             /*!< eallow, HXBLOCK */
#define EPWM_HXB8_0_MUX8_0                       (0x1UL<<EPWM_HXB8_0_MUX8_Pos)                    /*!< 0x00010000 */
#define EPWM_HXB8_0_MUX8_1                       (0x2UL<<EPWM_HXB8_0_MUX8_Pos)                    /*!< 0x00020000 */
#define EPWM_HXB8_0_MUX9_Pos                     (18U)
#define EPWM_HXB8_0_MUX9_Msk                     (0x3UL<<EPWM_HXB8_0_MUX9_Pos)                    /*!< 0x000C0000 */
#define EPWM_HXB8_0_MUX9                         EPWM_HXB8_0_MUX9_Msk                             /*!< eallow, HXBLOCK */
#define EPWM_HXB8_0_MUX9_0                       (0x1UL<<EPWM_HXB8_0_MUX9_Pos)                    /*!< 0x00040000 */
#define EPWM_HXB8_0_MUX9_1                       (0x2UL<<EPWM_HXB8_0_MUX9_Pos)                    /*!< 0x00080000 */
#define EPWM_HXB8_0_MUX10_Pos                    (20U)
#define EPWM_HXB8_0_MUX10_Msk                    (0x3UL<<EPWM_HXB8_0_MUX10_Pos)                   /*!< 0x00300000 */
#define EPWM_HXB8_0_MUX10                        EPWM_HXB8_0_MUX10_Msk                            /*!< eallow, HXBLOCK */
#define EPWM_HXB8_0_MUX10_0                      (0x1UL<<EPWM_HXB8_0_MUX10_Pos)                   /*!< 0x00100000 */
#define EPWM_HXB8_0_MUX10_1                      (0x2UL<<EPWM_HXB8_0_MUX10_Pos)                   /*!< 0x00200000 */
#define EPWM_HXB8_0_MUX11_Pos                    (22U)
#define EPWM_HXB8_0_MUX11_Msk                    (0x3UL<<EPWM_HXB8_0_MUX11_Pos)                   /*!< 0x00C00000 */
#define EPWM_HXB8_0_MUX11                        EPWM_HXB8_0_MUX11_Msk                            /*!< eallow, HXBLOCK */
#define EPWM_HXB8_0_MUX11_0                      (0x1UL<<EPWM_HXB8_0_MUX11_Pos)                   /*!< 0x00400000 */
#define EPWM_HXB8_0_MUX11_1                      (0x2UL<<EPWM_HXB8_0_MUX11_Pos)                   /*!< 0x00800000 */
#define EPWM_HXB8_0_MUX12_Pos                    (24U)
#define EPWM_HXB8_0_MUX12_Msk                    (0x3UL<<EPWM_HXB8_0_MUX12_Pos)                   /*!< 0x03000000 */
#define EPWM_HXB8_0_MUX12                        EPWM_HXB8_0_MUX12_Msk                            /*!< eallow, HXBLOCK */
#define EPWM_HXB8_0_MUX12_0                      (0x1UL<<EPWM_HXB8_0_MUX12_Pos)                   /*!< 0x01000000 */
#define EPWM_HXB8_0_MUX12_1                      (0x2UL<<EPWM_HXB8_0_MUX12_Pos)                   /*!< 0x02000000 */
#define EPWM_HXB8_0_MUX13_Pos                    (26U)
#define EPWM_HXB8_0_MUX13_Msk                    (0x3UL<<EPWM_HXB8_0_MUX13_Pos)                   /*!< 0x0C000000 */
#define EPWM_HXB8_0_MUX13                        EPWM_HXB8_0_MUX13_Msk                            /*!< eallow, HXBLOCK */
#define EPWM_HXB8_0_MUX13_0                      (0x1UL<<EPWM_HXB8_0_MUX13_Pos)                   /*!< 0x04000000 */
#define EPWM_HXB8_0_MUX13_1                      (0x2UL<<EPWM_HXB8_0_MUX13_Pos)                   /*!< 0x08000000 */
#define EPWM_HXB8_0_MUX14_Pos                    (28U)
#define EPWM_HXB8_0_MUX14_Msk                    (0x3UL<<EPWM_HXB8_0_MUX14_Pos)                   /*!< 0x30000000 */
#define EPWM_HXB8_0_MUX14                        EPWM_HXB8_0_MUX14_Msk                            /*!< eallow, HXBLOCK */
#define EPWM_HXB8_0_MUX14_0                      (0x1UL<<EPWM_HXB8_0_MUX14_Pos)                   /*!< 0x10000000 */
#define EPWM_HXB8_0_MUX14_1                      (0x2UL<<EPWM_HXB8_0_MUX14_Pos)                   /*!< 0x20000000 */
#define EPWM_HXB8_0_MUX15_Pos                    (30U)
#define EPWM_HXB8_0_MUX15_Msk                    (0x3UL<<EPWM_HXB8_0_MUX15_Pos)                   /*!< 0xC0000000 */
#define EPWM_HXB8_0_MUX15                        EPWM_HXB8_0_MUX15_Msk                            /*!< eallow, HXBLOCK */
#define EPWM_HXB8_0_MUX15_0                      (0x1UL<<EPWM_HXB8_0_MUX15_Pos)                   /*!< 0x40000000 */
#define EPWM_HXB8_0_MUX15_1                      (0x2UL<<EPWM_HXB8_0_MUX15_Pos)                   /*!< 0x80000000 */

/********************************* Bit definition for EPWM_HXB8_1 register *****************************************/
#define EPWM_HXB8_1_MUX16_Pos                    (0U)
#define EPWM_HXB8_1_MUX16_Msk                    (0x3UL<<EPWM_HXB8_1_MUX16_Pos)                   /*!< 0x00000003 */
#define EPWM_HXB8_1_MUX16                        EPWM_HXB8_1_MUX16_Msk                            /*!< eallow, HXBLOCK */
#define EPWM_HXB8_1_MUX16_0                      (0x1UL<<EPWM_HXB8_1_MUX16_Pos)                   /*!< 0x00000001 */
#define EPWM_HXB8_1_MUX16_1                      (0x2UL<<EPWM_HXB8_1_MUX16_Pos)                   /*!< 0x00000002 */
#define EPWM_HXB8_1_MUX17_Pos                    (2U)
#define EPWM_HXB8_1_MUX17_Msk                    (0x3UL<<EPWM_HXB8_1_MUX17_Pos)                   /*!< 0x0000000C */
#define EPWM_HXB8_1_MUX17                        EPWM_HXB8_1_MUX17_Msk                            /*!< eallow, HXBLOCK */
#define EPWM_HXB8_1_MUX17_0                      (0x1UL<<EPWM_HXB8_1_MUX17_Pos)                   /*!< 0x00000004 */
#define EPWM_HXB8_1_MUX17_1                      (0x2UL<<EPWM_HXB8_1_MUX17_Pos)                   /*!< 0x00000008 */
#define EPWM_HXB8_1_MUX18_Pos                    (4U)
#define EPWM_HXB8_1_MUX18_Msk                    (0x3UL<<EPWM_HXB8_1_MUX18_Pos)                   /*!< 0x00000030 */
#define EPWM_HXB8_1_MUX18                        EPWM_HXB8_1_MUX18_Msk                            /*!< eallow, HXBLOCK */
#define EPWM_HXB8_1_MUX18_0                      (0x1UL<<EPWM_HXB8_1_MUX18_Pos)                   /*!< 0x00000010 */
#define EPWM_HXB8_1_MUX18_1                      (0x2UL<<EPWM_HXB8_1_MUX18_Pos)                   /*!< 0x00000020 */
#define EPWM_HXB8_1_MUX19_Pos                    (6U)
#define EPWM_HXB8_1_MUX19_Msk                    (0x3UL<<EPWM_HXB8_1_MUX19_Pos)                   /*!< 0x000000C0 */
#define EPWM_HXB8_1_MUX19                        EPWM_HXB8_1_MUX19_Msk                            /*!< eallow, HXBLOCK */
#define EPWM_HXB8_1_MUX19_0                      (0x1UL<<EPWM_HXB8_1_MUX19_Pos)                   /*!< 0x00000040 */
#define EPWM_HXB8_1_MUX19_1                      (0x2UL<<EPWM_HXB8_1_MUX19_Pos)                   /*!< 0x00000080 */
#define EPWM_HXB8_1_MUX20_Pos                    (8U)
#define EPWM_HXB8_1_MUX20_Msk                    (0x3UL<<EPWM_HXB8_1_MUX20_Pos)                   /*!< 0x00000300 */
#define EPWM_HXB8_1_MUX20                        EPWM_HXB8_1_MUX20_Msk                            /*!< eallow, HXBLOCK */
#define EPWM_HXB8_1_MUX20_0                      (0x1UL<<EPWM_HXB8_1_MUX20_Pos)                   /*!< 0x00000100 */
#define EPWM_HXB8_1_MUX20_1                      (0x2UL<<EPWM_HXB8_1_MUX20_Pos)                   /*!< 0x00000200 */
#define EPWM_HXB8_1_MUX21_Pos                    (10U)
#define EPWM_HXB8_1_MUX21_Msk                    (0x3UL<<EPWM_HXB8_1_MUX21_Pos)                   /*!< 0x00000C00 */
#define EPWM_HXB8_1_MUX21                        EPWM_HXB8_1_MUX21_Msk                            /*!< eallow, HXBLOCK */
#define EPWM_HXB8_1_MUX21_0                      (0x1UL<<EPWM_HXB8_1_MUX21_Pos)                   /*!< 0x00000400 */
#define EPWM_HXB8_1_MUX21_1                      (0x2UL<<EPWM_HXB8_1_MUX21_Pos)                   /*!< 0x00000800 */
#define EPWM_HXB8_1_MUX22_Pos                    (12U)
#define EPWM_HXB8_1_MUX22_Msk                    (0x3UL<<EPWM_HXB8_1_MUX22_Pos)                   /*!< 0x00003000 */
#define EPWM_HXB8_1_MUX22                        EPWM_HXB8_1_MUX22_Msk                            /*!< eallow, HXBLOCK */
#define EPWM_HXB8_1_MUX22_0                      (0x1UL<<EPWM_HXB8_1_MUX22_Pos)                   /*!< 0x00001000 */
#define EPWM_HXB8_1_MUX22_1                      (0x2UL<<EPWM_HXB8_1_MUX22_Pos)                   /*!< 0x00002000 */
#define EPWM_HXB8_1_MUX23_Pos                    (14U)
#define EPWM_HXB8_1_MUX23_Msk                    (0x3UL<<EPWM_HXB8_1_MUX23_Pos)                   /*!< 0x0000C000 */
#define EPWM_HXB8_1_MUX23                        EPWM_HXB8_1_MUX23_Msk                            /*!< eallow, HXBLOCK */
#define EPWM_HXB8_1_MUX23_0                      (0x1UL<<EPWM_HXB8_1_MUX23_Pos)                   /*!< 0x00004000 */
#define EPWM_HXB8_1_MUX23_1                      (0x2UL<<EPWM_HXB8_1_MUX23_Pos)                   /*!< 0x00008000 */
#define EPWM_HXB8_1_MUX24_Pos                    (16U)
#define EPWM_HXB8_1_MUX24_Msk                    (0x3UL<<EPWM_HXB8_1_MUX24_Pos)                   /*!< 0x00030000 */
#define EPWM_HXB8_1_MUX24                        EPWM_HXB8_1_MUX24_Msk                            /*!< eallow, HXBLOCK */
#define EPWM_HXB8_1_MUX24_0                      (0x1UL<<EPWM_HXB8_1_MUX24_Pos)                   /*!< 0x00010000 */
#define EPWM_HXB8_1_MUX24_1                      (0x2UL<<EPWM_HXB8_1_MUX24_Pos)                   /*!< 0x00020000 */
#define EPWM_HXB8_1_MUX25_Pos                    (18U)
#define EPWM_HXB8_1_MUX25_Msk                    (0x3UL<<EPWM_HXB8_1_MUX25_Pos)                   /*!< 0x000C0000 */
#define EPWM_HXB8_1_MUX25                        EPWM_HXB8_1_MUX25_Msk                            /*!< eallow, HXBLOCK */
#define EPWM_HXB8_1_MUX25_0                      (0x1UL<<EPWM_HXB8_1_MUX25_Pos)                   /*!< 0x00040000 */
#define EPWM_HXB8_1_MUX25_1                      (0x2UL<<EPWM_HXB8_1_MUX25_Pos)                   /*!< 0x00080000 */
#define EPWM_HXB8_1_MUX26_Pos                    (20U)
#define EPWM_HXB8_1_MUX26_Msk                    (0x3UL<<EPWM_HXB8_1_MUX26_Pos)                   /*!< 0x00300000 */
#define EPWM_HXB8_1_MUX26                        EPWM_HXB8_1_MUX26_Msk                            /*!< eallow, HXBLOCK */
#define EPWM_HXB8_1_MUX26_0                      (0x1UL<<EPWM_HXB8_1_MUX26_Pos)                   /*!< 0x00100000 */
#define EPWM_HXB8_1_MUX26_1                      (0x2UL<<EPWM_HXB8_1_MUX26_Pos)                   /*!< 0x00200000 */
#define EPWM_HXB8_1_MUX27_Pos                    (22U)
#define EPWM_HXB8_1_MUX27_Msk                    (0x3UL<<EPWM_HXB8_1_MUX27_Pos)                   /*!< 0x00C00000 */
#define EPWM_HXB8_1_MUX27                        EPWM_HXB8_1_MUX27_Msk                            /*!< eallow, HXBLOCK */
#define EPWM_HXB8_1_MUX27_0                      (0x1UL<<EPWM_HXB8_1_MUX27_Pos)                   /*!< 0x00400000 */
#define EPWM_HXB8_1_MUX27_1                      (0x2UL<<EPWM_HXB8_1_MUX27_Pos)                   /*!< 0x00800000 */
#define EPWM_HXB8_1_MUX28_Pos                    (24U)
#define EPWM_HXB8_1_MUX28_Msk                    (0x3UL<<EPWM_HXB8_1_MUX28_Pos)                   /*!< 0x03000000 */
#define EPWM_HXB8_1_MUX28                        EPWM_HXB8_1_MUX28_Msk                            /*!< eallow, HXBLOCK */
#define EPWM_HXB8_1_MUX28_0                      (0x1UL<<EPWM_HXB8_1_MUX28_Pos)                   /*!< 0x01000000 */
#define EPWM_HXB8_1_MUX28_1                      (0x2UL<<EPWM_HXB8_1_MUX28_Pos)                   /*!< 0x02000000 */
#define EPWM_HXB8_1_MUX29_Pos                    (26U)
#define EPWM_HXB8_1_MUX29_Msk                    (0x3UL<<EPWM_HXB8_1_MUX29_Pos)                   /*!< 0x0C000000 */
#define EPWM_HXB8_1_MUX29                        EPWM_HXB8_1_MUX29_Msk                            /*!< eallow, HXBLOCK */
#define EPWM_HXB8_1_MUX29_0                      (0x1UL<<EPWM_HXB8_1_MUX29_Pos)                   /*!< 0x04000000 */
#define EPWM_HXB8_1_MUX29_1                      (0x2UL<<EPWM_HXB8_1_MUX29_Pos)                   /*!< 0x08000000 */
#define EPWM_HXB8_1_MUX30_Pos                    (28U)
#define EPWM_HXB8_1_MUX30_Msk                    (0x3UL<<EPWM_HXB8_1_MUX30_Pos)                   /*!< 0x30000000 */
#define EPWM_HXB8_1_MUX30                        EPWM_HXB8_1_MUX30_Msk                            /*!< eallow, HXBLOCK */
#define EPWM_HXB8_1_MUX30_0                      (0x1UL<<EPWM_HXB8_1_MUX30_Pos)                   /*!< 0x10000000 */
#define EPWM_HXB8_1_MUX30_1                      (0x2UL<<EPWM_HXB8_1_MUX30_Pos)                   /*!< 0x20000000 */
#define EPWM_HXB8_1_MUX31_Pos                    (30U)
#define EPWM_HXB8_1_MUX31_Msk                    (0x3UL<<EPWM_HXB8_1_MUX31_Pos)                   /*!< 0xC0000000 */
#define EPWM_HXB8_1_MUX31                        EPWM_HXB8_1_MUX31_Msk                            /*!< eallow, HXBLOCK */
#define EPWM_HXB8_1_MUX31_0                      (0x1UL<<EPWM_HXB8_1_MUX31_Pos)                   /*!< 0x40000000 */
#define EPWM_HXB8_1_MUX31_1                      (0x2UL<<EPWM_HXB8_1_MUX31_Pos)                   /*!< 0x80000000 */

/********************************* Bit definition for EPWM_HXB9_0 register *****************************************/
#define EPWM_HXB9_0_MUX0_Pos                     (0U)
#define EPWM_HXB9_0_MUX0_Msk                     (0x3UL<<EPWM_HXB9_0_MUX0_Pos)                    /*!< 0x00000003 */
#define EPWM_HXB9_0_MUX0                         EPWM_HXB9_0_MUX0_Msk                             /*!< eallow, HXBLOCK */
#define EPWM_HXB9_0_MUX0_0                       (0x1UL<<EPWM_HXB9_0_MUX0_Pos)                    /*!< 0x00000001 */
#define EPWM_HXB9_0_MUX0_1                       (0x2UL<<EPWM_HXB9_0_MUX0_Pos)                    /*!< 0x00000002 */
#define EPWM_HXB9_0_MUX1_Pos                     (2U)
#define EPWM_HXB9_0_MUX1_Msk                     (0x3UL<<EPWM_HXB9_0_MUX1_Pos)                    /*!< 0x0000000C */
#define EPWM_HXB9_0_MUX1                         EPWM_HXB9_0_MUX1_Msk                             /*!< eallow, HXBLOCK */
#define EPWM_HXB9_0_MUX1_0                       (0x1UL<<EPWM_HXB9_0_MUX1_Pos)                    /*!< 0x00000004 */
#define EPWM_HXB9_0_MUX1_1                       (0x2UL<<EPWM_HXB9_0_MUX1_Pos)                    /*!< 0x00000008 */
#define EPWM_HXB9_0_MUX2_Pos                     (4U)
#define EPWM_HXB9_0_MUX2_Msk                     (0x3UL<<EPWM_HXB9_0_MUX2_Pos)                    /*!< 0x00000030 */
#define EPWM_HXB9_0_MUX2                         EPWM_HXB9_0_MUX2_Msk                             /*!< eallow, HXBLOCK */
#define EPWM_HXB9_0_MUX2_0                       (0x1UL<<EPWM_HXB9_0_MUX2_Pos)                    /*!< 0x00000010 */
#define EPWM_HXB9_0_MUX2_1                       (0x2UL<<EPWM_HXB9_0_MUX2_Pos)                    /*!< 0x00000020 */
#define EPWM_HXB9_0_MUX3_Pos                     (6U)
#define EPWM_HXB9_0_MUX3_Msk                     (0x3UL<<EPWM_HXB9_0_MUX3_Pos)                    /*!< 0x000000C0 */
#define EPWM_HXB9_0_MUX3                         EPWM_HXB9_0_MUX3_Msk                             /*!< eallow, HXBLOCK */
#define EPWM_HXB9_0_MUX3_0                       (0x1UL<<EPWM_HXB9_0_MUX3_Pos)                    /*!< 0x00000040 */
#define EPWM_HXB9_0_MUX3_1                       (0x2UL<<EPWM_HXB9_0_MUX3_Pos)                    /*!< 0x00000080 */
#define EPWM_HXB9_0_MUX4_Pos                     (8U)
#define EPWM_HXB9_0_MUX4_Msk                     (0x3UL<<EPWM_HXB9_0_MUX4_Pos)                    /*!< 0x00000300 */
#define EPWM_HXB9_0_MUX4                         EPWM_HXB9_0_MUX4_Msk                             /*!< eallow, HXBLOCK */
#define EPWM_HXB9_0_MUX4_0                       (0x1UL<<EPWM_HXB9_0_MUX4_Pos)                    /*!< 0x00000100 */
#define EPWM_HXB9_0_MUX4_1                       (0x2UL<<EPWM_HXB9_0_MUX4_Pos)                    /*!< 0x00000200 */
#define EPWM_HXB9_0_MUX5_Pos                     (10U)
#define EPWM_HXB9_0_MUX5_Msk                     (0x3UL<<EPWM_HXB9_0_MUX5_Pos)                    /*!< 0x00000C00 */
#define EPWM_HXB9_0_MUX5                         EPWM_HXB9_0_MUX5_Msk                             /*!< eallow, HXBLOCK */
#define EPWM_HXB9_0_MUX5_0                       (0x1UL<<EPWM_HXB9_0_MUX5_Pos)                    /*!< 0x00000400 */
#define EPWM_HXB9_0_MUX5_1                       (0x2UL<<EPWM_HXB9_0_MUX5_Pos)                    /*!< 0x00000800 */
#define EPWM_HXB9_0_MUX6_Pos                     (12U)
#define EPWM_HXB9_0_MUX6_Msk                     (0x3UL<<EPWM_HXB9_0_MUX6_Pos)                    /*!< 0x00003000 */
#define EPWM_HXB9_0_MUX6                         EPWM_HXB9_0_MUX6_Msk                             /*!< eallow, HXBLOCK */
#define EPWM_HXB9_0_MUX6_0                       (0x1UL<<EPWM_HXB9_0_MUX6_Pos)                    /*!< 0x00001000 */
#define EPWM_HXB9_0_MUX6_1                       (0x2UL<<EPWM_HXB9_0_MUX6_Pos)                    /*!< 0x00002000 */
#define EPWM_HXB9_0_MUX7_Pos                     (14U)
#define EPWM_HXB9_0_MUX7_Msk                     (0x3UL<<EPWM_HXB9_0_MUX7_Pos)                    /*!< 0x0000C000 */
#define EPWM_HXB9_0_MUX7                         EPWM_HXB9_0_MUX7_Msk                             /*!< eallow, HXBLOCK */
#define EPWM_HXB9_0_MUX7_0                       (0x1UL<<EPWM_HXB9_0_MUX7_Pos)                    /*!< 0x00004000 */
#define EPWM_HXB9_0_MUX7_1                       (0x2UL<<EPWM_HXB9_0_MUX7_Pos)                    /*!< 0x00008000 */
#define EPWM_HXB9_0_MUX8_Pos                     (16U)
#define EPWM_HXB9_0_MUX8_Msk                     (0x3UL<<EPWM_HXB9_0_MUX8_Pos)                    /*!< 0x00030000 */
#define EPWM_HXB9_0_MUX8                         EPWM_HXB9_0_MUX8_Msk                             /*!< eallow, HXBLOCK */
#define EPWM_HXB9_0_MUX8_0                       (0x1UL<<EPWM_HXB9_0_MUX8_Pos)                    /*!< 0x00010000 */
#define EPWM_HXB9_0_MUX8_1                       (0x2UL<<EPWM_HXB9_0_MUX8_Pos)                    /*!< 0x00020000 */
#define EPWM_HXB9_0_MUX9_Pos                     (18U)
#define EPWM_HXB9_0_MUX9_Msk                     (0x3UL<<EPWM_HXB9_0_MUX9_Pos)                    /*!< 0x000C0000 */
#define EPWM_HXB9_0_MUX9                         EPWM_HXB9_0_MUX9_Msk                             /*!< eallow, HXBLOCK */
#define EPWM_HXB9_0_MUX9_0                       (0x1UL<<EPWM_HXB9_0_MUX9_Pos)                    /*!< 0x00040000 */
#define EPWM_HXB9_0_MUX9_1                       (0x2UL<<EPWM_HXB9_0_MUX9_Pos)                    /*!< 0x00080000 */
#define EPWM_HXB9_0_MUX10_Pos                    (20U)
#define EPWM_HXB9_0_MUX10_Msk                    (0x3UL<<EPWM_HXB9_0_MUX10_Pos)                   /*!< 0x00300000 */
#define EPWM_HXB9_0_MUX10                        EPWM_HXB9_0_MUX10_Msk                            /*!< eallow, HXBLOCK */
#define EPWM_HXB9_0_MUX10_0                      (0x1UL<<EPWM_HXB9_0_MUX10_Pos)                   /*!< 0x00100000 */
#define EPWM_HXB9_0_MUX10_1                      (0x2UL<<EPWM_HXB9_0_MUX10_Pos)                   /*!< 0x00200000 */
#define EPWM_HXB9_0_MUX11_Pos                    (22U)
#define EPWM_HXB9_0_MUX11_Msk                    (0x3UL<<EPWM_HXB9_0_MUX11_Pos)                   /*!< 0x00C00000 */
#define EPWM_HXB9_0_MUX11                        EPWM_HXB9_0_MUX11_Msk                            /*!< eallow, HXBLOCK */
#define EPWM_HXB9_0_MUX11_0                      (0x1UL<<EPWM_HXB9_0_MUX11_Pos)                   /*!< 0x00400000 */
#define EPWM_HXB9_0_MUX11_1                      (0x2UL<<EPWM_HXB9_0_MUX11_Pos)                   /*!< 0x00800000 */
#define EPWM_HXB9_0_MUX12_Pos                    (24U)
#define EPWM_HXB9_0_MUX12_Msk                    (0x3UL<<EPWM_HXB9_0_MUX12_Pos)                   /*!< 0x03000000 */
#define EPWM_HXB9_0_MUX12                        EPWM_HXB9_0_MUX12_Msk                            /*!< eallow, HXBLOCK */
#define EPWM_HXB9_0_MUX12_0                      (0x1UL<<EPWM_HXB9_0_MUX12_Pos)                   /*!< 0x01000000 */
#define EPWM_HXB9_0_MUX12_1                      (0x2UL<<EPWM_HXB9_0_MUX12_Pos)                   /*!< 0x02000000 */
#define EPWM_HXB9_0_MUX13_Pos                    (26U)
#define EPWM_HXB9_0_MUX13_Msk                    (0x3UL<<EPWM_HXB9_0_MUX13_Pos)                   /*!< 0x0C000000 */
#define EPWM_HXB9_0_MUX13                        EPWM_HXB9_0_MUX13_Msk                            /*!< eallow, HXBLOCK */
#define EPWM_HXB9_0_MUX13_0                      (0x1UL<<EPWM_HXB9_0_MUX13_Pos)                   /*!< 0x04000000 */
#define EPWM_HXB9_0_MUX13_1                      (0x2UL<<EPWM_HXB9_0_MUX13_Pos)                   /*!< 0x08000000 */
#define EPWM_HXB9_0_MUX14_Pos                    (28U)
#define EPWM_HXB9_0_MUX14_Msk                    (0x3UL<<EPWM_HXB9_0_MUX14_Pos)                   /*!< 0x30000000 */
#define EPWM_HXB9_0_MUX14                        EPWM_HXB9_0_MUX14_Msk                            /*!< eallow, HXBLOCK */
#define EPWM_HXB9_0_MUX14_0                      (0x1UL<<EPWM_HXB9_0_MUX14_Pos)                   /*!< 0x10000000 */
#define EPWM_HXB9_0_MUX14_1                      (0x2UL<<EPWM_HXB9_0_MUX14_Pos)                   /*!< 0x20000000 */
#define EPWM_HXB9_0_MUX15_Pos                    (30U)
#define EPWM_HXB9_0_MUX15_Msk                    (0x3UL<<EPWM_HXB9_0_MUX15_Pos)                   /*!< 0xC0000000 */
#define EPWM_HXB9_0_MUX15                        EPWM_HXB9_0_MUX15_Msk                            /*!< eallow, HXBLOCK */
#define EPWM_HXB9_0_MUX15_0                      (0x1UL<<EPWM_HXB9_0_MUX15_Pos)                   /*!< 0x40000000 */
#define EPWM_HXB9_0_MUX15_1                      (0x2UL<<EPWM_HXB9_0_MUX15_Pos)                   /*!< 0x80000000 */

/********************************* Bit definition for EPWM_HXB9_1 register *****************************************/
#define EPWM_HXB9_1_MUX16_Pos                    (0U)
#define EPWM_HXB9_1_MUX16_Msk                    (0x3UL<<EPWM_HXB9_1_MUX16_Pos)                   /*!< 0x00000003 */
#define EPWM_HXB9_1_MUX16                        EPWM_HXB9_1_MUX16_Msk                            /*!< eallow, HXBLOCK */
#define EPWM_HXB9_1_MUX16_0                      (0x1UL<<EPWM_HXB9_1_MUX16_Pos)                   /*!< 0x00000001 */
#define EPWM_HXB9_1_MUX16_1                      (0x2UL<<EPWM_HXB9_1_MUX16_Pos)                   /*!< 0x00000002 */
#define EPWM_HXB9_1_MUX17_Pos                    (2U)
#define EPWM_HXB9_1_MUX17_Msk                    (0x3UL<<EPWM_HXB9_1_MUX17_Pos)                   /*!< 0x0000000C */
#define EPWM_HXB9_1_MUX17                        EPWM_HXB9_1_MUX17_Msk                            /*!< eallow, HXBLOCK */
#define EPWM_HXB9_1_MUX17_0                      (0x1UL<<EPWM_HXB9_1_MUX17_Pos)                   /*!< 0x00000004 */
#define EPWM_HXB9_1_MUX17_1                      (0x2UL<<EPWM_HXB9_1_MUX17_Pos)                   /*!< 0x00000008 */
#define EPWM_HXB9_1_MUX18_Pos                    (4U)
#define EPWM_HXB9_1_MUX18_Msk                    (0x3UL<<EPWM_HXB9_1_MUX18_Pos)                   /*!< 0x00000030 */
#define EPWM_HXB9_1_MUX18                        EPWM_HXB9_1_MUX18_Msk                            /*!< eallow, HXBLOCK */
#define EPWM_HXB9_1_MUX18_0                      (0x1UL<<EPWM_HXB9_1_MUX18_Pos)                   /*!< 0x00000010 */
#define EPWM_HXB9_1_MUX18_1                      (0x2UL<<EPWM_HXB9_1_MUX18_Pos)                   /*!< 0x00000020 */
#define EPWM_HXB9_1_MUX19_Pos                    (6U)
#define EPWM_HXB9_1_MUX19_Msk                    (0x3UL<<EPWM_HXB9_1_MUX19_Pos)                   /*!< 0x000000C0 */
#define EPWM_HXB9_1_MUX19                        EPWM_HXB9_1_MUX19_Msk                            /*!< eallow, HXBLOCK */
#define EPWM_HXB9_1_MUX19_0                      (0x1UL<<EPWM_HXB9_1_MUX19_Pos)                   /*!< 0x00000040 */
#define EPWM_HXB9_1_MUX19_1                      (0x2UL<<EPWM_HXB9_1_MUX19_Pos)                   /*!< 0x00000080 */
#define EPWM_HXB9_1_MUX20_Pos                    (8U)
#define EPWM_HXB9_1_MUX20_Msk                    (0x3UL<<EPWM_HXB9_1_MUX20_Pos)                   /*!< 0x00000300 */
#define EPWM_HXB9_1_MUX20                        EPWM_HXB9_1_MUX20_Msk                            /*!< eallow, HXBLOCK */
#define EPWM_HXB9_1_MUX20_0                      (0x1UL<<EPWM_HXB9_1_MUX20_Pos)                   /*!< 0x00000100 */
#define EPWM_HXB9_1_MUX20_1                      (0x2UL<<EPWM_HXB9_1_MUX20_Pos)                   /*!< 0x00000200 */
#define EPWM_HXB9_1_MUX21_Pos                    (10U)
#define EPWM_HXB9_1_MUX21_Msk                    (0x3UL<<EPWM_HXB9_1_MUX21_Pos)                   /*!< 0x00000C00 */
#define EPWM_HXB9_1_MUX21                        EPWM_HXB9_1_MUX21_Msk                            /*!< eallow, HXBLOCK */
#define EPWM_HXB9_1_MUX21_0                      (0x1UL<<EPWM_HXB9_1_MUX21_Pos)                   /*!< 0x00000400 */
#define EPWM_HXB9_1_MUX21_1                      (0x2UL<<EPWM_HXB9_1_MUX21_Pos)                   /*!< 0x00000800 */
#define EPWM_HXB9_1_MUX22_Pos                    (12U)
#define EPWM_HXB9_1_MUX22_Msk                    (0x3UL<<EPWM_HXB9_1_MUX22_Pos)                   /*!< 0x00003000 */
#define EPWM_HXB9_1_MUX22                        EPWM_HXB9_1_MUX22_Msk                            /*!< eallow, HXBLOCK */
#define EPWM_HXB9_1_MUX22_0                      (0x1UL<<EPWM_HXB9_1_MUX22_Pos)                   /*!< 0x00001000 */
#define EPWM_HXB9_1_MUX22_1                      (0x2UL<<EPWM_HXB9_1_MUX22_Pos)                   /*!< 0x00002000 */
#define EPWM_HXB9_1_MUX23_Pos                    (14U)
#define EPWM_HXB9_1_MUX23_Msk                    (0x3UL<<EPWM_HXB9_1_MUX23_Pos)                   /*!< 0x0000C000 */
#define EPWM_HXB9_1_MUX23                        EPWM_HXB9_1_MUX23_Msk                            /*!< eallow, HXBLOCK */
#define EPWM_HXB9_1_MUX23_0                      (0x1UL<<EPWM_HXB9_1_MUX23_Pos)                   /*!< 0x00004000 */
#define EPWM_HXB9_1_MUX23_1                      (0x2UL<<EPWM_HXB9_1_MUX23_Pos)                   /*!< 0x00008000 */
#define EPWM_HXB9_1_MUX24_Pos                    (16U)
#define EPWM_HXB9_1_MUX24_Msk                    (0x3UL<<EPWM_HXB9_1_MUX24_Pos)                   /*!< 0x00030000 */
#define EPWM_HXB9_1_MUX24                        EPWM_HXB9_1_MUX24_Msk                            /*!< eallow, HXBLOCK */
#define EPWM_HXB9_1_MUX24_0                      (0x1UL<<EPWM_HXB9_1_MUX24_Pos)                   /*!< 0x00010000 */
#define EPWM_HXB9_1_MUX24_1                      (0x2UL<<EPWM_HXB9_1_MUX24_Pos)                   /*!< 0x00020000 */
#define EPWM_HXB9_1_MUX25_Pos                    (18U)
#define EPWM_HXB9_1_MUX25_Msk                    (0x3UL<<EPWM_HXB9_1_MUX25_Pos)                   /*!< 0x000C0000 */
#define EPWM_HXB9_1_MUX25                        EPWM_HXB9_1_MUX25_Msk                            /*!< eallow, HXBLOCK */
#define EPWM_HXB9_1_MUX25_0                      (0x1UL<<EPWM_HXB9_1_MUX25_Pos)                   /*!< 0x00040000 */
#define EPWM_HXB9_1_MUX25_1                      (0x2UL<<EPWM_HXB9_1_MUX25_Pos)                   /*!< 0x00080000 */
#define EPWM_HXB9_1_MUX26_Pos                    (20U)
#define EPWM_HXB9_1_MUX26_Msk                    (0x3UL<<EPWM_HXB9_1_MUX26_Pos)                   /*!< 0x00300000 */
#define EPWM_HXB9_1_MUX26                        EPWM_HXB9_1_MUX26_Msk                            /*!< eallow, HXBLOCK */
#define EPWM_HXB9_1_MUX26_0                      (0x1UL<<EPWM_HXB9_1_MUX26_Pos)                   /*!< 0x00100000 */
#define EPWM_HXB9_1_MUX26_1                      (0x2UL<<EPWM_HXB9_1_MUX26_Pos)                   /*!< 0x00200000 */
#define EPWM_HXB9_1_MUX27_Pos                    (22U)
#define EPWM_HXB9_1_MUX27_Msk                    (0x3UL<<EPWM_HXB9_1_MUX27_Pos)                   /*!< 0x00C00000 */
#define EPWM_HXB9_1_MUX27                        EPWM_HXB9_1_MUX27_Msk                            /*!< eallow, HXBLOCK */
#define EPWM_HXB9_1_MUX27_0                      (0x1UL<<EPWM_HXB9_1_MUX27_Pos)                   /*!< 0x00400000 */
#define EPWM_HXB9_1_MUX27_1                      (0x2UL<<EPWM_HXB9_1_MUX27_Pos)                   /*!< 0x00800000 */
#define EPWM_HXB9_1_MUX28_Pos                    (24U)
#define EPWM_HXB9_1_MUX28_Msk                    (0x3UL<<EPWM_HXB9_1_MUX28_Pos)                   /*!< 0x03000000 */
#define EPWM_HXB9_1_MUX28                        EPWM_HXB9_1_MUX28_Msk                            /*!< eallow, HXBLOCK */
#define EPWM_HXB9_1_MUX28_0                      (0x1UL<<EPWM_HXB9_1_MUX28_Pos)                   /*!< 0x01000000 */
#define EPWM_HXB9_1_MUX28_1                      (0x2UL<<EPWM_HXB9_1_MUX28_Pos)                   /*!< 0x02000000 */
#define EPWM_HXB9_1_MUX29_Pos                    (26U)
#define EPWM_HXB9_1_MUX29_Msk                    (0x3UL<<EPWM_HXB9_1_MUX29_Pos)                   /*!< 0x0C000000 */
#define EPWM_HXB9_1_MUX29                        EPWM_HXB9_1_MUX29_Msk                            /*!< eallow, HXBLOCK */
#define EPWM_HXB9_1_MUX29_0                      (0x1UL<<EPWM_HXB9_1_MUX29_Pos)                   /*!< 0x04000000 */
#define EPWM_HXB9_1_MUX29_1                      (0x2UL<<EPWM_HXB9_1_MUX29_Pos)                   /*!< 0x08000000 */
#define EPWM_HXB9_1_MUX30_Pos                    (28U)
#define EPWM_HXB9_1_MUX30_Msk                    (0x3UL<<EPWM_HXB9_1_MUX30_Pos)                   /*!< 0x30000000 */
#define EPWM_HXB9_1_MUX30                        EPWM_HXB9_1_MUX30_Msk                            /*!< eallow, HXBLOCK */
#define EPWM_HXB9_1_MUX30_0                      (0x1UL<<EPWM_HXB9_1_MUX30_Pos)                   /*!< 0x10000000 */
#define EPWM_HXB9_1_MUX30_1                      (0x2UL<<EPWM_HXB9_1_MUX30_Pos)                   /*!< 0x20000000 */
#define EPWM_HXB9_1_MUX31_Pos                    (30U)
#define EPWM_HXB9_1_MUX31_Msk                    (0x3UL<<EPWM_HXB9_1_MUX31_Pos)                   /*!< 0xC0000000 */
#define EPWM_HXB9_1_MUX31                        EPWM_HXB9_1_MUX31_Msk                            /*!< eallow, HXBLOCK */
#define EPWM_HXB9_1_MUX31_0                      (0x1UL<<EPWM_HXB9_1_MUX31_Pos)                   /*!< 0x40000000 */
#define EPWM_HXB9_1_MUX31_1                      (0x2UL<<EPWM_HXB9_1_MUX31_Pos)                   /*!< 0x80000000 */

/********************************* Bit definition for EPWM_HXB10_0 register ****************************************/
#define EPWM_HXB10_0_MUX0_Pos                    (0U)
#define EPWM_HXB10_0_MUX0_Msk                    (0x3UL<<EPWM_HXB10_0_MUX0_Pos)                   /*!< 0x00000003 */
#define EPWM_HXB10_0_MUX0                        EPWM_HXB10_0_MUX0_Msk                            /*!< eallow, HXBLOCK */
#define EPWM_HXB10_0_MUX0_0                      (0x1UL<<EPWM_HXB10_0_MUX0_Pos)                   /*!< 0x00000001 */
#define EPWM_HXB10_0_MUX0_1                      (0x2UL<<EPWM_HXB10_0_MUX0_Pos)                   /*!< 0x00000002 */
#define EPWM_HXB10_0_MUX1_Pos                    (2U)
#define EPWM_HXB10_0_MUX1_Msk                    (0x3UL<<EPWM_HXB10_0_MUX1_Pos)                   /*!< 0x0000000C */
#define EPWM_HXB10_0_MUX1                        EPWM_HXB10_0_MUX1_Msk                            /*!< eallow, HXBLOCK */
#define EPWM_HXB10_0_MUX1_0                      (0x1UL<<EPWM_HXB10_0_MUX1_Pos)                   /*!< 0x00000004 */
#define EPWM_HXB10_0_MUX1_1                      (0x2UL<<EPWM_HXB10_0_MUX1_Pos)                   /*!< 0x00000008 */
#define EPWM_HXB10_0_MUX2_Pos                    (4U)
#define EPWM_HXB10_0_MUX2_Msk                    (0x3UL<<EPWM_HXB10_0_MUX2_Pos)                   /*!< 0x00000030 */
#define EPWM_HXB10_0_MUX2                        EPWM_HXB10_0_MUX2_Msk                            /*!< eallow, HXBLOCK */
#define EPWM_HXB10_0_MUX2_0                      (0x1UL<<EPWM_HXB10_0_MUX2_Pos)                   /*!< 0x00000010 */
#define EPWM_HXB10_0_MUX2_1                      (0x2UL<<EPWM_HXB10_0_MUX2_Pos)                   /*!< 0x00000020 */
#define EPWM_HXB10_0_MUX3_Pos                    (6U)
#define EPWM_HXB10_0_MUX3_Msk                    (0x3UL<<EPWM_HXB10_0_MUX3_Pos)                   /*!< 0x000000C0 */
#define EPWM_HXB10_0_MUX3                        EPWM_HXB10_0_MUX3_Msk                            /*!< eallow, HXBLOCK */
#define EPWM_HXB10_0_MUX3_0                      (0x1UL<<EPWM_HXB10_0_MUX3_Pos)                   /*!< 0x00000040 */
#define EPWM_HXB10_0_MUX3_1                      (0x2UL<<EPWM_HXB10_0_MUX3_Pos)                   /*!< 0x00000080 */
#define EPWM_HXB10_0_MUX4_Pos                    (8U)
#define EPWM_HXB10_0_MUX4_Msk                    (0x3UL<<EPWM_HXB10_0_MUX4_Pos)                   /*!< 0x00000300 */
#define EPWM_HXB10_0_MUX4                        EPWM_HXB10_0_MUX4_Msk                            /*!< eallow, HXBLOCK */
#define EPWM_HXB10_0_MUX4_0                      (0x1UL<<EPWM_HXB10_0_MUX4_Pos)                   /*!< 0x00000100 */
#define EPWM_HXB10_0_MUX4_1                      (0x2UL<<EPWM_HXB10_0_MUX4_Pos)                   /*!< 0x00000200 */
#define EPWM_HXB10_0_MUX5_Pos                    (10U)
#define EPWM_HXB10_0_MUX5_Msk                    (0x3UL<<EPWM_HXB10_0_MUX5_Pos)                   /*!< 0x00000C00 */
#define EPWM_HXB10_0_MUX5                        EPWM_HXB10_0_MUX5_Msk                            /*!< eallow, HXBLOCK */
#define EPWM_HXB10_0_MUX5_0                      (0x1UL<<EPWM_HXB10_0_MUX5_Pos)                   /*!< 0x00000400 */
#define EPWM_HXB10_0_MUX5_1                      (0x2UL<<EPWM_HXB10_0_MUX5_Pos)                   /*!< 0x00000800 */
#define EPWM_HXB10_0_MUX6_Pos                    (12U)
#define EPWM_HXB10_0_MUX6_Msk                    (0x3UL<<EPWM_HXB10_0_MUX6_Pos)                   /*!< 0x00003000 */
#define EPWM_HXB10_0_MUX6                        EPWM_HXB10_0_MUX6_Msk                            /*!< eallow, HXBLOCK */
#define EPWM_HXB10_0_MUX6_0                      (0x1UL<<EPWM_HXB10_0_MUX6_Pos)                   /*!< 0x00001000 */
#define EPWM_HXB10_0_MUX6_1                      (0x2UL<<EPWM_HXB10_0_MUX6_Pos)                   /*!< 0x00002000 */
#define EPWM_HXB10_0_MUX7_Pos                    (14U)
#define EPWM_HXB10_0_MUX7_Msk                    (0x3UL<<EPWM_HXB10_0_MUX7_Pos)                   /*!< 0x0000C000 */
#define EPWM_HXB10_0_MUX7                        EPWM_HXB10_0_MUX7_Msk                            /*!< eallow, HXBLOCK */
#define EPWM_HXB10_0_MUX7_0                      (0x1UL<<EPWM_HXB10_0_MUX7_Pos)                   /*!< 0x00004000 */
#define EPWM_HXB10_0_MUX7_1                      (0x2UL<<EPWM_HXB10_0_MUX7_Pos)                   /*!< 0x00008000 */
#define EPWM_HXB10_0_MUX8_Pos                    (16U)
#define EPWM_HXB10_0_MUX8_Msk                    (0x3UL<<EPWM_HXB10_0_MUX8_Pos)                   /*!< 0x00030000 */
#define EPWM_HXB10_0_MUX8                        EPWM_HXB10_0_MUX8_Msk                            /*!< eallow, HXBLOCK */
#define EPWM_HXB10_0_MUX8_0                      (0x1UL<<EPWM_HXB10_0_MUX8_Pos)                   /*!< 0x00010000 */
#define EPWM_HXB10_0_MUX8_1                      (0x2UL<<EPWM_HXB10_0_MUX8_Pos)                   /*!< 0x00020000 */
#define EPWM_HXB10_0_MUX9_Pos                    (18U)
#define EPWM_HXB10_0_MUX9_Msk                    (0x3UL<<EPWM_HXB10_0_MUX9_Pos)                   /*!< 0x000C0000 */
#define EPWM_HXB10_0_MUX9                        EPWM_HXB10_0_MUX9_Msk                            /*!< eallow, HXBLOCK */
#define EPWM_HXB10_0_MUX9_0                      (0x1UL<<EPWM_HXB10_0_MUX9_Pos)                   /*!< 0x00040000 */
#define EPWM_HXB10_0_MUX9_1                      (0x2UL<<EPWM_HXB10_0_MUX9_Pos)                   /*!< 0x00080000 */
#define EPWM_HXB10_0_MUX10_Pos                   (20U)
#define EPWM_HXB10_0_MUX10_Msk                   (0x3UL<<EPWM_HXB10_0_MUX10_Pos)                  /*!< 0x00300000 */
#define EPWM_HXB10_0_MUX10                       EPWM_HXB10_0_MUX10_Msk                           /*!< eallow, HXBLOCK */
#define EPWM_HXB10_0_MUX10_0                     (0x1UL<<EPWM_HXB10_0_MUX10_Pos)                  /*!< 0x00100000 */
#define EPWM_HXB10_0_MUX10_1                     (0x2UL<<EPWM_HXB10_0_MUX10_Pos)                  /*!< 0x00200000 */
#define EPWM_HXB10_0_MUX11_Pos                   (22U)
#define EPWM_HXB10_0_MUX11_Msk                   (0x3UL<<EPWM_HXB10_0_MUX11_Pos)                  /*!< 0x00C00000 */
#define EPWM_HXB10_0_MUX11                       EPWM_HXB10_0_MUX11_Msk                           /*!< eallow, HXBLOCK */
#define EPWM_HXB10_0_MUX11_0                     (0x1UL<<EPWM_HXB10_0_MUX11_Pos)                  /*!< 0x00400000 */
#define EPWM_HXB10_0_MUX11_1                     (0x2UL<<EPWM_HXB10_0_MUX11_Pos)                  /*!< 0x00800000 */
#define EPWM_HXB10_0_MUX12_Pos                   (24U)
#define EPWM_HXB10_0_MUX12_Msk                   (0x3UL<<EPWM_HXB10_0_MUX12_Pos)                  /*!< 0x03000000 */
#define EPWM_HXB10_0_MUX12                       EPWM_HXB10_0_MUX12_Msk                           /*!< eallow, HXBLOCK */
#define EPWM_HXB10_0_MUX12_0                     (0x1UL<<EPWM_HXB10_0_MUX12_Pos)                  /*!< 0x01000000 */
#define EPWM_HXB10_0_MUX12_1                     (0x2UL<<EPWM_HXB10_0_MUX12_Pos)                  /*!< 0x02000000 */
#define EPWM_HXB10_0_MUX13_Pos                   (26U)
#define EPWM_HXB10_0_MUX13_Msk                   (0x3UL<<EPWM_HXB10_0_MUX13_Pos)                  /*!< 0x0C000000 */
#define EPWM_HXB10_0_MUX13                       EPWM_HXB10_0_MUX13_Msk                           /*!< eallow, HXBLOCK */
#define EPWM_HXB10_0_MUX13_0                     (0x1UL<<EPWM_HXB10_0_MUX13_Pos)                  /*!< 0x04000000 */
#define EPWM_HXB10_0_MUX13_1                     (0x2UL<<EPWM_HXB10_0_MUX13_Pos)                  /*!< 0x08000000 */
#define EPWM_HXB10_0_MUX14_Pos                   (28U)
#define EPWM_HXB10_0_MUX14_Msk                   (0x3UL<<EPWM_HXB10_0_MUX14_Pos)                  /*!< 0x30000000 */
#define EPWM_HXB10_0_MUX14                       EPWM_HXB10_0_MUX14_Msk                           /*!< eallow, HXBLOCK */
#define EPWM_HXB10_0_MUX14_0                     (0x1UL<<EPWM_HXB10_0_MUX14_Pos)                  /*!< 0x10000000 */
#define EPWM_HXB10_0_MUX14_1                     (0x2UL<<EPWM_HXB10_0_MUX14_Pos)                  /*!< 0x20000000 */
#define EPWM_HXB10_0_MUX15_Pos                   (30U)
#define EPWM_HXB10_0_MUX15_Msk                   (0x3UL<<EPWM_HXB10_0_MUX15_Pos)                  /*!< 0xC0000000 */
#define EPWM_HXB10_0_MUX15                       EPWM_HXB10_0_MUX15_Msk                           /*!< eallow, HXBLOCK */
#define EPWM_HXB10_0_MUX15_0                     (0x1UL<<EPWM_HXB10_0_MUX15_Pos)                  /*!< 0x40000000 */
#define EPWM_HXB10_0_MUX15_1                     (0x2UL<<EPWM_HXB10_0_MUX15_Pos)                  /*!< 0x80000000 */

/********************************* Bit definition for EPWM_HXB10_1 register ****************************************/
#define EPWM_HXB10_1_MUX16_Pos                   (0U)
#define EPWM_HXB10_1_MUX16_Msk                   (0x3UL<<EPWM_HXB10_1_MUX16_Pos)                  /*!< 0x00000003 */
#define EPWM_HXB10_1_MUX16                       EPWM_HXB10_1_MUX16_Msk                           /*!< eallow, HXBLOCK */
#define EPWM_HXB10_1_MUX16_0                     (0x1UL<<EPWM_HXB10_1_MUX16_Pos)                  /*!< 0x00000001 */
#define EPWM_HXB10_1_MUX16_1                     (0x2UL<<EPWM_HXB10_1_MUX16_Pos)                  /*!< 0x00000002 */
#define EPWM_HXB10_1_MUX17_Pos                   (2U)
#define EPWM_HXB10_1_MUX17_Msk                   (0x3UL<<EPWM_HXB10_1_MUX17_Pos)                  /*!< 0x0000000C */
#define EPWM_HXB10_1_MUX17                       EPWM_HXB10_1_MUX17_Msk                           /*!< eallow, HXBLOCK */
#define EPWM_HXB10_1_MUX17_0                     (0x1UL<<EPWM_HXB10_1_MUX17_Pos)                  /*!< 0x00000004 */
#define EPWM_HXB10_1_MUX17_1                     (0x2UL<<EPWM_HXB10_1_MUX17_Pos)                  /*!< 0x00000008 */
#define EPWM_HXB10_1_MUX18_Pos                   (4U)
#define EPWM_HXB10_1_MUX18_Msk                   (0x3UL<<EPWM_HXB10_1_MUX18_Pos)                  /*!< 0x00000030 */
#define EPWM_HXB10_1_MUX18                       EPWM_HXB10_1_MUX18_Msk                           /*!< eallow, HXBLOCK */
#define EPWM_HXB10_1_MUX18_0                     (0x1UL<<EPWM_HXB10_1_MUX18_Pos)                  /*!< 0x00000010 */
#define EPWM_HXB10_1_MUX18_1                     (0x2UL<<EPWM_HXB10_1_MUX18_Pos)                  /*!< 0x00000020 */
#define EPWM_HXB10_1_MUX19_Pos                   (6U)
#define EPWM_HXB10_1_MUX19_Msk                   (0x3UL<<EPWM_HXB10_1_MUX19_Pos)                  /*!< 0x000000C0 */
#define EPWM_HXB10_1_MUX19                       EPWM_HXB10_1_MUX19_Msk                           /*!< eallow, HXBLOCK */
#define EPWM_HXB10_1_MUX19_0                     (0x1UL<<EPWM_HXB10_1_MUX19_Pos)                  /*!< 0x00000040 */
#define EPWM_HXB10_1_MUX19_1                     (0x2UL<<EPWM_HXB10_1_MUX19_Pos)                  /*!< 0x00000080 */
#define EPWM_HXB10_1_MUX20_Pos                   (8U)
#define EPWM_HXB10_1_MUX20_Msk                   (0x3UL<<EPWM_HXB10_1_MUX20_Pos)                  /*!< 0x00000300 */
#define EPWM_HXB10_1_MUX20                       EPWM_HXB10_1_MUX20_Msk                           /*!< eallow, HXBLOCK */
#define EPWM_HXB10_1_MUX20_0                     (0x1UL<<EPWM_HXB10_1_MUX20_Pos)                  /*!< 0x00000100 */
#define EPWM_HXB10_1_MUX20_1                     (0x2UL<<EPWM_HXB10_1_MUX20_Pos)                  /*!< 0x00000200 */
#define EPWM_HXB10_1_MUX21_Pos                   (10U)
#define EPWM_HXB10_1_MUX21_Msk                   (0x3UL<<EPWM_HXB10_1_MUX21_Pos)                  /*!< 0x00000C00 */
#define EPWM_HXB10_1_MUX21                       EPWM_HXB10_1_MUX21_Msk                           /*!< eallow, HXBLOCK */
#define EPWM_HXB10_1_MUX21_0                     (0x1UL<<EPWM_HXB10_1_MUX21_Pos)                  /*!< 0x00000400 */
#define EPWM_HXB10_1_MUX21_1                     (0x2UL<<EPWM_HXB10_1_MUX21_Pos)                  /*!< 0x00000800 */
#define EPWM_HXB10_1_MUX22_Pos                   (12U)
#define EPWM_HXB10_1_MUX22_Msk                   (0x3UL<<EPWM_HXB10_1_MUX22_Pos)                  /*!< 0x00003000 */
#define EPWM_HXB10_1_MUX22                       EPWM_HXB10_1_MUX22_Msk                           /*!< eallow, HXBLOCK */
#define EPWM_HXB10_1_MUX22_0                     (0x1UL<<EPWM_HXB10_1_MUX22_Pos)                  /*!< 0x00001000 */
#define EPWM_HXB10_1_MUX22_1                     (0x2UL<<EPWM_HXB10_1_MUX22_Pos)                  /*!< 0x00002000 */
#define EPWM_HXB10_1_MUX23_Pos                   (14U)
#define EPWM_HXB10_1_MUX23_Msk                   (0x3UL<<EPWM_HXB10_1_MUX23_Pos)                  /*!< 0x0000C000 */
#define EPWM_HXB10_1_MUX23                       EPWM_HXB10_1_MUX23_Msk                           /*!< eallow, HXBLOCK */
#define EPWM_HXB10_1_MUX23_0                     (0x1UL<<EPWM_HXB10_1_MUX23_Pos)                  /*!< 0x00004000 */
#define EPWM_HXB10_1_MUX23_1                     (0x2UL<<EPWM_HXB10_1_MUX23_Pos)                  /*!< 0x00008000 */
#define EPWM_HXB10_1_MUX24_Pos                   (16U)
#define EPWM_HXB10_1_MUX24_Msk                   (0x3UL<<EPWM_HXB10_1_MUX24_Pos)                  /*!< 0x00030000 */
#define EPWM_HXB10_1_MUX24                       EPWM_HXB10_1_MUX24_Msk                           /*!< eallow, HXBLOCK */
#define EPWM_HXB10_1_MUX24_0                     (0x1UL<<EPWM_HXB10_1_MUX24_Pos)                  /*!< 0x00010000 */
#define EPWM_HXB10_1_MUX24_1                     (0x2UL<<EPWM_HXB10_1_MUX24_Pos)                  /*!< 0x00020000 */
#define EPWM_HXB10_1_MUX25_Pos                   (18U)
#define EPWM_HXB10_1_MUX25_Msk                   (0x3UL<<EPWM_HXB10_1_MUX25_Pos)                  /*!< 0x000C0000 */
#define EPWM_HXB10_1_MUX25                       EPWM_HXB10_1_MUX25_Msk                           /*!< eallow, HXBLOCK */
#define EPWM_HXB10_1_MUX25_0                     (0x1UL<<EPWM_HXB10_1_MUX25_Pos)                  /*!< 0x00040000 */
#define EPWM_HXB10_1_MUX25_1                     (0x2UL<<EPWM_HXB10_1_MUX25_Pos)                  /*!< 0x00080000 */
#define EPWM_HXB10_1_MUX26_Pos                   (20U)
#define EPWM_HXB10_1_MUX26_Msk                   (0x3UL<<EPWM_HXB10_1_MUX26_Pos)                  /*!< 0x00300000 */
#define EPWM_HXB10_1_MUX26                       EPWM_HXB10_1_MUX26_Msk                           /*!< eallow, HXBLOCK */
#define EPWM_HXB10_1_MUX26_0                     (0x1UL<<EPWM_HXB10_1_MUX26_Pos)                  /*!< 0x00100000 */
#define EPWM_HXB10_1_MUX26_1                     (0x2UL<<EPWM_HXB10_1_MUX26_Pos)                  /*!< 0x00200000 */
#define EPWM_HXB10_1_MUX27_Pos                   (22U)
#define EPWM_HXB10_1_MUX27_Msk                   (0x3UL<<EPWM_HXB10_1_MUX27_Pos)                  /*!< 0x00C00000 */
#define EPWM_HXB10_1_MUX27                       EPWM_HXB10_1_MUX27_Msk                           /*!< eallow, HXBLOCK */
#define EPWM_HXB10_1_MUX27_0                     (0x1UL<<EPWM_HXB10_1_MUX27_Pos)                  /*!< 0x00400000 */
#define EPWM_HXB10_1_MUX27_1                     (0x2UL<<EPWM_HXB10_1_MUX27_Pos)                  /*!< 0x00800000 */
#define EPWM_HXB10_1_MUX28_Pos                   (24U)
#define EPWM_HXB10_1_MUX28_Msk                   (0x3UL<<EPWM_HXB10_1_MUX28_Pos)                  /*!< 0x03000000 */
#define EPWM_HXB10_1_MUX28                       EPWM_HXB10_1_MUX28_Msk                           /*!< eallow, HXBLOCK */
#define EPWM_HXB10_1_MUX28_0                     (0x1UL<<EPWM_HXB10_1_MUX28_Pos)                  /*!< 0x01000000 */
#define EPWM_HXB10_1_MUX28_1                     (0x2UL<<EPWM_HXB10_1_MUX28_Pos)                  /*!< 0x02000000 */
#define EPWM_HXB10_1_MUX29_Pos                   (26U)
#define EPWM_HXB10_1_MUX29_Msk                   (0x3UL<<EPWM_HXB10_1_MUX29_Pos)                  /*!< 0x0C000000 */
#define EPWM_HXB10_1_MUX29                       EPWM_HXB10_1_MUX29_Msk                           /*!< eallow, HXBLOCK */
#define EPWM_HXB10_1_MUX29_0                     (0x1UL<<EPWM_HXB10_1_MUX29_Pos)                  /*!< 0x04000000 */
#define EPWM_HXB10_1_MUX29_1                     (0x2UL<<EPWM_HXB10_1_MUX29_Pos)                  /*!< 0x08000000 */
#define EPWM_HXB10_1_MUX30_Pos                   (28U)
#define EPWM_HXB10_1_MUX30_Msk                   (0x3UL<<EPWM_HXB10_1_MUX30_Pos)                  /*!< 0x30000000 */
#define EPWM_HXB10_1_MUX30                       EPWM_HXB10_1_MUX30_Msk                           /*!< eallow, HXBLOCK */
#define EPWM_HXB10_1_MUX30_0                     (0x1UL<<EPWM_HXB10_1_MUX30_Pos)                  /*!< 0x10000000 */
#define EPWM_HXB10_1_MUX30_1                     (0x2UL<<EPWM_HXB10_1_MUX30_Pos)                  /*!< 0x20000000 */
#define EPWM_HXB10_1_MUX31_Pos                   (30U)
#define EPWM_HXB10_1_MUX31_Msk                   (0x3UL<<EPWM_HXB10_1_MUX31_Pos)                  /*!< 0xC0000000 */
#define EPWM_HXB10_1_MUX31                       EPWM_HXB10_1_MUX31_Msk                           /*!< eallow, HXBLOCK */
#define EPWM_HXB10_1_MUX31_0                     (0x1UL<<EPWM_HXB10_1_MUX31_Pos)                  /*!< 0x40000000 */
#define EPWM_HXB10_1_MUX31_1                     (0x2UL<<EPWM_HXB10_1_MUX31_Pos)                  /*!< 0x80000000 */

/********************************* Bit definition for EPWM_HXB11_0 register ****************************************/
#define EPWM_HXB11_0_MUX0_Pos                    (0U)
#define EPWM_HXB11_0_MUX0_Msk                    (0x3UL<<EPWM_HXB11_0_MUX0_Pos)                   /*!< 0x00000003 */
#define EPWM_HXB11_0_MUX0                        EPWM_HXB11_0_MUX0_Msk                            /*!< eallow, HXBLOCK */
#define EPWM_HXB11_0_MUX0_0                      (0x1UL<<EPWM_HXB11_0_MUX0_Pos)                   /*!< 0x00000001 */
#define EPWM_HXB11_0_MUX0_1                      (0x2UL<<EPWM_HXB11_0_MUX0_Pos)                   /*!< 0x00000002 */
#define EPWM_HXB11_0_MUX1_Pos                    (2U)
#define EPWM_HXB11_0_MUX1_Msk                    (0x3UL<<EPWM_HXB11_0_MUX1_Pos)                   /*!< 0x0000000C */
#define EPWM_HXB11_0_MUX1                        EPWM_HXB11_0_MUX1_Msk                            /*!< eallow, HXBLOCK */
#define EPWM_HXB11_0_MUX1_0                      (0x1UL<<EPWM_HXB11_0_MUX1_Pos)                   /*!< 0x00000004 */
#define EPWM_HXB11_0_MUX1_1                      (0x2UL<<EPWM_HXB11_0_MUX1_Pos)                   /*!< 0x00000008 */
#define EPWM_HXB11_0_MUX2_Pos                    (4U)
#define EPWM_HXB11_0_MUX2_Msk                    (0x3UL<<EPWM_HXB11_0_MUX2_Pos)                   /*!< 0x00000030 */
#define EPWM_HXB11_0_MUX2                        EPWM_HXB11_0_MUX2_Msk                            /*!< eallow, HXBLOCK */
#define EPWM_HXB11_0_MUX2_0                      (0x1UL<<EPWM_HXB11_0_MUX2_Pos)                   /*!< 0x00000010 */
#define EPWM_HXB11_0_MUX2_1                      (0x2UL<<EPWM_HXB11_0_MUX2_Pos)                   /*!< 0x00000020 */
#define EPWM_HXB11_0_MUX3_Pos                    (6U)
#define EPWM_HXB11_0_MUX3_Msk                    (0x3UL<<EPWM_HXB11_0_MUX3_Pos)                   /*!< 0x000000C0 */
#define EPWM_HXB11_0_MUX3                        EPWM_HXB11_0_MUX3_Msk                            /*!< eallow, HXBLOCK */
#define EPWM_HXB11_0_MUX3_0                      (0x1UL<<EPWM_HXB11_0_MUX3_Pos)                   /*!< 0x00000040 */
#define EPWM_HXB11_0_MUX3_1                      (0x2UL<<EPWM_HXB11_0_MUX3_Pos)                   /*!< 0x00000080 */
#define EPWM_HXB11_0_MUX4_Pos                    (8U)
#define EPWM_HXB11_0_MUX4_Msk                    (0x3UL<<EPWM_HXB11_0_MUX4_Pos)                   /*!< 0x00000300 */
#define EPWM_HXB11_0_MUX4                        EPWM_HXB11_0_MUX4_Msk                            /*!< eallow, HXBLOCK */
#define EPWM_HXB11_0_MUX4_0                      (0x1UL<<EPWM_HXB11_0_MUX4_Pos)                   /*!< 0x00000100 */
#define EPWM_HXB11_0_MUX4_1                      (0x2UL<<EPWM_HXB11_0_MUX4_Pos)                   /*!< 0x00000200 */
#define EPWM_HXB11_0_MUX5_Pos                    (10U)
#define EPWM_HXB11_0_MUX5_Msk                    (0x3UL<<EPWM_HXB11_0_MUX5_Pos)                   /*!< 0x00000C00 */
#define EPWM_HXB11_0_MUX5                        EPWM_HXB11_0_MUX5_Msk                            /*!< eallow, HXBLOCK */
#define EPWM_HXB11_0_MUX5_0                      (0x1UL<<EPWM_HXB11_0_MUX5_Pos)                   /*!< 0x00000400 */
#define EPWM_HXB11_0_MUX5_1                      (0x2UL<<EPWM_HXB11_0_MUX5_Pos)                   /*!< 0x00000800 */
#define EPWM_HXB11_0_MUX6_Pos                    (12U)
#define EPWM_HXB11_0_MUX6_Msk                    (0x3UL<<EPWM_HXB11_0_MUX6_Pos)                   /*!< 0x00003000 */
#define EPWM_HXB11_0_MUX6                        EPWM_HXB11_0_MUX6_Msk                            /*!< eallow, HXBLOCK */
#define EPWM_HXB11_0_MUX6_0                      (0x1UL<<EPWM_HXB11_0_MUX6_Pos)                   /*!< 0x00001000 */
#define EPWM_HXB11_0_MUX6_1                      (0x2UL<<EPWM_HXB11_0_MUX6_Pos)                   /*!< 0x00002000 */
#define EPWM_HXB11_0_MUX7_Pos                    (14U)
#define EPWM_HXB11_0_MUX7_Msk                    (0x3UL<<EPWM_HXB11_0_MUX7_Pos)                   /*!< 0x0000C000 */
#define EPWM_HXB11_0_MUX7                        EPWM_HXB11_0_MUX7_Msk                            /*!< eallow, HXBLOCK */
#define EPWM_HXB11_0_MUX7_0                      (0x1UL<<EPWM_HXB11_0_MUX7_Pos)                   /*!< 0x00004000 */
#define EPWM_HXB11_0_MUX7_1                      (0x2UL<<EPWM_HXB11_0_MUX7_Pos)                   /*!< 0x00008000 */
#define EPWM_HXB11_0_MUX8_Pos                    (16U)
#define EPWM_HXB11_0_MUX8_Msk                    (0x3UL<<EPWM_HXB11_0_MUX8_Pos)                   /*!< 0x00030000 */
#define EPWM_HXB11_0_MUX8                        EPWM_HXB11_0_MUX8_Msk                            /*!< eallow, HXBLOCK */
#define EPWM_HXB11_0_MUX8_0                      (0x1UL<<EPWM_HXB11_0_MUX8_Pos)                   /*!< 0x00010000 */
#define EPWM_HXB11_0_MUX8_1                      (0x2UL<<EPWM_HXB11_0_MUX8_Pos)                   /*!< 0x00020000 */
#define EPWM_HXB11_0_MUX9_Pos                    (18U)
#define EPWM_HXB11_0_MUX9_Msk                    (0x3UL<<EPWM_HXB11_0_MUX9_Pos)                   /*!< 0x000C0000 */
#define EPWM_HXB11_0_MUX9                        EPWM_HXB11_0_MUX9_Msk                            /*!< eallow, HXBLOCK */
#define EPWM_HXB11_0_MUX9_0                      (0x1UL<<EPWM_HXB11_0_MUX9_Pos)                   /*!< 0x00040000 */
#define EPWM_HXB11_0_MUX9_1                      (0x2UL<<EPWM_HXB11_0_MUX9_Pos)                   /*!< 0x00080000 */
#define EPWM_HXB11_0_MUX10_Pos                   (20U)
#define EPWM_HXB11_0_MUX10_Msk                   (0x3UL<<EPWM_HXB11_0_MUX10_Pos)                  /*!< 0x00300000 */
#define EPWM_HXB11_0_MUX10                       EPWM_HXB11_0_MUX10_Msk                           /*!< eallow, HXBLOCK */
#define EPWM_HXB11_0_MUX10_0                     (0x1UL<<EPWM_HXB11_0_MUX10_Pos)                  /*!< 0x00100000 */
#define EPWM_HXB11_0_MUX10_1                     (0x2UL<<EPWM_HXB11_0_MUX10_Pos)                  /*!< 0x00200000 */
#define EPWM_HXB11_0_MUX11_Pos                   (22U)
#define EPWM_HXB11_0_MUX11_Msk                   (0x3UL<<EPWM_HXB11_0_MUX11_Pos)                  /*!< 0x00C00000 */
#define EPWM_HXB11_0_MUX11                       EPWM_HXB11_0_MUX11_Msk                           /*!< eallow, HXBLOCK */
#define EPWM_HXB11_0_MUX11_0                     (0x1UL<<EPWM_HXB11_0_MUX11_Pos)                  /*!< 0x00400000 */
#define EPWM_HXB11_0_MUX11_1                     (0x2UL<<EPWM_HXB11_0_MUX11_Pos)                  /*!< 0x00800000 */
#define EPWM_HXB11_0_MUX12_Pos                   (24U)
#define EPWM_HXB11_0_MUX12_Msk                   (0x3UL<<EPWM_HXB11_0_MUX12_Pos)                  /*!< 0x03000000 */
#define EPWM_HXB11_0_MUX12                       EPWM_HXB11_0_MUX12_Msk                           /*!< eallow, HXBLOCK */
#define EPWM_HXB11_0_MUX12_0                     (0x1UL<<EPWM_HXB11_0_MUX12_Pos)                  /*!< 0x01000000 */
#define EPWM_HXB11_0_MUX12_1                     (0x2UL<<EPWM_HXB11_0_MUX12_Pos)                  /*!< 0x02000000 */
#define EPWM_HXB11_0_MUX13_Pos                   (26U)
#define EPWM_HXB11_0_MUX13_Msk                   (0x3UL<<EPWM_HXB11_0_MUX13_Pos)                  /*!< 0x0C000000 */
#define EPWM_HXB11_0_MUX13                       EPWM_HXB11_0_MUX13_Msk                           /*!< eallow, HXBLOCK */
#define EPWM_HXB11_0_MUX13_0                     (0x1UL<<EPWM_HXB11_0_MUX13_Pos)                  /*!< 0x04000000 */
#define EPWM_HXB11_0_MUX13_1                     (0x2UL<<EPWM_HXB11_0_MUX13_Pos)                  /*!< 0x08000000 */
#define EPWM_HXB11_0_MUX14_Pos                   (28U)
#define EPWM_HXB11_0_MUX14_Msk                   (0x3UL<<EPWM_HXB11_0_MUX14_Pos)                  /*!< 0x30000000 */
#define EPWM_HXB11_0_MUX14                       EPWM_HXB11_0_MUX14_Msk                           /*!< eallow, HXBLOCK */
#define EPWM_HXB11_0_MUX14_0                     (0x1UL<<EPWM_HXB11_0_MUX14_Pos)                  /*!< 0x10000000 */
#define EPWM_HXB11_0_MUX14_1                     (0x2UL<<EPWM_HXB11_0_MUX14_Pos)                  /*!< 0x20000000 */
#define EPWM_HXB11_0_MUX15_Pos                   (30U)
#define EPWM_HXB11_0_MUX15_Msk                   (0x3UL<<EPWM_HXB11_0_MUX15_Pos)                  /*!< 0xC0000000 */
#define EPWM_HXB11_0_MUX15                       EPWM_HXB11_0_MUX15_Msk                           /*!< eallow, HXBLOCK */
#define EPWM_HXB11_0_MUX15_0                     (0x1UL<<EPWM_HXB11_0_MUX15_Pos)                  /*!< 0x40000000 */
#define EPWM_HXB11_0_MUX15_1                     (0x2UL<<EPWM_HXB11_0_MUX15_Pos)                  /*!< 0x80000000 */

/********************************* Bit definition for EPWM_HXB11_1 register ****************************************/
#define EPWM_HXB11_1_MUX16_Pos                   (0U)
#define EPWM_HXB11_1_MUX16_Msk                   (0x3UL<<EPWM_HXB11_1_MUX16_Pos)                  /*!< 0x00000003 */
#define EPWM_HXB11_1_MUX16                       EPWM_HXB11_1_MUX16_Msk                           /*!< eallow, HXBLOCK */
#define EPWM_HXB11_1_MUX16_0                     (0x1UL<<EPWM_HXB11_1_MUX16_Pos)                  /*!< 0x00000001 */
#define EPWM_HXB11_1_MUX16_1                     (0x2UL<<EPWM_HXB11_1_MUX16_Pos)                  /*!< 0x00000002 */
#define EPWM_HXB11_1_MUX17_Pos                   (2U)
#define EPWM_HXB11_1_MUX17_Msk                   (0x3UL<<EPWM_HXB11_1_MUX17_Pos)                  /*!< 0x0000000C */
#define EPWM_HXB11_1_MUX17                       EPWM_HXB11_1_MUX17_Msk                           /*!< eallow, HXBLOCK */
#define EPWM_HXB11_1_MUX17_0                     (0x1UL<<EPWM_HXB11_1_MUX17_Pos)                  /*!< 0x00000004 */
#define EPWM_HXB11_1_MUX17_1                     (0x2UL<<EPWM_HXB11_1_MUX17_Pos)                  /*!< 0x00000008 */
#define EPWM_HXB11_1_MUX18_Pos                   (4U)
#define EPWM_HXB11_1_MUX18_Msk                   (0x3UL<<EPWM_HXB11_1_MUX18_Pos)                  /*!< 0x00000030 */
#define EPWM_HXB11_1_MUX18                       EPWM_HXB11_1_MUX18_Msk                           /*!< eallow, HXBLOCK */
#define EPWM_HXB11_1_MUX18_0                     (0x1UL<<EPWM_HXB11_1_MUX18_Pos)                  /*!< 0x00000010 */
#define EPWM_HXB11_1_MUX18_1                     (0x2UL<<EPWM_HXB11_1_MUX18_Pos)                  /*!< 0x00000020 */
#define EPWM_HXB11_1_MUX19_Pos                   (6U)
#define EPWM_HXB11_1_MUX19_Msk                   (0x3UL<<EPWM_HXB11_1_MUX19_Pos)                  /*!< 0x000000C0 */
#define EPWM_HXB11_1_MUX19                       EPWM_HXB11_1_MUX19_Msk                           /*!< eallow, HXBLOCK */
#define EPWM_HXB11_1_MUX19_0                     (0x1UL<<EPWM_HXB11_1_MUX19_Pos)                  /*!< 0x00000040 */
#define EPWM_HXB11_1_MUX19_1                     (0x2UL<<EPWM_HXB11_1_MUX19_Pos)                  /*!< 0x00000080 */
#define EPWM_HXB11_1_MUX20_Pos                   (8U)
#define EPWM_HXB11_1_MUX20_Msk                   (0x3UL<<EPWM_HXB11_1_MUX20_Pos)                  /*!< 0x00000300 */
#define EPWM_HXB11_1_MUX20                       EPWM_HXB11_1_MUX20_Msk                           /*!< eallow, HXBLOCK */
#define EPWM_HXB11_1_MUX20_0                     (0x1UL<<EPWM_HXB11_1_MUX20_Pos)                  /*!< 0x00000100 */
#define EPWM_HXB11_1_MUX20_1                     (0x2UL<<EPWM_HXB11_1_MUX20_Pos)                  /*!< 0x00000200 */
#define EPWM_HXB11_1_MUX21_Pos                   (10U)
#define EPWM_HXB11_1_MUX21_Msk                   (0x3UL<<EPWM_HXB11_1_MUX21_Pos)                  /*!< 0x00000C00 */
#define EPWM_HXB11_1_MUX21                       EPWM_HXB11_1_MUX21_Msk                           /*!< eallow, HXBLOCK */
#define EPWM_HXB11_1_MUX21_0                     (0x1UL<<EPWM_HXB11_1_MUX21_Pos)                  /*!< 0x00000400 */
#define EPWM_HXB11_1_MUX21_1                     (0x2UL<<EPWM_HXB11_1_MUX21_Pos)                  /*!< 0x00000800 */
#define EPWM_HXB11_1_MUX22_Pos                   (12U)
#define EPWM_HXB11_1_MUX22_Msk                   (0x3UL<<EPWM_HXB11_1_MUX22_Pos)                  /*!< 0x00003000 */
#define EPWM_HXB11_1_MUX22                       EPWM_HXB11_1_MUX22_Msk                           /*!< eallow, HXBLOCK */
#define EPWM_HXB11_1_MUX22_0                     (0x1UL<<EPWM_HXB11_1_MUX22_Pos)                  /*!< 0x00001000 */
#define EPWM_HXB11_1_MUX22_1                     (0x2UL<<EPWM_HXB11_1_MUX22_Pos)                  /*!< 0x00002000 */
#define EPWM_HXB11_1_MUX23_Pos                   (14U)
#define EPWM_HXB11_1_MUX23_Msk                   (0x3UL<<EPWM_HXB11_1_MUX23_Pos)                  /*!< 0x0000C000 */
#define EPWM_HXB11_1_MUX23                       EPWM_HXB11_1_MUX23_Msk                           /*!< eallow, HXBLOCK */
#define EPWM_HXB11_1_MUX23_0                     (0x1UL<<EPWM_HXB11_1_MUX23_Pos)                  /*!< 0x00004000 */
#define EPWM_HXB11_1_MUX23_1                     (0x2UL<<EPWM_HXB11_1_MUX23_Pos)                  /*!< 0x00008000 */
#define EPWM_HXB11_1_MUX24_Pos                   (16U)
#define EPWM_HXB11_1_MUX24_Msk                   (0x3UL<<EPWM_HXB11_1_MUX24_Pos)                  /*!< 0x00030000 */
#define EPWM_HXB11_1_MUX24                       EPWM_HXB11_1_MUX24_Msk                           /*!< eallow, HXBLOCK */
#define EPWM_HXB11_1_MUX24_0                     (0x1UL<<EPWM_HXB11_1_MUX24_Pos)                  /*!< 0x00010000 */
#define EPWM_HXB11_1_MUX24_1                     (0x2UL<<EPWM_HXB11_1_MUX24_Pos)                  /*!< 0x00020000 */
#define EPWM_HXB11_1_MUX25_Pos                   (18U)
#define EPWM_HXB11_1_MUX25_Msk                   (0x3UL<<EPWM_HXB11_1_MUX25_Pos)                  /*!< 0x000C0000 */
#define EPWM_HXB11_1_MUX25                       EPWM_HXB11_1_MUX25_Msk                           /*!< eallow, HXBLOCK */
#define EPWM_HXB11_1_MUX25_0                     (0x1UL<<EPWM_HXB11_1_MUX25_Pos)                  /*!< 0x00040000 */
#define EPWM_HXB11_1_MUX25_1                     (0x2UL<<EPWM_HXB11_1_MUX25_Pos)                  /*!< 0x00080000 */
#define EPWM_HXB11_1_MUX26_Pos                   (20U)
#define EPWM_HXB11_1_MUX26_Msk                   (0x3UL<<EPWM_HXB11_1_MUX26_Pos)                  /*!< 0x00300000 */
#define EPWM_HXB11_1_MUX26                       EPWM_HXB11_1_MUX26_Msk                           /*!< eallow, HXBLOCK */
#define EPWM_HXB11_1_MUX26_0                     (0x1UL<<EPWM_HXB11_1_MUX26_Pos)                  /*!< 0x00100000 */
#define EPWM_HXB11_1_MUX26_1                     (0x2UL<<EPWM_HXB11_1_MUX26_Pos)                  /*!< 0x00200000 */
#define EPWM_HXB11_1_MUX27_Pos                   (22U)
#define EPWM_HXB11_1_MUX27_Msk                   (0x3UL<<EPWM_HXB11_1_MUX27_Pos)                  /*!< 0x00C00000 */
#define EPWM_HXB11_1_MUX27                       EPWM_HXB11_1_MUX27_Msk                           /*!< eallow, HXBLOCK */
#define EPWM_HXB11_1_MUX27_0                     (0x1UL<<EPWM_HXB11_1_MUX27_Pos)                  /*!< 0x00400000 */
#define EPWM_HXB11_1_MUX27_1                     (0x2UL<<EPWM_HXB11_1_MUX27_Pos)                  /*!< 0x00800000 */
#define EPWM_HXB11_1_MUX28_Pos                   (24U)
#define EPWM_HXB11_1_MUX28_Msk                   (0x3UL<<EPWM_HXB11_1_MUX28_Pos)                  /*!< 0x03000000 */
#define EPWM_HXB11_1_MUX28                       EPWM_HXB11_1_MUX28_Msk                           /*!< eallow, HXBLOCK */
#define EPWM_HXB11_1_MUX28_0                     (0x1UL<<EPWM_HXB11_1_MUX28_Pos)                  /*!< 0x01000000 */
#define EPWM_HXB11_1_MUX28_1                     (0x2UL<<EPWM_HXB11_1_MUX28_Pos)                  /*!< 0x02000000 */
#define EPWM_HXB11_1_MUX29_Pos                   (26U)
#define EPWM_HXB11_1_MUX29_Msk                   (0x3UL<<EPWM_HXB11_1_MUX29_Pos)                  /*!< 0x0C000000 */
#define EPWM_HXB11_1_MUX29                       EPWM_HXB11_1_MUX29_Msk                           /*!< eallow, HXBLOCK */
#define EPWM_HXB11_1_MUX29_0                     (0x1UL<<EPWM_HXB11_1_MUX29_Pos)                  /*!< 0x04000000 */
#define EPWM_HXB11_1_MUX29_1                     (0x2UL<<EPWM_HXB11_1_MUX29_Pos)                  /*!< 0x08000000 */
#define EPWM_HXB11_1_MUX30_Pos                   (28U)
#define EPWM_HXB11_1_MUX30_Msk                   (0x3UL<<EPWM_HXB11_1_MUX30_Pos)                  /*!< 0x30000000 */
#define EPWM_HXB11_1_MUX30                       EPWM_HXB11_1_MUX30_Msk                           /*!< eallow, HXBLOCK */
#define EPWM_HXB11_1_MUX30_0                     (0x1UL<<EPWM_HXB11_1_MUX30_Pos)                  /*!< 0x10000000 */
#define EPWM_HXB11_1_MUX30_1                     (0x2UL<<EPWM_HXB11_1_MUX30_Pos)                  /*!< 0x20000000 */
#define EPWM_HXB11_1_MUX31_Pos                   (30U)
#define EPWM_HXB11_1_MUX31_Msk                   (0x3UL<<EPWM_HXB11_1_MUX31_Pos)                  /*!< 0xC0000000 */
#define EPWM_HXB11_1_MUX31                       EPWM_HXB11_1_MUX31_Msk                           /*!< eallow, HXBLOCK */
#define EPWM_HXB11_1_MUX31_0                     (0x1UL<<EPWM_HXB11_1_MUX31_Pos)                  /*!< 0x40000000 */
#define EPWM_HXB11_1_MUX31_1                     (0x2UL<<EPWM_HXB11_1_MUX31_Pos)                  /*!< 0x80000000 */

/********************************* Bit definition for EPWM_HXB12_0 register ****************************************/
#define EPWM_HXB12_0_MUX0_Pos                    (0U)
#define EPWM_HXB12_0_MUX0_Msk                    (0x3UL<<EPWM_HXB12_0_MUX0_Pos)                   /*!< 0x00000003 */
#define EPWM_HXB12_0_MUX0                        EPWM_HXB12_0_MUX0_Msk                            /*!< eallow, HXBLOCK */
#define EPWM_HXB12_0_MUX0_0                      (0x1UL<<EPWM_HXB12_0_MUX0_Pos)                   /*!< 0x00000001 */
#define EPWM_HXB12_0_MUX0_1                      (0x2UL<<EPWM_HXB12_0_MUX0_Pos)                   /*!< 0x00000002 */
#define EPWM_HXB12_0_MUX1_Pos                    (2U)
#define EPWM_HXB12_0_MUX1_Msk                    (0x3UL<<EPWM_HXB12_0_MUX1_Pos)                   /*!< 0x0000000C */
#define EPWM_HXB12_0_MUX1                        EPWM_HXB12_0_MUX1_Msk                            /*!< eallow, HXBLOCK */
#define EPWM_HXB12_0_MUX1_0                      (0x1UL<<EPWM_HXB12_0_MUX1_Pos)                   /*!< 0x00000004 */
#define EPWM_HXB12_0_MUX1_1                      (0x2UL<<EPWM_HXB12_0_MUX1_Pos)                   /*!< 0x00000008 */
#define EPWM_HXB12_0_MUX2_Pos                    (4U)
#define EPWM_HXB12_0_MUX2_Msk                    (0x3UL<<EPWM_HXB12_0_MUX2_Pos)                   /*!< 0x00000030 */
#define EPWM_HXB12_0_MUX2                        EPWM_HXB12_0_MUX2_Msk                            /*!< eallow, HXBLOCK */
#define EPWM_HXB12_0_MUX2_0                      (0x1UL<<EPWM_HXB12_0_MUX2_Pos)                   /*!< 0x00000010 */
#define EPWM_HXB12_0_MUX2_1                      (0x2UL<<EPWM_HXB12_0_MUX2_Pos)                   /*!< 0x00000020 */
#define EPWM_HXB12_0_MUX3_Pos                    (6U)
#define EPWM_HXB12_0_MUX3_Msk                    (0x3UL<<EPWM_HXB12_0_MUX3_Pos)                   /*!< 0x000000C0 */
#define EPWM_HXB12_0_MUX3                        EPWM_HXB12_0_MUX3_Msk                            /*!< eallow, HXBLOCK */
#define EPWM_HXB12_0_MUX3_0                      (0x1UL<<EPWM_HXB12_0_MUX3_Pos)                   /*!< 0x00000040 */
#define EPWM_HXB12_0_MUX3_1                      (0x2UL<<EPWM_HXB12_0_MUX3_Pos)                   /*!< 0x00000080 */
#define EPWM_HXB12_0_MUX4_Pos                    (8U)
#define EPWM_HXB12_0_MUX4_Msk                    (0x3UL<<EPWM_HXB12_0_MUX4_Pos)                   /*!< 0x00000300 */
#define EPWM_HXB12_0_MUX4                        EPWM_HXB12_0_MUX4_Msk                            /*!< eallow, HXBLOCK */
#define EPWM_HXB12_0_MUX4_0                      (0x1UL<<EPWM_HXB12_0_MUX4_Pos)                   /*!< 0x00000100 */
#define EPWM_HXB12_0_MUX4_1                      (0x2UL<<EPWM_HXB12_0_MUX4_Pos)                   /*!< 0x00000200 */
#define EPWM_HXB12_0_MUX5_Pos                    (10U)
#define EPWM_HXB12_0_MUX5_Msk                    (0x3UL<<EPWM_HXB12_0_MUX5_Pos)                   /*!< 0x00000C00 */
#define EPWM_HXB12_0_MUX5                        EPWM_HXB12_0_MUX5_Msk                            /*!< eallow, HXBLOCK */
#define EPWM_HXB12_0_MUX5_0                      (0x1UL<<EPWM_HXB12_0_MUX5_Pos)                   /*!< 0x00000400 */
#define EPWM_HXB12_0_MUX5_1                      (0x2UL<<EPWM_HXB12_0_MUX5_Pos)                   /*!< 0x00000800 */
#define EPWM_HXB12_0_MUX6_Pos                    (12U)
#define EPWM_HXB12_0_MUX6_Msk                    (0x3UL<<EPWM_HXB12_0_MUX6_Pos)                   /*!< 0x00003000 */
#define EPWM_HXB12_0_MUX6                        EPWM_HXB12_0_MUX6_Msk                            /*!< eallow, HXBLOCK */
#define EPWM_HXB12_0_MUX6_0                      (0x1UL<<EPWM_HXB12_0_MUX6_Pos)                   /*!< 0x00001000 */
#define EPWM_HXB12_0_MUX6_1                      (0x2UL<<EPWM_HXB12_0_MUX6_Pos)                   /*!< 0x00002000 */
#define EPWM_HXB12_0_MUX7_Pos                    (14U)
#define EPWM_HXB12_0_MUX7_Msk                    (0x3UL<<EPWM_HXB12_0_MUX7_Pos)                   /*!< 0x0000C000 */
#define EPWM_HXB12_0_MUX7                        EPWM_HXB12_0_MUX7_Msk                            /*!< eallow, HXBLOCK */
#define EPWM_HXB12_0_MUX7_0                      (0x1UL<<EPWM_HXB12_0_MUX7_Pos)                   /*!< 0x00004000 */
#define EPWM_HXB12_0_MUX7_1                      (0x2UL<<EPWM_HXB12_0_MUX7_Pos)                   /*!< 0x00008000 */
#define EPWM_HXB12_0_MUX8_Pos                    (16U)
#define EPWM_HXB12_0_MUX8_Msk                    (0x3UL<<EPWM_HXB12_0_MUX8_Pos)                   /*!< 0x00030000 */
#define EPWM_HXB12_0_MUX8                        EPWM_HXB12_0_MUX8_Msk                            /*!< eallow, HXBLOCK */
#define EPWM_HXB12_0_MUX8_0                      (0x1UL<<EPWM_HXB12_0_MUX8_Pos)                   /*!< 0x00010000 */
#define EPWM_HXB12_0_MUX8_1                      (0x2UL<<EPWM_HXB12_0_MUX8_Pos)                   /*!< 0x00020000 */
#define EPWM_HXB12_0_MUX9_Pos                    (18U)
#define EPWM_HXB12_0_MUX9_Msk                    (0x3UL<<EPWM_HXB12_0_MUX9_Pos)                   /*!< 0x000C0000 */
#define EPWM_HXB12_0_MUX9                        EPWM_HXB12_0_MUX9_Msk                            /*!< eallow, HXBLOCK */
#define EPWM_HXB12_0_MUX9_0                      (0x1UL<<EPWM_HXB12_0_MUX9_Pos)                   /*!< 0x00040000 */
#define EPWM_HXB12_0_MUX9_1                      (0x2UL<<EPWM_HXB12_0_MUX9_Pos)                   /*!< 0x00080000 */
#define EPWM_HXB12_0_MUX10_Pos                   (20U)
#define EPWM_HXB12_0_MUX10_Msk                   (0x3UL<<EPWM_HXB12_0_MUX10_Pos)                  /*!< 0x00300000 */
#define EPWM_HXB12_0_MUX10                       EPWM_HXB12_0_MUX10_Msk                           /*!< eallow, HXBLOCK */
#define EPWM_HXB12_0_MUX10_0                     (0x1UL<<EPWM_HXB12_0_MUX10_Pos)                  /*!< 0x00100000 */
#define EPWM_HXB12_0_MUX10_1                     (0x2UL<<EPWM_HXB12_0_MUX10_Pos)                  /*!< 0x00200000 */
#define EPWM_HXB12_0_MUX11_Pos                   (22U)
#define EPWM_HXB12_0_MUX11_Msk                   (0x3UL<<EPWM_HXB12_0_MUX11_Pos)                  /*!< 0x00C00000 */
#define EPWM_HXB12_0_MUX11                       EPWM_HXB12_0_MUX11_Msk                           /*!< eallow, HXBLOCK */
#define EPWM_HXB12_0_MUX11_0                     (0x1UL<<EPWM_HXB12_0_MUX11_Pos)                  /*!< 0x00400000 */
#define EPWM_HXB12_0_MUX11_1                     (0x2UL<<EPWM_HXB12_0_MUX11_Pos)                  /*!< 0x00800000 */
#define EPWM_HXB12_0_MUX12_Pos                   (24U)
#define EPWM_HXB12_0_MUX12_Msk                   (0x3UL<<EPWM_HXB12_0_MUX12_Pos)                  /*!< 0x03000000 */
#define EPWM_HXB12_0_MUX12                       EPWM_HXB12_0_MUX12_Msk                           /*!< eallow, HXBLOCK */
#define EPWM_HXB12_0_MUX12_0                     (0x1UL<<EPWM_HXB12_0_MUX12_Pos)                  /*!< 0x01000000 */
#define EPWM_HXB12_0_MUX12_1                     (0x2UL<<EPWM_HXB12_0_MUX12_Pos)                  /*!< 0x02000000 */
#define EPWM_HXB12_0_MUX13_Pos                   (26U)
#define EPWM_HXB12_0_MUX13_Msk                   (0x3UL<<EPWM_HXB12_0_MUX13_Pos)                  /*!< 0x0C000000 */
#define EPWM_HXB12_0_MUX13                       EPWM_HXB12_0_MUX13_Msk                           /*!< eallow, HXBLOCK */
#define EPWM_HXB12_0_MUX13_0                     (0x1UL<<EPWM_HXB12_0_MUX13_Pos)                  /*!< 0x04000000 */
#define EPWM_HXB12_0_MUX13_1                     (0x2UL<<EPWM_HXB12_0_MUX13_Pos)                  /*!< 0x08000000 */
#define EPWM_HXB12_0_MUX14_Pos                   (28U)
#define EPWM_HXB12_0_MUX14_Msk                   (0x3UL<<EPWM_HXB12_0_MUX14_Pos)                  /*!< 0x30000000 */
#define EPWM_HXB12_0_MUX14                       EPWM_HXB12_0_MUX14_Msk                           /*!< eallow, HXBLOCK */
#define EPWM_HXB12_0_MUX14_0                     (0x1UL<<EPWM_HXB12_0_MUX14_Pos)                  /*!< 0x10000000 */
#define EPWM_HXB12_0_MUX14_1                     (0x2UL<<EPWM_HXB12_0_MUX14_Pos)                  /*!< 0x20000000 */
#define EPWM_HXB12_0_MUX15_Pos                   (30U)
#define EPWM_HXB12_0_MUX15_Msk                   (0x3UL<<EPWM_HXB12_0_MUX15_Pos)                  /*!< 0xC0000000 */
#define EPWM_HXB12_0_MUX15                       EPWM_HXB12_0_MUX15_Msk                           /*!< eallow, HXBLOCK */
#define EPWM_HXB12_0_MUX15_0                     (0x1UL<<EPWM_HXB12_0_MUX15_Pos)                  /*!< 0x40000000 */
#define EPWM_HXB12_0_MUX15_1                     (0x2UL<<EPWM_HXB12_0_MUX15_Pos)                  /*!< 0x80000000 */

/********************************* Bit definition for EPWM_HXB12_1 register ****************************************/
#define EPWM_HXB12_1_MUX16_Pos                   (0U)
#define EPWM_HXB12_1_MUX16_Msk                   (0x3UL<<EPWM_HXB12_1_MUX16_Pos)                  /*!< 0x00000003 */
#define EPWM_HXB12_1_MUX16                       EPWM_HXB12_1_MUX16_Msk                           /*!< eallow, HXBLOCK */
#define EPWM_HXB12_1_MUX16_0                     (0x1UL<<EPWM_HXB12_1_MUX16_Pos)                  /*!< 0x00000001 */
#define EPWM_HXB12_1_MUX16_1                     (0x2UL<<EPWM_HXB12_1_MUX16_Pos)                  /*!< 0x00000002 */
#define EPWM_HXB12_1_MUX17_Pos                   (2U)
#define EPWM_HXB12_1_MUX17_Msk                   (0x3UL<<EPWM_HXB12_1_MUX17_Pos)                  /*!< 0x0000000C */
#define EPWM_HXB12_1_MUX17                       EPWM_HXB12_1_MUX17_Msk                           /*!< eallow, HXBLOCK */
#define EPWM_HXB12_1_MUX17_0                     (0x1UL<<EPWM_HXB12_1_MUX17_Pos)                  /*!< 0x00000004 */
#define EPWM_HXB12_1_MUX17_1                     (0x2UL<<EPWM_HXB12_1_MUX17_Pos)                  /*!< 0x00000008 */
#define EPWM_HXB12_1_MUX18_Pos                   (4U)
#define EPWM_HXB12_1_MUX18_Msk                   (0x3UL<<EPWM_HXB12_1_MUX18_Pos)                  /*!< 0x00000030 */
#define EPWM_HXB12_1_MUX18                       EPWM_HXB12_1_MUX18_Msk                           /*!< eallow, HXBLOCK */
#define EPWM_HXB12_1_MUX18_0                     (0x1UL<<EPWM_HXB12_1_MUX18_Pos)                  /*!< 0x00000010 */
#define EPWM_HXB12_1_MUX18_1                     (0x2UL<<EPWM_HXB12_1_MUX18_Pos)                  /*!< 0x00000020 */
#define EPWM_HXB12_1_MUX19_Pos                   (6U)
#define EPWM_HXB12_1_MUX19_Msk                   (0x3UL<<EPWM_HXB12_1_MUX19_Pos)                  /*!< 0x000000C0 */
#define EPWM_HXB12_1_MUX19                       EPWM_HXB12_1_MUX19_Msk                           /*!< eallow, HXBLOCK */
#define EPWM_HXB12_1_MUX19_0                     (0x1UL<<EPWM_HXB12_1_MUX19_Pos)                  /*!< 0x00000040 */
#define EPWM_HXB12_1_MUX19_1                     (0x2UL<<EPWM_HXB12_1_MUX19_Pos)                  /*!< 0x00000080 */
#define EPWM_HXB12_1_MUX20_Pos                   (8U)
#define EPWM_HXB12_1_MUX20_Msk                   (0x3UL<<EPWM_HXB12_1_MUX20_Pos)                  /*!< 0x00000300 */
#define EPWM_HXB12_1_MUX20                       EPWM_HXB12_1_MUX20_Msk                           /*!< eallow, HXBLOCK */
#define EPWM_HXB12_1_MUX20_0                     (0x1UL<<EPWM_HXB12_1_MUX20_Pos)                  /*!< 0x00000100 */
#define EPWM_HXB12_1_MUX20_1                     (0x2UL<<EPWM_HXB12_1_MUX20_Pos)                  /*!< 0x00000200 */
#define EPWM_HXB12_1_MUX21_Pos                   (10U)
#define EPWM_HXB12_1_MUX21_Msk                   (0x3UL<<EPWM_HXB12_1_MUX21_Pos)                  /*!< 0x00000C00 */
#define EPWM_HXB12_1_MUX21                       EPWM_HXB12_1_MUX21_Msk                           /*!< eallow, HXBLOCK */
#define EPWM_HXB12_1_MUX21_0                     (0x1UL<<EPWM_HXB12_1_MUX21_Pos)                  /*!< 0x00000400 */
#define EPWM_HXB12_1_MUX21_1                     (0x2UL<<EPWM_HXB12_1_MUX21_Pos)                  /*!< 0x00000800 */
#define EPWM_HXB12_1_MUX22_Pos                   (12U)
#define EPWM_HXB12_1_MUX22_Msk                   (0x3UL<<EPWM_HXB12_1_MUX22_Pos)                  /*!< 0x00003000 */
#define EPWM_HXB12_1_MUX22                       EPWM_HXB12_1_MUX22_Msk                           /*!< eallow, HXBLOCK */
#define EPWM_HXB12_1_MUX22_0                     (0x1UL<<EPWM_HXB12_1_MUX22_Pos)                  /*!< 0x00001000 */
#define EPWM_HXB12_1_MUX22_1                     (0x2UL<<EPWM_HXB12_1_MUX22_Pos)                  /*!< 0x00002000 */
#define EPWM_HXB12_1_MUX23_Pos                   (14U)
#define EPWM_HXB12_1_MUX23_Msk                   (0x3UL<<EPWM_HXB12_1_MUX23_Pos)                  /*!< 0x0000C000 */
#define EPWM_HXB12_1_MUX23                       EPWM_HXB12_1_MUX23_Msk                           /*!< eallow, HXBLOCK */
#define EPWM_HXB12_1_MUX23_0                     (0x1UL<<EPWM_HXB12_1_MUX23_Pos)                  /*!< 0x00004000 */
#define EPWM_HXB12_1_MUX23_1                     (0x2UL<<EPWM_HXB12_1_MUX23_Pos)                  /*!< 0x00008000 */
#define EPWM_HXB12_1_MUX24_Pos                   (16U)
#define EPWM_HXB12_1_MUX24_Msk                   (0x3UL<<EPWM_HXB12_1_MUX24_Pos)                  /*!< 0x00030000 */
#define EPWM_HXB12_1_MUX24                       EPWM_HXB12_1_MUX24_Msk                           /*!< eallow, HXBLOCK */
#define EPWM_HXB12_1_MUX24_0                     (0x1UL<<EPWM_HXB12_1_MUX24_Pos)                  /*!< 0x00010000 */
#define EPWM_HXB12_1_MUX24_1                     (0x2UL<<EPWM_HXB12_1_MUX24_Pos)                  /*!< 0x00020000 */
#define EPWM_HXB12_1_MUX25_Pos                   (18U)
#define EPWM_HXB12_1_MUX25_Msk                   (0x3UL<<EPWM_HXB12_1_MUX25_Pos)                  /*!< 0x000C0000 */
#define EPWM_HXB12_1_MUX25                       EPWM_HXB12_1_MUX25_Msk                           /*!< eallow, HXBLOCK */
#define EPWM_HXB12_1_MUX25_0                     (0x1UL<<EPWM_HXB12_1_MUX25_Pos)                  /*!< 0x00040000 */
#define EPWM_HXB12_1_MUX25_1                     (0x2UL<<EPWM_HXB12_1_MUX25_Pos)                  /*!< 0x00080000 */
#define EPWM_HXB12_1_MUX26_Pos                   (20U)
#define EPWM_HXB12_1_MUX26_Msk                   (0x3UL<<EPWM_HXB12_1_MUX26_Pos)                  /*!< 0x00300000 */
#define EPWM_HXB12_1_MUX26                       EPWM_HXB12_1_MUX26_Msk                           /*!< eallow, HXBLOCK */
#define EPWM_HXB12_1_MUX26_0                     (0x1UL<<EPWM_HXB12_1_MUX26_Pos)                  /*!< 0x00100000 */
#define EPWM_HXB12_1_MUX26_1                     (0x2UL<<EPWM_HXB12_1_MUX26_Pos)                  /*!< 0x00200000 */
#define EPWM_HXB12_1_MUX27_Pos                   (22U)
#define EPWM_HXB12_1_MUX27_Msk                   (0x3UL<<EPWM_HXB12_1_MUX27_Pos)                  /*!< 0x00C00000 */
#define EPWM_HXB12_1_MUX27                       EPWM_HXB12_1_MUX27_Msk                           /*!< eallow, HXBLOCK */
#define EPWM_HXB12_1_MUX27_0                     (0x1UL<<EPWM_HXB12_1_MUX27_Pos)                  /*!< 0x00400000 */
#define EPWM_HXB12_1_MUX27_1                     (0x2UL<<EPWM_HXB12_1_MUX27_Pos)                  /*!< 0x00800000 */
#define EPWM_HXB12_1_MUX28_Pos                   (24U)
#define EPWM_HXB12_1_MUX28_Msk                   (0x3UL<<EPWM_HXB12_1_MUX28_Pos)                  /*!< 0x03000000 */
#define EPWM_HXB12_1_MUX28                       EPWM_HXB12_1_MUX28_Msk                           /*!< eallow, HXBLOCK */
#define EPWM_HXB12_1_MUX28_0                     (0x1UL<<EPWM_HXB12_1_MUX28_Pos)                  /*!< 0x01000000 */
#define EPWM_HXB12_1_MUX28_1                     (0x2UL<<EPWM_HXB12_1_MUX28_Pos)                  /*!< 0x02000000 */
#define EPWM_HXB12_1_MUX29_Pos                   (26U)
#define EPWM_HXB12_1_MUX29_Msk                   (0x3UL<<EPWM_HXB12_1_MUX29_Pos)                  /*!< 0x0C000000 */
#define EPWM_HXB12_1_MUX29                       EPWM_HXB12_1_MUX29_Msk                           /*!< eallow, HXBLOCK */
#define EPWM_HXB12_1_MUX29_0                     (0x1UL<<EPWM_HXB12_1_MUX29_Pos)                  /*!< 0x04000000 */
#define EPWM_HXB12_1_MUX29_1                     (0x2UL<<EPWM_HXB12_1_MUX29_Pos)                  /*!< 0x08000000 */
#define EPWM_HXB12_1_MUX30_Pos                   (28U)
#define EPWM_HXB12_1_MUX30_Msk                   (0x3UL<<EPWM_HXB12_1_MUX30_Pos)                  /*!< 0x30000000 */
#define EPWM_HXB12_1_MUX30                       EPWM_HXB12_1_MUX30_Msk                           /*!< eallow, HXBLOCK */
#define EPWM_HXB12_1_MUX30_0                     (0x1UL<<EPWM_HXB12_1_MUX30_Pos)                  /*!< 0x10000000 */
#define EPWM_HXB12_1_MUX30_1                     (0x2UL<<EPWM_HXB12_1_MUX30_Pos)                  /*!< 0x20000000 */
#define EPWM_HXB12_1_MUX31_Pos                   (30U)
#define EPWM_HXB12_1_MUX31_Msk                   (0x3UL<<EPWM_HXB12_1_MUX31_Pos)                  /*!< 0xC0000000 */
#define EPWM_HXB12_1_MUX31                       EPWM_HXB12_1_MUX31_Msk                           /*!< eallow, HXBLOCK */
#define EPWM_HXB12_1_MUX31_0                     (0x1UL<<EPWM_HXB12_1_MUX31_Pos)                  /*!< 0x40000000 */
#define EPWM_HXB12_1_MUX31_1                     (0x2UL<<EPWM_HXB12_1_MUX31_Pos)                  /*!< 0x80000000 */

/********************************* Bit definition for EPWM_HXB4_MUX register ***************************************/
#define EPWM_HXB4_MUX_MUXEN_Pos                  (0U)
#define EPWM_HXB4_MUX_MUXEN_Msk                  (0xFFFFFFFFUL<<EPWM_HXB4_MUX_MUXEN_Pos)          /*!< 0xFFFFFFFF */
#define EPWM_HXB4_MUX_MUXEN                      EPWM_HXB4_MUX_MUXEN_Msk                          /*!< eallow, HXBLOCK */

/********************************* Bit definition for EPWM_HXB5_MUX register ***************************************/
#define EPWM_HXB5_MUX_MUXEN_Pos                  (0U)
#define EPWM_HXB5_MUX_MUXEN_Msk                  (0xFFFFFFFFUL<<EPWM_HXB5_MUX_MUXEN_Pos)          /*!< 0xFFFFFFFF */
#define EPWM_HXB5_MUX_MUXEN                      EPWM_HXB5_MUX_MUXEN_Msk                          /*!< eallow, HXBLOCK */

/********************************* Bit definition for EPWM_HXB7_MUX register ***************************************/
#define EPWM_HXB7_MUX_MUXEN_Pos                  (0U)
#define EPWM_HXB7_MUX_MUXEN_Msk                  (0xFFFFFFFFUL<<EPWM_HXB7_MUX_MUXEN_Pos)          /*!< 0xFFFFFFFF */
#define EPWM_HXB7_MUX_MUXEN                      EPWM_HXB7_MUX_MUXEN_Msk                          /*!< eallow, HXBLOCK */

/********************************* Bit definition for EPWM_HXB8_MUX register ***************************************/
#define EPWM_HXB8_MUX_MUXEN_Pos                  (0U)
#define EPWM_HXB8_MUX_MUXEN_Msk                  (0xFFFFFFFFUL<<EPWM_HXB8_MUX_MUXEN_Pos)          /*!< 0xFFFFFFFF */
#define EPWM_HXB8_MUX_MUXEN                      EPWM_HXB8_MUX_MUXEN_Msk                          /*!< eallow, HXBLOCK */

/********************************* Bit definition for EPWM_HXB9_MUX register ***************************************/
#define EPWM_HXB9_MUX_MUXEN_Pos                  (0U)
#define EPWM_HXB9_MUX_MUXEN_Msk                  (0xFFFFFFFFUL<<EPWM_HXB9_MUX_MUXEN_Pos)          /*!< 0xFFFFFFFF */
#define EPWM_HXB9_MUX_MUXEN                      EPWM_HXB9_MUX_MUXEN_Msk                          /*!< eallow, HXBLOCK */

/********************************* Bit definition for EPWM_HXB10_MUX register **************************************/
#define EPWM_HXB10_MUX_MUXEN_Pos                 (0U)
#define EPWM_HXB10_MUX_MUXEN_Msk                 (0xFFFFFFFFUL<<EPWM_HXB10_MUX_MUXEN_Pos)         /*!< 0xFFFFFFFF */
#define EPWM_HXB10_MUX_MUXEN                     EPWM_HXB10_MUX_MUXEN_Msk                         /*!< eallow, HXBLOCK */

/********************************* Bit definition for EPWM_HXB11_MUX register **************************************/
#define EPWM_HXB11_MUX_MUXEN_Pos                 (0U)
#define EPWM_HXB11_MUX_MUXEN_Msk                 (0xFFFFFFFFUL<<EPWM_HXB11_MUX_MUXEN_Pos)         /*!< 0xFFFFFFFF */
#define EPWM_HXB11_MUX_MUXEN                     EPWM_HXB11_MUX_MUXEN_Msk                         /*!< eallow, HXBLOCK */

/********************************* Bit definition for EPWM_HXB12_MUX register **************************************/
#define EPWM_HXB12_MUX_MUXEN_Pos                 (0U)
#define EPWM_HXB12_MUX_MUXEN_Msk                 (0xFFFFFFFFUL<<EPWM_HXB12_MUX_MUXEN_Pos)         /*!< 0xFFFFFFFF */
#define EPWM_HXB12_MUX_MUXEN                     EPWM_HXB12_MUX_MUXEN_Msk                         /*!< eallow, HXBLOCK */

/********************************* Bit definition for EPWM_HXB_POL register ****************************************/
#define EPWM_HXB_POL_HXB4P_Pos                   (0U)
#define EPWM_HXB_POL_HXB4P_Msk                   (0x1UL<<EPWM_HXB_POL_HXB4P_Pos)                  /*!< 0x00000001 */
#define EPWM_HXB_POL_HXB4P                       EPWM_HXB_POL_HXB4P_Msk                           /*!< eallow, HXBLOCK */
#define EPWM_HXB_POL_HXB5P_Pos                   (1U)
#define EPWM_HXB_POL_HXB5P_Msk                   (0x1UL<<EPWM_HXB_POL_HXB5P_Pos)                  /*!< 0x00000002 */
#define EPWM_HXB_POL_HXB5P                       EPWM_HXB_POL_HXB5P_Msk                           /*!< eallow, HXBLOCK */
#define EPWM_HXB_POL_HXB7P_Pos                   (2U)
#define EPWM_HXB_POL_HXB7P_Msk                   (0x1UL<<EPWM_HXB_POL_HXB7P_Pos)                  /*!< 0x00000004 */
#define EPWM_HXB_POL_HXB7P                       EPWM_HXB_POL_HXB7P_Msk                           /*!< eallow, HXBLOCK */
#define EPWM_HXB_POL_HXB8P_Pos                   (3U)
#define EPWM_HXB_POL_HXB8P_Msk                   (0x1UL<<EPWM_HXB_POL_HXB8P_Pos)                  /*!< 0x00000008 */
#define EPWM_HXB_POL_HXB8P                       EPWM_HXB_POL_HXB8P_Msk                           /*!< eallow, HXBLOCK */
#define EPWM_HXB_POL_HXB9P_Pos                   (4U)
#define EPWM_HXB_POL_HXB9P_Msk                   (0x1UL<<EPWM_HXB_POL_HXB9P_Pos)                  /*!< 0x00000010 */
#define EPWM_HXB_POL_HXB9P                       EPWM_HXB_POL_HXB9P_Msk                           /*!< eallow, HXBLOCK */
#define EPWM_HXB_POL_HXB10P_Pos                  (5U)
#define EPWM_HXB_POL_HXB10P_Msk                  (0x1UL<<EPWM_HXB_POL_HXB10P_Pos)                 /*!< 0x00000020 */
#define EPWM_HXB_POL_HXB10P                      EPWM_HXB_POL_HXB10P_Msk                          /*!< eallow, HXBLOCK */
#define EPWM_HXB_POL_HXB11P_Pos                  (6U)
#define EPWM_HXB_POL_HXB11P_Msk                  (0x1UL<<EPWM_HXB_POL_HXB11P_Pos)                 /*!< 0x00000040 */
#define EPWM_HXB_POL_HXB11P                      EPWM_HXB_POL_HXB11P_Msk                          /*!< eallow, HXBLOCK */
#define EPWM_HXB_POL_HXB12P_Pos                  (7U)
#define EPWM_HXB_POL_HXB12P_Msk                  (0x1UL<<EPWM_HXB_POL_HXB12P_Pos)                 /*!< 0x00000080 */
#define EPWM_HXB_POL_HXB12P                      EPWM_HXB_POL_HXB12P_Msk                          /*!< eallow, HXBLOCK */

/********************************* Bit definition for EPWM_HXB_LOCK register ***************************************/
#define EPWM_HXB_LOCK_HXBLOCK_Pos                (0U)
#define EPWM_HXB_LOCK_HXBLOCK_Msk                (0x1UL<<EPWM_HXB_LOCK_HXBLOCK_Pos)               /*!< 0x00000001 */
#define EPWM_HXB_LOCK_HXBLOCK                    EPWM_HXB_LOCK_HXBLOCK_Msk                        /*!< eallow */
#define EPWM_HXB_LOCK_KEY_Pos                    (16U)
#define EPWM_HXB_LOCK_KEY_Msk                    (0xFFFFUL<<EPWM_HXB_LOCK_KEY_Pos)                /*!< 0xFFFF0000 */
#define EPWM_HXB_LOCK_KEY                        EPWM_HXB_LOCK_KEY_Msk                            /*!< eallow */

/********************************* Bit definition for EPWM_SYNCI_SEL1_4 register ***********************************/
#define EPWM_SYNCI_SEL1_4_SYNCISEL1_Pos          (0U)
#define EPWM_SYNCI_SEL1_4_SYNCISEL1_Msk          (0x1FUL<<EPWM_SYNCI_SEL1_4_SYNCISEL1_Pos)        /*!< 0x0000001F */
#define EPWM_SYNCI_SEL1_4_SYNCISEL1              EPWM_SYNCI_SEL1_4_SYNCISEL1_Msk                  /*!< eallow, SYNCILOCK */
#define EPWM_SYNCI_SEL1_4_SYNCISEL1_0            (0x1UL<<EPWM_SYNCI_SEL1_4_SYNCISEL1_Pos)         /*!< 0x00000001 */
#define EPWM_SYNCI_SEL1_4_SYNCISEL1_1            (0x2UL<<EPWM_SYNCI_SEL1_4_SYNCISEL1_Pos)         /*!< 0x00000002 */
#define EPWM_SYNCI_SEL1_4_SYNCISEL1_2            (0x4UL<<EPWM_SYNCI_SEL1_4_SYNCISEL1_Pos)         /*!< 0x00000004 */
#define EPWM_SYNCI_SEL1_4_SYNCISEL1_3            (0x8UL<<EPWM_SYNCI_SEL1_4_SYNCISEL1_Pos)         /*!< 0x00000008 */
#define EPWM_SYNCI_SEL1_4_SYNCISEL1_4            (0x10UL<<EPWM_SYNCI_SEL1_4_SYNCISEL1_Pos)        /*!< 0x00000010 */
#define EPWM_SYNCI_SEL1_4_SYNCISEL2_Pos          (8U)
#define EPWM_SYNCI_SEL1_4_SYNCISEL2_Msk          (0x1FUL<<EPWM_SYNCI_SEL1_4_SYNCISEL2_Pos)        /*!< 0x00001F00 */
#define EPWM_SYNCI_SEL1_4_SYNCISEL2              EPWM_SYNCI_SEL1_4_SYNCISEL2_Msk                  /*!< eallow, SYNCILOCK */
#define EPWM_SYNCI_SEL1_4_SYNCISEL2_0            (0x1UL<<EPWM_SYNCI_SEL1_4_SYNCISEL2_Pos)         /*!< 0x00000100 */
#define EPWM_SYNCI_SEL1_4_SYNCISEL2_1            (0x2UL<<EPWM_SYNCI_SEL1_4_SYNCISEL2_Pos)         /*!< 0x00000200 */
#define EPWM_SYNCI_SEL1_4_SYNCISEL2_2            (0x4UL<<EPWM_SYNCI_SEL1_4_SYNCISEL2_Pos)         /*!< 0x00000400 */
#define EPWM_SYNCI_SEL1_4_SYNCISEL2_3            (0x8UL<<EPWM_SYNCI_SEL1_4_SYNCISEL2_Pos)         /*!< 0x00000800 */
#define EPWM_SYNCI_SEL1_4_SYNCISEL2_4            (0x10UL<<EPWM_SYNCI_SEL1_4_SYNCISEL2_Pos)        /*!< 0x00001000 */
#define EPWM_SYNCI_SEL1_4_SYNCISEL3_Pos          (16U)
#define EPWM_SYNCI_SEL1_4_SYNCISEL3_Msk          (0x1FUL<<EPWM_SYNCI_SEL1_4_SYNCISEL3_Pos)        /*!< 0x001F0000 */
#define EPWM_SYNCI_SEL1_4_SYNCISEL3              EPWM_SYNCI_SEL1_4_SYNCISEL3_Msk                  /*!< eallow, SYNCILOCK */
#define EPWM_SYNCI_SEL1_4_SYNCISEL3_0            (0x1UL<<EPWM_SYNCI_SEL1_4_SYNCISEL3_Pos)         /*!< 0x00010000 */
#define EPWM_SYNCI_SEL1_4_SYNCISEL3_1            (0x2UL<<EPWM_SYNCI_SEL1_4_SYNCISEL3_Pos)         /*!< 0x00020000 */
#define EPWM_SYNCI_SEL1_4_SYNCISEL3_2            (0x4UL<<EPWM_SYNCI_SEL1_4_SYNCISEL3_Pos)         /*!< 0x00040000 */
#define EPWM_SYNCI_SEL1_4_SYNCISEL3_3            (0x8UL<<EPWM_SYNCI_SEL1_4_SYNCISEL3_Pos)         /*!< 0x00080000 */
#define EPWM_SYNCI_SEL1_4_SYNCISEL3_4            (0x10UL<<EPWM_SYNCI_SEL1_4_SYNCISEL3_Pos)        /*!< 0x00100000 */
#define EPWM_SYNCI_SEL1_4_SYNCISEL4_Pos          (24U)
#define EPWM_SYNCI_SEL1_4_SYNCISEL4_Msk          (0x1FUL<<EPWM_SYNCI_SEL1_4_SYNCISEL4_Pos)        /*!< 0x1F000000 */
#define EPWM_SYNCI_SEL1_4_SYNCISEL4              EPWM_SYNCI_SEL1_4_SYNCISEL4_Msk                  /*!< eallow, SYNCILOCK */
#define EPWM_SYNCI_SEL1_4_SYNCISEL4_0            (0x1UL<<EPWM_SYNCI_SEL1_4_SYNCISEL4_Pos)         /*!< 0x01000000 */
#define EPWM_SYNCI_SEL1_4_SYNCISEL4_1            (0x2UL<<EPWM_SYNCI_SEL1_4_SYNCISEL4_Pos)         /*!< 0x02000000 */
#define EPWM_SYNCI_SEL1_4_SYNCISEL4_2            (0x4UL<<EPWM_SYNCI_SEL1_4_SYNCISEL4_Pos)         /*!< 0x04000000 */
#define EPWM_SYNCI_SEL1_4_SYNCISEL4_3            (0x8UL<<EPWM_SYNCI_SEL1_4_SYNCISEL4_Pos)         /*!< 0x08000000 */
#define EPWM_SYNCI_SEL1_4_SYNCISEL4_4            (0x10UL<<EPWM_SYNCI_SEL1_4_SYNCISEL4_Pos)        /*!< 0x10000000 */

/********************************* Bit definition for EPWM_SYNCI_SEL5_6 register ***********************************/
#define EPWM_SYNCI_SEL5_6_SYNCISEL5_Pos          (0U)
#define EPWM_SYNCI_SEL5_6_SYNCISEL5_Msk          (0x1FUL<<EPWM_SYNCI_SEL5_6_SYNCISEL5_Pos)        /*!< 0x0000001F */
#define EPWM_SYNCI_SEL5_6_SYNCISEL5              EPWM_SYNCI_SEL5_6_SYNCISEL5_Msk                  /*!< eallow, SYNCILOCK */
#define EPWM_SYNCI_SEL5_6_SYNCISEL5_0            (0x1UL<<EPWM_SYNCI_SEL5_6_SYNCISEL5_Pos)         /*!< 0x00000001 */
#define EPWM_SYNCI_SEL5_6_SYNCISEL5_1            (0x2UL<<EPWM_SYNCI_SEL5_6_SYNCISEL5_Pos)         /*!< 0x00000002 */
#define EPWM_SYNCI_SEL5_6_SYNCISEL5_2            (0x4UL<<EPWM_SYNCI_SEL5_6_SYNCISEL5_Pos)         /*!< 0x00000004 */
#define EPWM_SYNCI_SEL5_6_SYNCISEL5_3            (0x8UL<<EPWM_SYNCI_SEL5_6_SYNCISEL5_Pos)         /*!< 0x00000008 */
#define EPWM_SYNCI_SEL5_6_SYNCISEL5_4            (0x10UL<<EPWM_SYNCI_SEL5_6_SYNCISEL5_Pos)        /*!< 0x00000010 */
#define EPWM_SYNCI_SEL5_6_SYNCISEL6_Pos          (8U)
#define EPWM_SYNCI_SEL5_6_SYNCISEL6_Msk          (0x1FUL<<EPWM_SYNCI_SEL5_6_SYNCISEL6_Pos)        /*!< 0x00001F00 */
#define EPWM_SYNCI_SEL5_6_SYNCISEL6              EPWM_SYNCI_SEL5_6_SYNCISEL6_Msk                  /*!< eallow, SYNCILOCK */
#define EPWM_SYNCI_SEL5_6_SYNCISEL6_0            (0x1UL<<EPWM_SYNCI_SEL5_6_SYNCISEL6_Pos)         /*!< 0x00000100 */
#define EPWM_SYNCI_SEL5_6_SYNCISEL6_1            (0x2UL<<EPWM_SYNCI_SEL5_6_SYNCISEL6_Pos)         /*!< 0x00000200 */
#define EPWM_SYNCI_SEL5_6_SYNCISEL6_2            (0x4UL<<EPWM_SYNCI_SEL5_6_SYNCISEL6_Pos)         /*!< 0x00000400 */
#define EPWM_SYNCI_SEL5_6_SYNCISEL6_3            (0x8UL<<EPWM_SYNCI_SEL5_6_SYNCISEL6_Pos)         /*!< 0x00000800 */
#define EPWM_SYNCI_SEL5_6_SYNCISEL6_4            (0x10UL<<EPWM_SYNCI_SEL5_6_SYNCISEL6_Pos)        /*!< 0x00001000 */

/********************************* Bit definition for EPWM_SYNCO_SEL1_4 register ***********************************/
#define EPWM_SYNCO_SEL1_4_SYNCOSEL1_Pos          (0U)
#define EPWM_SYNCO_SEL1_4_SYNCOSEL1_Msk          (0x1FUL<<EPWM_SYNCO_SEL1_4_SYNCOSEL1_Pos)        /*!< 0x0000001F */
#define EPWM_SYNCO_SEL1_4_SYNCOSEL1              EPWM_SYNCO_SEL1_4_SYNCOSEL1_Msk                  /*!< eallow */
#define EPWM_SYNCO_SEL1_4_SYNCOSEL1_0            (0x1UL<<EPWM_SYNCO_SEL1_4_SYNCOSEL1_Pos)         /*!< 0x00000001 */
#define EPWM_SYNCO_SEL1_4_SYNCOSEL1_1            (0x2UL<<EPWM_SYNCO_SEL1_4_SYNCOSEL1_Pos)         /*!< 0x00000002 */
#define EPWM_SYNCO_SEL1_4_SYNCOSEL1_2            (0x4UL<<EPWM_SYNCO_SEL1_4_SYNCOSEL1_Pos)         /*!< 0x00000004 */
#define EPWM_SYNCO_SEL1_4_SYNCOSEL1_3            (0x8UL<<EPWM_SYNCO_SEL1_4_SYNCOSEL1_Pos)         /*!< 0x00000008 */
#define EPWM_SYNCO_SEL1_4_SYNCOSEL1_4            (0x10UL<<EPWM_SYNCO_SEL1_4_SYNCOSEL1_Pos)        /*!< 0x00000010 */
#define EPWM_SYNCO_SEL1_4_SYNCOSEL2_Pos          (8U)
#define EPWM_SYNCO_SEL1_4_SYNCOSEL2_Msk          (0x1FUL<<EPWM_SYNCO_SEL1_4_SYNCOSEL2_Pos)        /*!< 0x00001F00 */
#define EPWM_SYNCO_SEL1_4_SYNCOSEL2              EPWM_SYNCO_SEL1_4_SYNCOSEL2_Msk                  /*!< eallow */
#define EPWM_SYNCO_SEL1_4_SYNCOSEL2_0            (0x1UL<<EPWM_SYNCO_SEL1_4_SYNCOSEL2_Pos)         /*!< 0x00000100 */
#define EPWM_SYNCO_SEL1_4_SYNCOSEL2_1            (0x2UL<<EPWM_SYNCO_SEL1_4_SYNCOSEL2_Pos)         /*!< 0x00000200 */
#define EPWM_SYNCO_SEL1_4_SYNCOSEL2_2            (0x4UL<<EPWM_SYNCO_SEL1_4_SYNCOSEL2_Pos)         /*!< 0x00000400 */
#define EPWM_SYNCO_SEL1_4_SYNCOSEL2_3            (0x8UL<<EPWM_SYNCO_SEL1_4_SYNCOSEL2_Pos)         /*!< 0x00000800 */
#define EPWM_SYNCO_SEL1_4_SYNCOSEL2_4            (0x10UL<<EPWM_SYNCO_SEL1_4_SYNCOSEL2_Pos)        /*!< 0x00001000 */
#define EPWM_SYNCO_SEL1_4_SYNCOSEL3_Pos          (16U)
#define EPWM_SYNCO_SEL1_4_SYNCOSEL3_Msk          (0x1FUL<<EPWM_SYNCO_SEL1_4_SYNCOSEL3_Pos)        /*!< 0x001F0000 */
#define EPWM_SYNCO_SEL1_4_SYNCOSEL3              EPWM_SYNCO_SEL1_4_SYNCOSEL3_Msk                  /*!< eallow */
#define EPWM_SYNCO_SEL1_4_SYNCOSEL3_0            (0x1UL<<EPWM_SYNCO_SEL1_4_SYNCOSEL3_Pos)         /*!< 0x00010000 */
#define EPWM_SYNCO_SEL1_4_SYNCOSEL3_1            (0x2UL<<EPWM_SYNCO_SEL1_4_SYNCOSEL3_Pos)         /*!< 0x00020000 */
#define EPWM_SYNCO_SEL1_4_SYNCOSEL3_2            (0x4UL<<EPWM_SYNCO_SEL1_4_SYNCOSEL3_Pos)         /*!< 0x00040000 */
#define EPWM_SYNCO_SEL1_4_SYNCOSEL3_3            (0x8UL<<EPWM_SYNCO_SEL1_4_SYNCOSEL3_Pos)         /*!< 0x00080000 */
#define EPWM_SYNCO_SEL1_4_SYNCOSEL3_4            (0x10UL<<EPWM_SYNCO_SEL1_4_SYNCOSEL3_Pos)        /*!< 0x00100000 */
#define EPWM_SYNCO_SEL1_4_SYNCOSEL4_Pos          (24U)
#define EPWM_SYNCO_SEL1_4_SYNCOSEL4_Msk          (0x1FUL<<EPWM_SYNCO_SEL1_4_SYNCOSEL4_Pos)        /*!< 0x1F000000 */
#define EPWM_SYNCO_SEL1_4_SYNCOSEL4              EPWM_SYNCO_SEL1_4_SYNCOSEL4_Msk                  /*!< eallow */
#define EPWM_SYNCO_SEL1_4_SYNCOSEL4_0            (0x1UL<<EPWM_SYNCO_SEL1_4_SYNCOSEL4_Pos)         /*!< 0x01000000 */
#define EPWM_SYNCO_SEL1_4_SYNCOSEL4_1            (0x2UL<<EPWM_SYNCO_SEL1_4_SYNCOSEL4_Pos)         /*!< 0x02000000 */
#define EPWM_SYNCO_SEL1_4_SYNCOSEL4_2            (0x4UL<<EPWM_SYNCO_SEL1_4_SYNCOSEL4_Pos)         /*!< 0x04000000 */
#define EPWM_SYNCO_SEL1_4_SYNCOSEL4_3            (0x8UL<<EPWM_SYNCO_SEL1_4_SYNCOSEL4_Pos)         /*!< 0x08000000 */
#define EPWM_SYNCO_SEL1_4_SYNCOSEL4_4            (0x10UL<<EPWM_SYNCO_SEL1_4_SYNCOSEL4_Pos)        /*!< 0x10000000 */

/********************************* Bit definition for EPWM_SYNCO_SEL5_6 register ***********************************/
#define EPWM_SYNCO_SEL5_6_SYNCOSEL5_Pos          (0U)
#define EPWM_SYNCO_SEL5_6_SYNCOSEL5_Msk          (0x1FUL<<EPWM_SYNCO_SEL5_6_SYNCOSEL5_Pos)        /*!< 0x0000001F */
#define EPWM_SYNCO_SEL5_6_SYNCOSEL5              EPWM_SYNCO_SEL5_6_SYNCOSEL5_Msk                  /*!< eallow */
#define EPWM_SYNCO_SEL5_6_SYNCOSEL5_0            (0x1UL<<EPWM_SYNCO_SEL5_6_SYNCOSEL5_Pos)         /*!< 0x00000001 */
#define EPWM_SYNCO_SEL5_6_SYNCOSEL5_1            (0x2UL<<EPWM_SYNCO_SEL5_6_SYNCOSEL5_Pos)         /*!< 0x00000002 */
#define EPWM_SYNCO_SEL5_6_SYNCOSEL5_2            (0x4UL<<EPWM_SYNCO_SEL5_6_SYNCOSEL5_Pos)         /*!< 0x00000004 */
#define EPWM_SYNCO_SEL5_6_SYNCOSEL5_3            (0x8UL<<EPWM_SYNCO_SEL5_6_SYNCOSEL5_Pos)         /*!< 0x00000008 */
#define EPWM_SYNCO_SEL5_6_SYNCOSEL5_4            (0x10UL<<EPWM_SYNCO_SEL5_6_SYNCOSEL5_Pos)        /*!< 0x00000010 */
#define EPWM_SYNCO_SEL5_6_SYNCOSEL6_Pos          (8U)
#define EPWM_SYNCO_SEL5_6_SYNCOSEL6_Msk          (0x1FUL<<EPWM_SYNCO_SEL5_6_SYNCOSEL6_Pos)        /*!< 0x00001F00 */
#define EPWM_SYNCO_SEL5_6_SYNCOSEL6              EPWM_SYNCO_SEL5_6_SYNCOSEL6_Msk                  /*!< eallow */
#define EPWM_SYNCO_SEL5_6_SYNCOSEL6_0            (0x1UL<<EPWM_SYNCO_SEL5_6_SYNCOSEL6_Pos)         /*!< 0x00000100 */
#define EPWM_SYNCO_SEL5_6_SYNCOSEL6_1            (0x2UL<<EPWM_SYNCO_SEL5_6_SYNCOSEL6_Pos)         /*!< 0x00000200 */
#define EPWM_SYNCO_SEL5_6_SYNCOSEL6_2            (0x4UL<<EPWM_SYNCO_SEL5_6_SYNCOSEL6_Pos)         /*!< 0x00000400 */
#define EPWM_SYNCO_SEL5_6_SYNCOSEL6_3            (0x8UL<<EPWM_SYNCO_SEL5_6_SYNCOSEL6_Pos)         /*!< 0x00000800 */
#define EPWM_SYNCO_SEL5_6_SYNCOSEL6_4            (0x10UL<<EPWM_SYNCO_SEL5_6_SYNCOSEL6_Pos)        /*!< 0x00001000 */

/********************************* Bit definition for EPWM_ADCOUT register *****************************************/
#define EPWM_ADCOUT_SOC1A_EN_Pos                 (0U)
#define EPWM_ADCOUT_SOC1A_EN_Msk                 (0x1UL<<EPWM_ADCOUT_SOC1A_EN_Pos)                /*!< 0x00000001 */
#define EPWM_ADCOUT_SOC1A_EN                     EPWM_ADCOUT_SOC1A_EN_Msk                         /*!< eallow , ADCSOCLOCK */
#define EPWM_ADCOUT_SOC2A_EN_Pos                 (1U)
#define EPWM_ADCOUT_SOC2A_EN_Msk                 (0x1UL<<EPWM_ADCOUT_SOC2A_EN_Pos)                /*!< 0x00000002 */
#define EPWM_ADCOUT_SOC2A_EN                     EPWM_ADCOUT_SOC2A_EN_Msk                         /*!< eallow , ADCSOCLOCK */
#define EPWM_ADCOUT_SOC3A_EN_Pos                 (2U)
#define EPWM_ADCOUT_SOC3A_EN_Msk                 (0x1UL<<EPWM_ADCOUT_SOC3A_EN_Pos)                /*!< 0x00000004 */
#define EPWM_ADCOUT_SOC3A_EN                     EPWM_ADCOUT_SOC3A_EN_Msk                         /*!< eallow , ADCSOCLOCK */
#define EPWM_ADCOUT_SOC4A_EN_Pos                 (3U)
#define EPWM_ADCOUT_SOC4A_EN_Msk                 (0x1UL<<EPWM_ADCOUT_SOC4A_EN_Pos)                /*!< 0x00000008 */
#define EPWM_ADCOUT_SOC4A_EN                     EPWM_ADCOUT_SOC4A_EN_Msk                         /*!< eallow , ADCSOCLOCK */
#define EPWM_ADCOUT_SOC5A_EN_Pos                 (4U)
#define EPWM_ADCOUT_SOC5A_EN_Msk                 (0x1UL<<EPWM_ADCOUT_SOC5A_EN_Pos)                /*!< 0x00000010 */
#define EPWM_ADCOUT_SOC5A_EN                     EPWM_ADCOUT_SOC5A_EN_Msk                         /*!< eallow , ADCSOCLOCK */
#define EPWM_ADCOUT_SOC6A_EN_Pos                 (5U)
#define EPWM_ADCOUT_SOC6A_EN_Msk                 (0x1UL<<EPWM_ADCOUT_SOC6A_EN_Pos)                /*!< 0x00000020 */
#define EPWM_ADCOUT_SOC6A_EN                     EPWM_ADCOUT_SOC6A_EN_Msk                         /*!< eallow , ADCSOCLOCK */
#define EPWM_ADCOUT_SOC1B_EN_Pos                 (6U)
#define EPWM_ADCOUT_SOC1B_EN_Msk                 (0x1UL<<EPWM_ADCOUT_SOC1B_EN_Pos)                /*!< 0x00000040 */
#define EPWM_ADCOUT_SOC1B_EN                     EPWM_ADCOUT_SOC1B_EN_Msk                         /*!< eallow , ADCSOCLOCK */
#define EPWM_ADCOUT_SOC2B_EN_Pos                 (7U)
#define EPWM_ADCOUT_SOC2B_EN_Msk                 (0x1UL<<EPWM_ADCOUT_SOC2B_EN_Pos)                /*!< 0x00000080 */
#define EPWM_ADCOUT_SOC2B_EN                     EPWM_ADCOUT_SOC2B_EN_Msk                         /*!< eallow , ADCSOCLOCK */
#define EPWM_ADCOUT_SOC3B_EN_Pos                 (8U)
#define EPWM_ADCOUT_SOC3B_EN_Msk                 (0x1UL<<EPWM_ADCOUT_SOC3B_EN_Pos)                /*!< 0x00000100 */
#define EPWM_ADCOUT_SOC3B_EN                     EPWM_ADCOUT_SOC3B_EN_Msk                         /*!< eallow , ADCSOCLOCK */
#define EPWM_ADCOUT_SOC4B_EN_Pos                 (9U)
#define EPWM_ADCOUT_SOC4B_EN_Msk                 (0x1UL<<EPWM_ADCOUT_SOC4B_EN_Pos)                /*!< 0x00000200 */
#define EPWM_ADCOUT_SOC4B_EN                     EPWM_ADCOUT_SOC4B_EN_Msk                         /*!< eallow , ADCSOCLOCK */
#define EPWM_ADCOUT_SOC5B_EN_Pos                 (10U)
#define EPWM_ADCOUT_SOC5B_EN_Msk                 (0x1UL<<EPWM_ADCOUT_SOC5B_EN_Pos)                /*!< 0x00000400 */
#define EPWM_ADCOUT_SOC5B_EN                     EPWM_ADCOUT_SOC5B_EN_Msk                         /*!< eallow , ADCSOCLOCK */
#define EPWM_ADCOUT_SOC6B_EN_Pos                 (11U)
#define EPWM_ADCOUT_SOC6B_EN_Msk                 (0x1UL<<EPWM_ADCOUT_SOC6B_EN_Pos)                /*!< 0x00000800 */
#define EPWM_ADCOUT_SOC6B_EN                     EPWM_ADCOUT_SOC6B_EN_Msk                         /*!< eallow , ADCSOCLOCK */
#define EPWM_ADCOUT_SOCA_POL_Pos                 (12U)
#define EPWM_ADCOUT_SOCA_POL_Msk                 (0x1UL<<EPWM_ADCOUT_SOCA_POL_Pos)                /*!< 0x00001000 */
#define EPWM_ADCOUT_SOCA_POL                     EPWM_ADCOUT_SOCA_POL_Msk                         /*!< eallow , ADCSOCLOCK */
#define EPWM_ADCOUT_SOCB_POL_Pos                 (13U)
#define EPWM_ADCOUT_SOCB_POL_Msk                 (0x1UL<<EPWM_ADCOUT_SOCB_POL_Pos)                /*!< 0x00002000 */
#define EPWM_ADCOUT_SOCB_POL                     EPWM_ADCOUT_SOCB_POL_Msk                         /*!< eallow , ADCSOCLOCK */

/********************************* Bit definition for EPWM_SCOUT_CFG register **************************************/
#define EPWM_SCOUT_CFG_SCOUT_SEL_Pos             (0U)
#define EPWM_SCOUT_CFG_SCOUT_SEL_Msk             (0x7UL<<EPWM_SCOUT_CFG_SCOUT_SEL_Pos)            /*!< 0x00000007 */
#define EPWM_SCOUT_CFG_SCOUT_SEL                 EPWM_SCOUT_CFG_SCOUT_SEL_Msk                     /*!< eallow  */
#define EPWM_SCOUT_CFG_SCOUT_SEL_0               (0x1UL<<EPWM_SCOUT_CFG_SCOUT_SEL_Pos)            /*!< 0x00000001 */
#define EPWM_SCOUT_CFG_SCOUT_SEL_1               (0x2UL<<EPWM_SCOUT_CFG_SCOUT_SEL_Pos)            /*!< 0x00000002 */
#define EPWM_SCOUT_CFG_SCOUT_SEL_2               (0x4UL<<EPWM_SCOUT_CFG_SCOUT_SEL_Pos)            /*!< 0x00000004 */
#define EPWM_SCOUT_CFG_SCOUT_EXP_BYPASS_Pos      (3U)
#define EPWM_SCOUT_CFG_SCOUT_EXP_BYPASS_Msk      (0x1UL<<EPWM_SCOUT_CFG_SCOUT_EXP_BYPASS_Pos)     /*!< 0x00000008 */
#define EPWM_SCOUT_CFG_SCOUT_EXP_BYPASS          EPWM_SCOUT_CFG_SCOUT_EXP_BYPASS_Msk              /*!< eallow  */

/********************************* Bit definition for EPWM_SYNCSOCLOCK register ************************************/
#define EPWM_SYNCSOCLOCK_SYNCILOCK_Pos           (0U)
#define EPWM_SYNCSOCLOCK_SYNCILOCK_Msk           (0x1UL<<EPWM_SYNCSOCLOCK_SYNCILOCK_Pos)          /*!< 0x00000001 */
#define EPWM_SYNCSOCLOCK_SYNCILOCK               EPWM_SYNCSOCLOCK_SYNCILOCK_Msk                   /*!< eallow  */
#define EPWM_SYNCSOCLOCK_ADCSOCLOCK_Pos          (1U)
#define EPWM_SYNCSOCLOCK_ADCSOCLOCK_Msk          (0x1UL<<EPWM_SYNCSOCLOCK_ADCSOCLOCK_Pos)         /*!< 0x00000002 */
#define EPWM_SYNCSOCLOCK_ADCSOCLOCK              EPWM_SYNCSOCLOCK_ADCSOCLOCK_Msk                  /*!< eallow  */

/********************************* Bit definition for EPWM_EALLOW register *****************************************/
#define EPWM_EALLOW_EALLOW_Pos                   (0U)
#define EPWM_EALLOW_EALLOW_Msk                   (0x1UL<<EPWM_EALLOW_EALLOW_Pos)                  /*!< 0x00000001 */
#define EPWM_EALLOW_EALLOW                       EPWM_EALLOW_EALLOW_Msk                           
#define EPWM_EALLOW_KEY_Pos                      (16U)
#define EPWM_EALLOW_KEY_Msk                      (0xFFFFUL<<EPWM_EALLOW_KEY_Pos)                  /*!< 0xFFFF0000 */
#define EPWM_EALLOW_KEY                          EPWM_EALLOW_KEY_Msk

/********************************* Bit definition for EPWM_CLKEN register ******************************************/
#define EPWM_CLKEN_EPWM1_CLK_EN_Pos             (0U)
#define EPWM_CLKEN_EPWM1_CLK_EN_Msk             (0x1UL<<EPWM_CLKEN_EPWM1_CLK_EN_Pos)            /*!< 0x00000001 */
#define EPWM_CLKEN_EPWM1_CLK_EN                 EPWM_CLKEN_EPWM1_CLK_EN_Msk                     /*!< eallow  */
#define EPWM_CLKEN_EPWM2_CLK_EN_Pos             (1U)
#define EPWM_CLKEN_EPWM2_CLK_EN_Msk             (0x1UL<<EPWM_CLKEN_EPWM2_CLK_EN_Pos)            /*!< 0x00000002 */
#define EPWM_CLKEN_EPWM2_CLK_EN                 EPWM_CLKEN_EPWM2_CLK_EN_Msk                     /*!< eallow  */
#define EPWM_CLKEN_EPWM3_CLK_EN_Pos             (2U)
#define EPWM_CLKEN_EPWM3_CLK_EN_Msk             (0x1UL<<EPWM_CLKEN_EPWM3_CLK_EN_Pos)            /*!< 0x00000004 */
#define EPWM_CLKEN_EPWM3_CLK_EN                 EPWM_CLKEN_EPWM3_CLK_EN_Msk                     /*!< eallow  */
#define EPWM_CLKEN_EPWM4_CLK_EN_Pos             (3U)
#define EPWM_CLKEN_EPWM4_CLK_EN_Msk             (0x1UL<<EPWM_CLKEN_EPWM4_CLK_EN_Pos)            /*!< 0x00000008 */
#define EPWM_CLKEN_EPWM4_CLK_EN                 EPWM_CLKEN_EPWM4_CLK_EN_Msk                     /*!< eallow  */
#define EPWM_CLKEN_EPWM5_CLK_EN_Pos             (4U)
#define EPWM_CLKEN_EPWM5_CLK_EN_Msk             (0x1UL<<EPWM_CLKEN_EPWM5_CLK_EN_Pos)            /*!< 0x00000010 */
#define EPWM_CLKEN_EPWM5_CLK_EN                 EPWM_CLKEN_EPWM5_CLK_EN_Msk                     /*!< eallow  */
#define EPWM_CLKEN_EPWM6_CLK_EN_Pos             (5U)
#define EPWM_CLKEN_EPWM6_CLK_EN_Msk             (0x1UL<<EPWM_CLKEN_EPWM6_CLK_EN_Pos)            /*!< 0x00000020 */
#define EPWM_CLKEN_EPWM6_CLK_EN                 EPWM_CLKEN_EPWM6_CLK_EN_Msk                     /*!< eallow  */

/********************************* Bit definition for EPWM_XBARFLG1 register ***************************************/
#define EPWM_XBARFLG1_COMP1_OUT_FLG_Pos          (0U)
#define EPWM_XBARFLG1_COMP1_OUT_FLG_Msk          (0x1UL<<EPWM_XBARFLG1_COMP1_OUT_FLG_Pos)         /*!< 0x00000001 */
#define EPWM_XBARFLG1_COMP1_OUT_FLG              EPWM_XBARFLG1_COMP1_OUT_FLG_Msk                  
#define EPWM_XBARFLG1_COMP2_OUT_FLG_Pos          (1U)
#define EPWM_XBARFLG1_COMP2_OUT_FLG_Msk          (0x1UL<<EPWM_XBARFLG1_COMP2_OUT_FLG_Pos)         /*!< 0x00000002 */
#define EPWM_XBARFLG1_COMP2_OUT_FLG              EPWM_XBARFLG1_COMP2_OUT_FLG_Msk                  
#define EPWM_XBARFLG1_COMP3_OUT_FLG_Pos          (2U)
#define EPWM_XBARFLG1_COMP3_OUT_FLG_Msk          (0x1UL<<EPWM_XBARFLG1_COMP3_OUT_FLG_Pos)         /*!< 0x00000004 */
#define EPWM_XBARFLG1_COMP3_OUT_FLG              EPWM_XBARFLG1_COMP3_OUT_FLG_Msk                  
#define EPWM_XBARFLG1_COMP4_OUT_FLG_Pos          (3U)
#define EPWM_XBARFLG1_COMP4_OUT_FLG_Msk          (0x1UL<<EPWM_XBARFLG1_COMP4_OUT_FLG_Pos)         /*!< 0x00000008 */
#define EPWM_XBARFLG1_COMP4_OUT_FLG              EPWM_XBARFLG1_COMP4_OUT_FLG_Msk                  
#define EPWM_XBARFLG1_INPUT1_FLG_Pos             (4U)
#define EPWM_XBARFLG1_INPUT1_FLG_Msk             (0x1UL<<EPWM_XBARFLG1_INPUT1_FLG_Pos)            /*!< 0x00000010 */
#define EPWM_XBARFLG1_INPUT1_FLG                 EPWM_XBARFLG1_INPUT1_FLG_Msk                     
#define EPWM_XBARFLG1_INPUT2_FLG_Pos             (5U)
#define EPWM_XBARFLG1_INPUT2_FLG_Msk             (0x1UL<<EPWM_XBARFLG1_INPUT2_FLG_Pos)            /*!< 0x00000020 */
#define EPWM_XBARFLG1_INPUT2_FLG                 EPWM_XBARFLG1_INPUT2_FLG_Msk                     
#define EPWM_XBARFLG1_INPUT3_FLG_Pos             (6U)
#define EPWM_XBARFLG1_INPUT3_FLG_Msk             (0x1UL<<EPWM_XBARFLG1_INPUT3_FLG_Pos)            /*!< 0x00000040 */
#define EPWM_XBARFLG1_INPUT3_FLG                 EPWM_XBARFLG1_INPUT3_FLG_Msk                     
#define EPWM_XBARFLG1_INPUT4_FLG_Pos             (7U)
#define EPWM_XBARFLG1_INPUT4_FLG_Msk             (0x1UL<<EPWM_XBARFLG1_INPUT4_FLG_Pos)            /*!< 0x00000080 */
#define EPWM_XBARFLG1_INPUT4_FLG                 EPWM_XBARFLG1_INPUT4_FLG_Msk                     
#define EPWM_XBARFLG1_INPUT5_FLG_Pos             (8U)
#define EPWM_XBARFLG1_INPUT5_FLG_Msk             (0x1UL<<EPWM_XBARFLG1_INPUT5_FLG_Pos)            /*!< 0x00000100 */
#define EPWM_XBARFLG1_INPUT5_FLG                 EPWM_XBARFLG1_INPUT5_FLG_Msk                     
#define EPWM_XBARFLG1_INPUT6_FLG_Pos             (9U)
#define EPWM_XBARFLG1_INPUT6_FLG_Msk             (0x1UL<<EPWM_XBARFLG1_INPUT6_FLG_Pos)            /*!< 0x00000200 */
#define EPWM_XBARFLG1_INPUT6_FLG                 EPWM_XBARFLG1_INPUT6_FLG_Msk                     
#define EPWM_XBARFLG1_ADCSOCA_FLG_Pos            (10U)
#define EPWM_XBARFLG1_ADCSOCA_FLG_Msk            (0x1UL<<EPWM_XBARFLG1_ADCSOCA_FLG_Pos)           /*!< 0x00000400 */
#define EPWM_XBARFLG1_ADCSOCA_FLG                EPWM_XBARFLG1_ADCSOCA_FLG_Msk                    
#define EPWM_XBARFLG1_ADCSOCB_FLG_Pos            (11U)
#define EPWM_XBARFLG1_ADCSOCB_FLG_Msk            (0x1UL<<EPWM_XBARFLG1_ADCSOCB_FLG_Pos)           /*!< 0x00000800 */
#define EPWM_XBARFLG1_ADCSOCB_FLG                EPWM_XBARFLG1_ADCSOCB_FLG_Msk                    
#define EPWM_XBARFLG1_INPUT7_FLG_Pos             (12U)
#define EPWM_XBARFLG1_INPUT7_FLG_Msk             (0x1UL<<EPWM_XBARFLG1_INPUT7_FLG_Pos)            /*!< 0x00001000 */
#define EPWM_XBARFLG1_INPUT7_FLG                 EPWM_XBARFLG1_INPUT7_FLG_Msk                     
#define EPWM_XBARFLG1_INPUT8_FLG_Pos             (13U)
#define EPWM_XBARFLG1_INPUT8_FLG_Msk             (0x1UL<<EPWM_XBARFLG1_INPUT8_FLG_Pos)            /*!< 0x00002000 */
#define EPWM_XBARFLG1_INPUT8_FLG                 EPWM_XBARFLG1_INPUT8_FLG_Msk                     
#define EPWM_XBARFLG1_INPUT9_FLG_Pos             (14U)
#define EPWM_XBARFLG1_INPUT9_FLG_Msk             (0x1UL<<EPWM_XBARFLG1_INPUT9_FLG_Pos)            /*!< 0x00004000 */
#define EPWM_XBARFLG1_INPUT9_FLG                 EPWM_XBARFLG1_INPUT9_FLG_Msk                     
#define EPWM_XBARFLG1_INPUT10_FLG_Pos            (15U)
#define EPWM_XBARFLG1_INPUT10_FLG_Msk            (0x1UL<<EPWM_XBARFLG1_INPUT10_FLG_Pos)           /*!< 0x00008000 */
#define EPWM_XBARFLG1_INPUT10_FLG                EPWM_XBARFLG1_INPUT10_FLG_Msk                    
#define EPWM_XBARFLG1_INPUT11_FLG_Pos            (16U)
#define EPWM_XBARFLG1_INPUT11_FLG_Msk            (0x1UL<<EPWM_XBARFLG1_INPUT11_FLG_Pos)           /*!< 0x00010000 */
#define EPWM_XBARFLG1_INPUT11_FLG                EPWM_XBARFLG1_INPUT11_FLG_Msk                    
#define EPWM_XBARFLG1_INPUT12_FLG_Pos            (17U)
#define EPWM_XBARFLG1_INPUT12_FLG_Msk            (0x1UL<<EPWM_XBARFLG1_INPUT12_FLG_Pos)           /*!< 0x00020000 */
#define EPWM_XBARFLG1_INPUT12_FLG                EPWM_XBARFLG1_INPUT12_FLG_Msk                    
#define EPWM_XBARFLG1_INPUT13_FLG_Pos            (18U)
#define EPWM_XBARFLG1_INPUT13_FLG_Msk            (0x1UL<<EPWM_XBARFLG1_INPUT13_FLG_Pos)           /*!< 0x00040000 */
#define EPWM_XBARFLG1_INPUT13_FLG                EPWM_XBARFLG1_INPUT13_FLG_Msk                    
#define EPWM_XBARFLG1_INPUT14_FLG_Pos            (19U)
#define EPWM_XBARFLG1_INPUT14_FLG_Msk            (0x1UL<<EPWM_XBARFLG1_INPUT14_FLG_Pos)           /*!< 0x00080000 */
#define EPWM_XBARFLG1_INPUT14_FLG                EPWM_XBARFLG1_INPUT14_FLG_Msk                    
#define EPWM_XBARFLG1_ADC1_AWD1_FLG_Pos          (20U)
#define EPWM_XBARFLG1_ADC1_AWD1_FLG_Msk          (0x1UL<<EPWM_XBARFLG1_ADC1_AWD1_FLG_Pos)         /*!< 0x00100000 */
#define EPWM_XBARFLG1_ADC1_AWD1_FLG              EPWM_XBARFLG1_ADC1_AWD1_FLG_Msk                  
#define EPWM_XBARFLG1_ADC1_AWD2_FLG_Pos          (21U)
#define EPWM_XBARFLG1_ADC1_AWD2_FLG_Msk          (0x1UL<<EPWM_XBARFLG1_ADC1_AWD2_FLG_Pos)         /*!< 0x00200000 */
#define EPWM_XBARFLG1_ADC1_AWD2_FLG              EPWM_XBARFLG1_ADC1_AWD2_FLG_Msk                  
#define EPWM_XBARFLG1_ADC1_AWD3_FLG_Pos          (22U)
#define EPWM_XBARFLG1_ADC1_AWD3_FLG_Msk          (0x1UL<<EPWM_XBARFLG1_ADC1_AWD3_FLG_Pos)         /*!< 0x00400000 */
#define EPWM_XBARFLG1_ADC1_AWD3_FLG              EPWM_XBARFLG1_ADC1_AWD3_FLG_Msk                  
#define EPWM_XBARFLG1_ADC2_AWD1_FLG_Pos          (23U)
#define EPWM_XBARFLG1_ADC2_AWD1_FLG_Msk          (0x1UL<<EPWM_XBARFLG1_ADC2_AWD1_FLG_Pos)         /*!< 0x00800000 */
#define EPWM_XBARFLG1_ADC2_AWD1_FLG              EPWM_XBARFLG1_ADC2_AWD1_FLG_Msk                  
#define EPWM_XBARFLG1_ADC2_AWD2_FLG_Pos          (24U)
#define EPWM_XBARFLG1_ADC2_AWD2_FLG_Msk          (0x1UL<<EPWM_XBARFLG1_ADC2_AWD2_FLG_Pos)         /*!< 0x01000000 */
#define EPWM_XBARFLG1_ADC2_AWD2_FLG              EPWM_XBARFLG1_ADC2_AWD2_FLG_Msk                  
#define EPWM_XBARFLG1_ADC2_AWD3_FLG_Pos          (25U)
#define EPWM_XBARFLG1_ADC2_AWD3_FLG_Msk          (0x1UL<<EPWM_XBARFLG1_ADC2_AWD3_FLG_Pos)         /*!< 0x02000000 */
#define EPWM_XBARFLG1_ADC2_AWD3_FLG              EPWM_XBARFLG1_ADC2_AWD3_FLG_Msk                  
#define EPWM_XBARFLG1_TIM1_CH1_FLG_Pos           (26U)
#define EPWM_XBARFLG1_TIM1_CH1_FLG_Msk           (0x1UL<<EPWM_XBARFLG1_TIM1_CH1_FLG_Pos)          /*!< 0x04000000 */
#define EPWM_XBARFLG1_TIM1_CH1_FLG               EPWM_XBARFLG1_TIM1_CH1_FLG_Msk                   
#define EPWM_XBARFLG1_TIM1_CH2_FLG_Pos           (27U)
#define EPWM_XBARFLG1_TIM1_CH2_FLG_Msk           (0x1UL<<EPWM_XBARFLG1_TIM1_CH2_FLG_Pos)          /*!< 0x08000000 */
#define EPWM_XBARFLG1_TIM1_CH2_FLG               EPWM_XBARFLG1_TIM1_CH2_FLG_Msk                   
#define EPWM_XBARFLG1_TIM1_CH3_FLG_Pos           (28U)
#define EPWM_XBARFLG1_TIM1_CH3_FLG_Msk           (0x1UL<<EPWM_XBARFLG1_TIM1_CH3_FLG_Pos)          /*!< 0x10000000 */
#define EPWM_XBARFLG1_TIM1_CH3_FLG               EPWM_XBARFLG1_TIM1_CH3_FLG_Msk                   
#define EPWM_XBARFLG1_TIM1_CH4_FLG_Pos           (29U)
#define EPWM_XBARFLG1_TIM1_CH4_FLG_Msk           (0x1UL<<EPWM_XBARFLG1_TIM1_CH4_FLG_Pos)          /*!< 0x20000000 */
#define EPWM_XBARFLG1_TIM1_CH4_FLG               EPWM_XBARFLG1_TIM1_CH4_FLG_Msk                   
#define EPWM_XBARFLG1_TIM1_CH5_FLG_Pos           (30U)
#define EPWM_XBARFLG1_TIM1_CH5_FLG_Msk           (0x1UL<<EPWM_XBARFLG1_TIM1_CH5_FLG_Pos)          /*!< 0x40000000 */
#define EPWM_XBARFLG1_TIM1_CH5_FLG               EPWM_XBARFLG1_TIM1_CH5_FLG_Msk                   
#define EPWM_XBARFLG1_TIM1_CH6_FLG_Pos           (31U)
#define EPWM_XBARFLG1_TIM1_CH6_FLG_Msk           (0x1UL<<EPWM_XBARFLG1_TIM1_CH6_FLG_Pos)          /*!< 0x80000000 */
#define EPWM_XBARFLG1_TIM1_CH6_FLG               EPWM_XBARFLG1_TIM1_CH6_FLG_Msk                   

/********************************* Bit definition for EPWM_XBARFLG2 register ***************************************/
#define EPWM_XBARFLG2_TIM2_CH1_FLG_Pos           (0U)
#define EPWM_XBARFLG2_TIM2_CH1_FLG_Msk           (0x1UL<<EPWM_XBARFLG2_TIM2_CH1_FLG_Pos)          /*!< 0x00000001 */
#define EPWM_XBARFLG2_TIM2_CH1_FLG               EPWM_XBARFLG2_TIM2_CH1_FLG_Msk                   
#define EPWM_XBARFLG2_TIM2_CH2_FLG_Pos           (1U)
#define EPWM_XBARFLG2_TIM2_CH2_FLG_Msk           (0x1UL<<EPWM_XBARFLG2_TIM2_CH2_FLG_Pos)          /*!< 0x00000002 */
#define EPWM_XBARFLG2_TIM2_CH2_FLG               EPWM_XBARFLG2_TIM2_CH2_FLG_Msk                   
#define EPWM_XBARFLG2_TIM2_CH3_FLG_Pos           (2U)
#define EPWM_XBARFLG2_TIM2_CH3_FLG_Msk           (0x1UL<<EPWM_XBARFLG2_TIM2_CH3_FLG_Pos)          /*!< 0x00000004 */
#define EPWM_XBARFLG2_TIM2_CH3_FLG               EPWM_XBARFLG2_TIM2_CH3_FLG_Msk                   
#define EPWM_XBARFLG2_TIM2_CH4_FLG_Pos           (3U)
#define EPWM_XBARFLG2_TIM2_CH4_FLG_Msk           (0x1UL<<EPWM_XBARFLG2_TIM2_CH4_FLG_Pos)          /*!< 0x00000008 */
#define EPWM_XBARFLG2_TIM2_CH4_FLG               EPWM_XBARFLG2_TIM2_CH4_FLG_Msk                   
#define EPWM_XBARFLG2_TIM3_CH1_FLG_Pos           (4U)
#define EPWM_XBARFLG2_TIM3_CH1_FLG_Msk           (0x1UL<<EPWM_XBARFLG2_TIM3_CH1_FLG_Pos)          /*!< 0x00000010 */
#define EPWM_XBARFLG2_TIM3_CH1_FLG               EPWM_XBARFLG2_TIM3_CH1_FLG_Msk                   
#define EPWM_XBARFLG2_TIM3_CH2_FLG_Pos           (5U)
#define EPWM_XBARFLG2_TIM3_CH2_FLG_Msk           (0x1UL<<EPWM_XBARFLG2_TIM3_CH2_FLG_Pos)          /*!< 0x00000020 */
#define EPWM_XBARFLG2_TIM3_CH2_FLG               EPWM_XBARFLG2_TIM3_CH2_FLG_Msk                   
#define EPWM_XBARFLG2_TIM3_CH3_FLG_Pos           (6U)
#define EPWM_XBARFLG2_TIM3_CH3_FLG_Msk           (0x1UL<<EPWM_XBARFLG2_TIM3_CH3_FLG_Pos)          /*!< 0x00000040 */
#define EPWM_XBARFLG2_TIM3_CH3_FLG               EPWM_XBARFLG2_TIM3_CH3_FLG_Msk                   
#define EPWM_XBARFLG2_TIM3_CH4_FLG_Pos           (7U)
#define EPWM_XBARFLG2_TIM3_CH4_FLG_Msk           (0x1UL<<EPWM_XBARFLG2_TIM3_CH4_FLG_Pos)          /*!< 0x00000080 */
#define EPWM_XBARFLG2_TIM3_CH4_FLG               EPWM_XBARFLG2_TIM3_CH4_FLG_Msk                   
#define EPWM_XBARFLG2_TIM8_CH1_FLG_Pos           (8U)
#define EPWM_XBARFLG2_TIM8_CH1_FLG_Msk           (0x1UL<<EPWM_XBARFLG2_TIM8_CH1_FLG_Pos)          /*!< 0x00000100 */
#define EPWM_XBARFLG2_TIM8_CH1_FLG               EPWM_XBARFLG2_TIM8_CH1_FLG_Msk                   
#define EPWM_XBARFLG2_TIM8_CH2_FLG_Pos           (9U)
#define EPWM_XBARFLG2_TIM8_CH2_FLG_Msk           (0x1UL<<EPWM_XBARFLG2_TIM8_CH2_FLG_Pos)          /*!< 0x00000200 */
#define EPWM_XBARFLG2_TIM8_CH2_FLG               EPWM_XBARFLG2_TIM8_CH2_FLG_Msk                   
#define EPWM_XBARFLG2_TIM8_CH3_FLG_Pos           (10U)
#define EPWM_XBARFLG2_TIM8_CH3_FLG_Msk           (0x1UL<<EPWM_XBARFLG2_TIM8_CH3_FLG_Pos)          /*!< 0x00000400 */
#define EPWM_XBARFLG2_TIM8_CH3_FLG               EPWM_XBARFLG2_TIM8_CH3_FLG_Msk                   
#define EPWM_XBARFLG2_TIM8_CH4_FLG_Pos           (11U)
#define EPWM_XBARFLG2_TIM8_CH4_FLG_Msk           (0x1UL<<EPWM_XBARFLG2_TIM8_CH4_FLG_Pos)          /*!< 0x00000800 */
#define EPWM_XBARFLG2_TIM8_CH4_FLG               EPWM_XBARFLG2_TIM8_CH4_FLG_Msk                   
#define EPWM_XBARFLG2_TIM8_CH5_FLG_Pos           (12U)
#define EPWM_XBARFLG2_TIM8_CH5_FLG_Msk           (0x1UL<<EPWM_XBARFLG2_TIM8_CH5_FLG_Pos)          /*!< 0x00001000 */
#define EPWM_XBARFLG2_TIM8_CH5_FLG               EPWM_XBARFLG2_TIM8_CH5_FLG_Msk                   
#define EPWM_XBARFLG2_TIM8_CH6_FLG_Pos           (13U)
#define EPWM_XBARFLG2_TIM8_CH6_FLG_Msk           (0x1UL<<EPWM_XBARFLG2_TIM8_CH6_FLG_Pos)          /*!< 0x00002000 */
#define EPWM_XBARFLG2_TIM8_CH6_FLG               EPWM_XBARFLG2_TIM8_CH6_FLG_Msk                   
#define EPWM_XBARFLG2_EPWM_SCOUT_FLG_Pos        (14U)
#define EPWM_XBARFLG2_EPWM_SCOUT_FLG_Msk        (0x1UL<<EPWM_XBARFLG2_EPWM_SCOUT_FLG_Pos)       /*!< 0x00004000 */
#define EPWM_XBARFLG2_EPWM_SCOUT_FLG            EPWM_XBARFLG2_EPWM_SCOUT_FLG_Msk                
#define EPWM_XBARFLG2_CPUHALT_FLG_Pos            (15U)
#define EPWM_XBARFLG2_CPUHALT_FLG_Msk            (0x1UL<<EPWM_XBARFLG2_CPUHALT_FLG_Pos)           /*!< 0x00008000 */
#define EPWM_XBARFLG2_CPUHALT_FLG                EPWM_XBARFLG2_CPUHALT_FLG_Msk                    

/********************************* Bit definition for EPWM_XBARCLR1 register ***************************************/
#define EPWM_XBARCLR1_COMP1_OUT_CLR_Pos          (0U)
#define EPWM_XBARCLR1_COMP1_OUT_CLR_Msk          (0x1UL<<EPWM_XBARCLR1_COMP1_OUT_CLR_Pos)         /*!< 0x00000001 */
#define EPWM_XBARCLR1_COMP1_OUT_CLR              EPWM_XBARCLR1_COMP1_OUT_CLR_Msk                  
#define EPWM_XBARCLR1_COMP2_OUT_CLR_Pos          (1U)
#define EPWM_XBARCLR1_COMP2_OUT_CLR_Msk          (0x1UL<<EPWM_XBARCLR1_COMP2_OUT_CLR_Pos)         /*!< 0x00000002 */
#define EPWM_XBARCLR1_COMP2_OUT_CLR              EPWM_XBARCLR1_COMP2_OUT_CLR_Msk                  
#define EPWM_XBARCLR1_COMP3_OUT_CLR_Pos          (2U)
#define EPWM_XBARCLR1_COMP3_OUT_CLR_Msk          (0x1UL<<EPWM_XBARCLR1_COMP3_OUT_CLR_Pos)         /*!< 0x00000004 */
#define EPWM_XBARCLR1_COMP3_OUT_CLR              EPWM_XBARCLR1_COMP3_OUT_CLR_Msk                  
#define EPWM_XBARCLR1_COMP4_OUT_CLR_Pos          (3U)
#define EPWM_XBARCLR1_COMP4_OUT_CLR_Msk          (0x1UL<<EPWM_XBARCLR1_COMP4_OUT_CLR_Pos)         /*!< 0x00000008 */
#define EPWM_XBARCLR1_COMP4_OUT_CLR              EPWM_XBARCLR1_COMP4_OUT_CLR_Msk                  
#define EPWM_XBARCLR1_INPUT1_CLR_Pos             (4U)
#define EPWM_XBARCLR1_INPUT1_CLR_Msk             (0x1UL<<EPWM_XBARCLR1_INPUT1_CLR_Pos)            /*!< 0x00000010 */
#define EPWM_XBARCLR1_INPUT1_CLR                 EPWM_XBARCLR1_INPUT1_CLR_Msk                     
#define EPWM_XBARCLR1_INPUT2_CLR_Pos             (5U)
#define EPWM_XBARCLR1_INPUT2_CLR_Msk             (0x1UL<<EPWM_XBARCLR1_INPUT2_CLR_Pos)            /*!< 0x00000020 */
#define EPWM_XBARCLR1_INPUT2_CLR                 EPWM_XBARCLR1_INPUT2_CLR_Msk                     
#define EPWM_XBARCLR1_INPUT3_CLR_Pos             (6U)
#define EPWM_XBARCLR1_INPUT3_CLR_Msk             (0x1UL<<EPWM_XBARCLR1_INPUT3_CLR_Pos)            /*!< 0x00000040 */
#define EPWM_XBARCLR1_INPUT3_CLR                 EPWM_XBARCLR1_INPUT3_CLR_Msk                     
#define EPWM_XBARCLR1_INPUT4_CLR_Pos             (7U)
#define EPWM_XBARCLR1_INPUT4_CLR_Msk             (0x1UL<<EPWM_XBARCLR1_INPUT4_CLR_Pos)            /*!< 0x00000080 */
#define EPWM_XBARCLR1_INPUT4_CLR                 EPWM_XBARCLR1_INPUT4_CLR_Msk                     
#define EPWM_XBARCLR1_INPUT5_CLR_Pos             (8U)
#define EPWM_XBARCLR1_INPUT5_CLR_Msk             (0x1UL<<EPWM_XBARCLR1_INPUT5_CLR_Pos)            /*!< 0x00000100 */
#define EPWM_XBARCLR1_INPUT5_CLR                 EPWM_XBARCLR1_INPUT5_CLR_Msk                     
#define EPWM_XBARCLR1_INPUT6_CLR_Pos             (9U)
#define EPWM_XBARCLR1_INPUT6_CLR_Msk             (0x1UL<<EPWM_XBARCLR1_INPUT6_CLR_Pos)            /*!< 0x00000200 */
#define EPWM_XBARCLR1_INPUT6_CLR                 EPWM_XBARCLR1_INPUT6_CLR_Msk                     
#define EPWM_XBARCLR1_ADCSOCA_CLR_Pos            (10U)
#define EPWM_XBARCLR1_ADCSOCA_CLR_Msk            (0x1UL<<EPWM_XBARCLR1_ADCSOCA_CLR_Pos)           /*!< 0x00000400 */
#define EPWM_XBARCLR1_ADCSOCA_CLR                EPWM_XBARCLR1_ADCSOCA_CLR_Msk                    
#define EPWM_XBARCLR1_ADCSOCB_CLR_Pos            (11U)
#define EPWM_XBARCLR1_ADCSOCB_CLR_Msk            (0x1UL<<EPWM_XBARCLR1_ADCSOCB_CLR_Pos)           /*!< 0x00000800 */
#define EPWM_XBARCLR1_ADCSOCB_CLR                EPWM_XBARCLR1_ADCSOCB_CLR_Msk                    
#define EPWM_XBARCLR1_INPUT7_CLR_Pos             (12U)
#define EPWM_XBARCLR1_INPUT7_CLR_Msk             (0x1UL<<EPWM_XBARCLR1_INPUT7_CLR_Pos)            /*!< 0x00001000 */
#define EPWM_XBARCLR1_INPUT7_CLR                 EPWM_XBARCLR1_INPUT7_CLR_Msk                     
#define EPWM_XBARCLR1_INPUT8_CLR_Pos             (13U)
#define EPWM_XBARCLR1_INPUT8_CLR_Msk             (0x1UL<<EPWM_XBARCLR1_INPUT8_CLR_Pos)            /*!< 0x00002000 */
#define EPWM_XBARCLR1_INPUT8_CLR                 EPWM_XBARCLR1_INPUT8_CLR_Msk                     
#define EPWM_XBARCLR1_INPUT9_CLR_Pos             (14U)
#define EPWM_XBARCLR1_INPUT9_CLR_Msk             (0x1UL<<EPWM_XBARCLR1_INPUT9_CLR_Pos)            /*!< 0x00004000 */
#define EPWM_XBARCLR1_INPUT9_CLR                 EPWM_XBARCLR1_INPUT9_CLR_Msk                     
#define EPWM_XBARCLR1_INPUT10_CLR_Pos            (15U)
#define EPWM_XBARCLR1_INPUT10_CLR_Msk            (0x1UL<<EPWM_XBARCLR1_INPUT10_CLR_Pos)           /*!< 0x00008000 */
#define EPWM_XBARCLR1_INPUT10_CLR                EPWM_XBARCLR1_INPUT10_CLR_Msk                    
#define EPWM_XBARCLR1_INPUT11_CLR_Pos            (16U)
#define EPWM_XBARCLR1_INPUT11_CLR_Msk            (0x1UL<<EPWM_XBARCLR1_INPUT11_CLR_Pos)           /*!< 0x00010000 */
#define EPWM_XBARCLR1_INPUT11_CLR                EPWM_XBARCLR1_INPUT11_CLR_Msk                    
#define EPWM_XBARCLR1_INPUT12_CLR_Pos            (17U)
#define EPWM_XBARCLR1_INPUT12_CLR_Msk            (0x1UL<<EPWM_XBARCLR1_INPUT12_CLR_Pos)           /*!< 0x00020000 */
#define EPWM_XBARCLR1_INPUT12_CLR                EPWM_XBARCLR1_INPUT12_CLR_Msk                    
#define EPWM_XBARCLR1_INPUT13_CLR_Pos            (18U)
#define EPWM_XBARCLR1_INPUT13_CLR_Msk            (0x1UL<<EPWM_XBARCLR1_INPUT13_CLR_Pos)           /*!< 0x00040000 */
#define EPWM_XBARCLR1_INPUT13_CLR                EPWM_XBARCLR1_INPUT13_CLR_Msk                    
#define EPWM_XBARCLR1_INPUT14_CLR_Pos            (19U)
#define EPWM_XBARCLR1_INPUT14_CLR_Msk            (0x1UL<<EPWM_XBARCLR1_INPUT14_CLR_Pos)           /*!< 0x00080000 */
#define EPWM_XBARCLR1_INPUT14_CLR                EPWM_XBARCLR1_INPUT14_CLR_Msk                    
#define EPWM_XBARCLR1_ADC1_AWD1_CLR_Pos          (20U)
#define EPWM_XBARCLR1_ADC1_AWD1_CLR_Msk          (0x1UL<<EPWM_XBARCLR1_ADC1_AWD1_CLR_Pos)         /*!< 0x00100000 */
#define EPWM_XBARCLR1_ADC1_AWD1_CLR              EPWM_XBARCLR1_ADC1_AWD1_CLR_Msk                  
#define EPWM_XBARCLR1_ADC1_AWD2_CLR_Pos          (21U)
#define EPWM_XBARCLR1_ADC1_AWD2_CLR_Msk          (0x1UL<<EPWM_XBARCLR1_ADC1_AWD2_CLR_Pos)         /*!< 0x00200000 */
#define EPWM_XBARCLR1_ADC1_AWD2_CLR              EPWM_XBARCLR1_ADC1_AWD2_CLR_Msk                  
#define EPWM_XBARCLR1_ADC1_AWD3_CLR_Pos          (22U)
#define EPWM_XBARCLR1_ADC1_AWD3_CLR_Msk          (0x1UL<<EPWM_XBARCLR1_ADC1_AWD3_CLR_Pos)         /*!< 0x00400000 */
#define EPWM_XBARCLR1_ADC1_AWD3_CLR              EPWM_XBARCLR1_ADC1_AWD3_CLR_Msk                  
#define EPWM_XBARCLR1_ADC2_AWD1_CLR_Pos          (23U)
#define EPWM_XBARCLR1_ADC2_AWD1_CLR_Msk          (0x1UL<<EPWM_XBARCLR1_ADC2_AWD1_CLR_Pos)         /*!< 0x00800000 */
#define EPWM_XBARCLR1_ADC2_AWD1_CLR              EPWM_XBARCLR1_ADC2_AWD1_CLR_Msk                  
#define EPWM_XBARCLR1_ADC2_AWD2_CLR_Pos          (24U)
#define EPWM_XBARCLR1_ADC2_AWD2_CLR_Msk          (0x1UL<<EPWM_XBARCLR1_ADC2_AWD2_CLR_Pos)         /*!< 0x01000000 */
#define EPWM_XBARCLR1_ADC2_AWD2_CLR              EPWM_XBARCLR1_ADC2_AWD2_CLR_Msk                  
#define EPWM_XBARCLR1_ADC2_AWD3_CLR_Pos          (25U)
#define EPWM_XBARCLR1_ADC2_AWD3_CLR_Msk          (0x1UL<<EPWM_XBARCLR1_ADC2_AWD3_CLR_Pos)         /*!< 0x02000000 */
#define EPWM_XBARCLR1_ADC2_AWD3_CLR              EPWM_XBARCLR1_ADC2_AWD3_CLR_Msk                  
#define EPWM_XBARCLR1_TIM1_CH1_CLR_Pos           (26U)
#define EPWM_XBARCLR1_TIM1_CH1_CLR_Msk           (0x1UL<<EPWM_XBARCLR1_TIM1_CH1_CLR_Pos)          /*!< 0x04000000 */
#define EPWM_XBARCLR1_TIM1_CH1_CLR               EPWM_XBARCLR1_TIM1_CH1_CLR_Msk                   
#define EPWM_XBARCLR1_TIM1_CH2_CLR_Pos           (27U)
#define EPWM_XBARCLR1_TIM1_CH2_CLR_Msk           (0x1UL<<EPWM_XBARCLR1_TIM1_CH2_CLR_Pos)          /*!< 0x08000000 */
#define EPWM_XBARCLR1_TIM1_CH2_CLR               EPWM_XBARCLR1_TIM1_CH2_CLR_Msk                   
#define EPWM_XBARCLR1_TIM1_CH3_CLR_Pos           (28U)
#define EPWM_XBARCLR1_TIM1_CH3_CLR_Msk           (0x1UL<<EPWM_XBARCLR1_TIM1_CH3_CLR_Pos)          /*!< 0x10000000 */
#define EPWM_XBARCLR1_TIM1_CH3_CLR               EPWM_XBARCLR1_TIM1_CH3_CLR_Msk                   
#define EPWM_XBARCLR1_TIM1_CH4_CLR_Pos           (29U)
#define EPWM_XBARCLR1_TIM1_CH4_CLR_Msk           (0x1UL<<EPWM_XBARCLR1_TIM1_CH4_CLR_Pos)          /*!< 0x20000000 */
#define EPWM_XBARCLR1_TIM1_CH4_CLR               EPWM_XBARCLR1_TIM1_CH4_CLR_Msk                   
#define EPWM_XBARCLR1_TIM1_CH5_CLR_Pos           (30U)
#define EPWM_XBARCLR1_TIM1_CH5_CLR_Msk           (0x1UL<<EPWM_XBARCLR1_TIM1_CH5_CLR_Pos)          /*!< 0x40000000 */
#define EPWM_XBARCLR1_TIM1_CH5_CLR               EPWM_XBARCLR1_TIM1_CH5_CLR_Msk                   
#define EPWM_XBARCLR1_TIM1_CH6_CLR_Pos           (31U)
#define EPWM_XBARCLR1_TIM1_CH6_CLR_Msk           (0x1UL<<EPWM_XBARCLR1_TIM1_CH6_CLR_Pos)          /*!< 0x80000000 */
#define EPWM_XBARCLR1_TIM1_CH6_CLR               EPWM_XBARCLR1_TIM1_CH6_CLR_Msk                   

/********************************* Bit definition for EPWM_XBARCLR2 register ***************************************/
#define EPWM_XBARCLR2_TIM2_CH1_CLR_Pos           (0U)
#define EPWM_XBARCLR2_TIM2_CH1_CLR_Msk           (0x1UL<<EPWM_XBARCLR2_TIM2_CH1_CLR_Pos)          /*!< 0x00000001 */
#define EPWM_XBARCLR2_TIM2_CH1_CLR               EPWM_XBARCLR2_TIM2_CH1_CLR_Msk                   
#define EPWM_XBARCLR2_TIM2_CH2_CLR_Pos           (1U)
#define EPWM_XBARCLR2_TIM2_CH2_CLR_Msk           (0x1UL<<EPWM_XBARCLR2_TIM2_CH2_CLR_Pos)          /*!< 0x00000002 */
#define EPWM_XBARCLR2_TIM2_CH2_CLR               EPWM_XBARCLR2_TIM2_CH2_CLR_Msk                   
#define EPWM_XBARCLR2_TIM2_CH3_CLR_Pos           (2U)
#define EPWM_XBARCLR2_TIM2_CH3_CLR_Msk           (0x1UL<<EPWM_XBARCLR2_TIM2_CH3_CLR_Pos)          /*!< 0x00000004 */
#define EPWM_XBARCLR2_TIM2_CH3_CLR               EPWM_XBARCLR2_TIM2_CH3_CLR_Msk                   
#define EPWM_XBARCLR2_TIM2_CH4_CLR_Pos           (3U)
#define EPWM_XBARCLR2_TIM2_CH4_CLR_Msk           (0x1UL<<EPWM_XBARCLR2_TIM2_CH4_CLR_Pos)          /*!< 0x00000008 */
#define EPWM_XBARCLR2_TIM2_CH4_CLR               EPWM_XBARCLR2_TIM2_CH4_CLR_Msk                   
#define EPWM_XBARCLR2_TIM3_CH1_CLR_Pos           (4U)
#define EPWM_XBARCLR2_TIM3_CH1_CLR_Msk           (0x1UL<<EPWM_XBARCLR2_TIM3_CH1_CLR_Pos)          /*!< 0x00000010 */
#define EPWM_XBARCLR2_TIM3_CH1_CLR               EPWM_XBARCLR2_TIM3_CH1_CLR_Msk                   
#define EPWM_XBARCLR2_TIM3_CH2_CLR_Pos           (5U)
#define EPWM_XBARCLR2_TIM3_CH2_CLR_Msk           (0x1UL<<EPWM_XBARCLR2_TIM3_CH2_CLR_Pos)          /*!< 0x00000020 */
#define EPWM_XBARCLR2_TIM3_CH2_CLR               EPWM_XBARCLR2_TIM3_CH2_CLR_Msk                   
#define EPWM_XBARCLR2_TIM3_CH3_CLR_Pos           (6U)
#define EPWM_XBARCLR2_TIM3_CH3_CLR_Msk           (0x1UL<<EPWM_XBARCLR2_TIM3_CH3_CLR_Pos)          /*!< 0x00000040 */
#define EPWM_XBARCLR2_TIM3_CH3_CLR               EPWM_XBARCLR2_TIM3_CH3_CLR_Msk                   
#define EPWM_XBARCLR2_TIM3_CH4_CLR_Pos           (7U)
#define EPWM_XBARCLR2_TIM3_CH4_CLR_Msk           (0x1UL<<EPWM_XBARCLR2_TIM3_CH4_CLR_Pos)          /*!< 0x00000080 */
#define EPWM_XBARCLR2_TIM3_CH4_CLR               EPWM_XBARCLR2_TIM3_CH4_CLR_Msk                   
#define EPWM_XBARCLR2_TIM8_CH1_CLR_Pos           (8U)
#define EPWM_XBARCLR2_TIM8_CH1_CLR_Msk           (0x1UL<<EPWM_XBARCLR2_TIM8_CH1_CLR_Pos)          /*!< 0x00000100 */
#define EPWM_XBARCLR2_TIM8_CH1_CLR               EPWM_XBARCLR2_TIM8_CH1_CLR_Msk                   
#define EPWM_XBARCLR2_TIM8_CH2_CLR_Pos           (9U)
#define EPWM_XBARCLR2_TIM8_CH2_CLR_Msk           (0x1UL<<EPWM_XBARCLR2_TIM8_CH2_CLR_Pos)          /*!< 0x00000200 */
#define EPWM_XBARCLR2_TIM8_CH2_CLR               EPWM_XBARCLR2_TIM8_CH2_CLR_Msk                   
#define EPWM_XBARCLR2_TIM8_CH3_CLR_Pos           (10U)
#define EPWM_XBARCLR2_TIM8_CH3_CLR_Msk           (0x1UL<<EPWM_XBARCLR2_TIM8_CH3_CLR_Pos)          /*!< 0x00000400 */
#define EPWM_XBARCLR2_TIM8_CH3_CLR               EPWM_XBARCLR2_TIM8_CH3_CLR_Msk                   
#define EPWM_XBARCLR2_TIM8_CH4_CLR_Pos           (11U)
#define EPWM_XBARCLR2_TIM8_CH4_CLR_Msk           (0x1UL<<EPWM_XBARCLR2_TIM8_CH4_CLR_Pos)          /*!< 0x00000800 */
#define EPWM_XBARCLR2_TIM8_CH4_CLR               EPWM_XBARCLR2_TIM8_CH4_CLR_Msk                   
#define EPWM_XBARCLR2_TIM8_CH5_CLR_Pos           (12U)
#define EPWM_XBARCLR2_TIM8_CH5_CLR_Msk           (0x1UL<<EPWM_XBARCLR2_TIM8_CH5_CLR_Pos)          /*!< 0x00001000 */
#define EPWM_XBARCLR2_TIM8_CH5_CLR               EPWM_XBARCLR2_TIM8_CH5_CLR_Msk                   
#define EPWM_XBARCLR2_TIM8_CH6_CLR_Pos           (13U)
#define EPWM_XBARCLR2_TIM8_CH6_CLR_Msk           (0x1UL<<EPWM_XBARCLR2_TIM8_CH6_CLR_Pos)          /*!< 0x00002000 */
#define EPWM_XBARCLR2_TIM8_CH6_CLR               EPWM_XBARCLR2_TIM8_CH6_CLR_Msk                   
#define EPWM_XBARCLR2_EPWM_SCOUT_CLR_Pos        (14U)
#define EPWM_XBARCLR2_EPWM_SCOUT_CLR_Msk        (0x1UL<<EPWM_XBARCLR2_EPWM_SCOUT_CLR_Pos)       /*!< 0x00004000 */
#define EPWM_XBARCLR2_EPWM_SCOUT_CLR            EPWM_XBARCLR2_EPWM_SCOUT_CLR_Msk                
#define EPWM_XBARCLR2_CPUHALT_CLR_Pos            (15U)
#define EPWM_XBARCLR2_CPUHALT_CLR_Msk            (0x1UL<<EPWM_XBARCLR2_CPUHALT_CLR_Pos)           /*!< 0x00008000 */
#define EPWM_XBARCLR2_CPUHALT_CLR                EPWM_XBARCLR2_CPUHALT_CLR_Msk                    

/********************************* Bit definition for EPWM_FPGA_SFO_DBG register ***********************************/
#define EPWM_FPGA_SFO_DBG_SFO_DEBUG_Pos          (0U)
#define EPWM_FPGA_SFO_DBG_SFO_DEBUG_Msk          (0x7UL<<EPWM_FPGA_SFO_DBG_SFO_DEBUG_Pos)         /*!< 0x00000007 */
#define EPWM_FPGA_SFO_DBG_SFO_DEBUG              EPWM_FPGA_SFO_DBG_SFO_DEBUG_Msk
#define EPWM_FPGA_SFO_DBG_SFO_DEBUG_0            (0x1UL<<EPWM_FPGA_SFO_DBG_SFO_DEBUG_Pos)         /*!< 0x00000001 */
#define EPWM_FPGA_SFO_DBG_SFO_DEBUG_1            (0x2UL<<EPWM_FPGA_SFO_DBG_SFO_DEBUG_Pos)         /*!< 0x00000002 */
#define EPWM_FPGA_SFO_DBG_SFO_DEBUG_2            (0x4UL<<EPWM_FPGA_SFO_DBG_SFO_DEBUG_Pos)         /*!< 0x00000004 */

/********************************************************************************************************************/
/********************************* EPWM ***************************************************************************/
/********************************************************************************************************************/

/********************************* Bit definition for EPWM_TBCTL register *****************************************/
#define EPWM_TBCTL_CTRMODE_Pos                  (0U)
#define EPWM_TBCTL_CTRMODE_Msk                  (0x3UL<<EPWM_TBCTL_CTRMODE_Pos)                 /*!< 0x00000003 */
#define EPWM_TBCTL_CTRMODE                      EPWM_TBCTL_CTRMODE_Msk
#define EPWM_TBCTL_CTRMODE_0                    (0x1UL<<EPWM_TBCTL_CTRMODE_Pos)                 /*!< 0x00000001 */
#define EPWM_TBCTL_CTRMODE_1                    (0x2UL<<EPWM_TBCTL_CTRMODE_Pos)                 /*!< 0x00000002 */
#define EPWM_TBCTL_PHSEN_Pos                    (2U)
#define EPWM_TBCTL_PHSEN_Msk                    (0x1UL<<EPWM_TBCTL_PHSEN_Pos)                   /*!< 0x00000004 */
#define EPWM_TBCTL_PHSEN                        EPWM_TBCTL_PHSEN_Msk                            
#define EPWM_TBCTL_PRDLD_Pos                    (3U)
#define EPWM_TBCTL_PRDLD_Msk                    (0x1UL<<EPWM_TBCTL_PRDLD_Pos)                   /*!< 0x00000008 */
#define EPWM_TBCTL_PRDLD                        EPWM_TBCTL_PRDLD_Msk                            
#define EPWM_TBCTL_SYNCOSEL_Pos                 (4U)
#define EPWM_TBCTL_SYNCOSEL_Msk                 (0x3UL<<EPWM_TBCTL_SYNCOSEL_Pos)                /*!< 0x00000030 */
#define EPWM_TBCTL_SYNCOSEL                     EPWM_TBCTL_SYNCOSEL_Msk
#define EPWM_TBCTL_SYNCOSEL_0                   (0x1UL<<EPWM_TBCTL_SYNCOSEL_Pos)                /*!< 0x00000010 */
#define EPWM_TBCTL_SYNCOSEL_1                   (0x2UL<<EPWM_TBCTL_SYNCOSEL_Pos)                /*!< 0x00000020 */
#define EPWM_TBCTL_SWFSYNC_Pos                  (6U)
#define EPWM_TBCTL_SWFSYNC_Msk                  (0x1UL<<EPWM_TBCTL_SWFSYNC_Pos)                 /*!< 0x00000040 */
#define EPWM_TBCTL_SWFSYNC                      EPWM_TBCTL_SWFSYNC_Msk                          
#define EPWM_TBCTL_HSPCLKDIV_Pos                (7U)
#define EPWM_TBCTL_HSPCLKDIV_Msk                (0x7UL<<EPWM_TBCTL_HSPCLKDIV_Pos)               /*!< 0x00000380 */
#define EPWM_TBCTL_HSPCLKDIV                    EPWM_TBCTL_HSPCLKDIV_Msk
#define EPWM_TBCTL_HSPCLKDIV_0                  (0x1UL<<EPWM_TBCTL_HSPCLKDIV_Pos)               /*!< 0x00000080 */
#define EPWM_TBCTL_HSPCLKDIV_1                  (0x2UL<<EPWM_TBCTL_HSPCLKDIV_Pos)               /*!< 0x00000100 */
#define EPWM_TBCTL_HSPCLKDIV_2                  (0x4UL<<EPWM_TBCTL_HSPCLKDIV_Pos)               /*!< 0x00000200 */
#define EPWM_TBCTL_CLKDIV_Pos                   (10U)
#define EPWM_TBCTL_CLKDIV_Msk                   (0x7UL<<EPWM_TBCTL_CLKDIV_Pos)                  /*!< 0x00001C00 */
#define EPWM_TBCTL_CLKDIV                       EPWM_TBCTL_CLKDIV_Msk
#define EPWM_TBCTL_CLKDIV_0                     (0x1UL<<EPWM_TBCTL_CLKDIV_Pos)                  /*!< 0x00000400 */
#define EPWM_TBCTL_CLKDIV_1                     (0x2UL<<EPWM_TBCTL_CLKDIV_Pos)                  /*!< 0x00000800 */
#define EPWM_TBCTL_CLKDIV_2                     (0x4UL<<EPWM_TBCTL_CLKDIV_Pos)                  /*!< 0x00001000 */
#define EPWM_TBCTL_PHSDIR_Pos                   (13U)
#define EPWM_TBCTL_PHSDIR_Msk                   (0x1UL<<EPWM_TBCTL_PHSDIR_Pos)                  /*!< 0x00002000 */
#define EPWM_TBCTL_PHSDIR                       EPWM_TBCTL_PHSDIR_Msk                           
#define EPWM_TBCTL_FREE_SOFT_Pos                (14U)
#define EPWM_TBCTL_FREE_SOFT_Msk                (0x3UL<<EPWM_TBCTL_FREE_SOFT_Pos)               /*!< 0x0000C000 */
#define EPWM_TBCTL_FREE_SOFT                    EPWM_TBCTL_FREE_SOFT_Msk
#define EPWM_TBCTL_FREE_SOFT_0                  (0x1UL<<EPWM_TBCTL_FREE_SOFT_Pos)               /*!< 0x00004000 */
#define EPWM_TBCTL_FREE_SOFT_1                  (0x2UL<<EPWM_TBCTL_FREE_SOFT_Pos)               /*!< 0x00008000 */

/********************************* Bit definition for EPWM_TBCTL2 register ****************************************/
#define EPWM_TBCTL2_OSHTSYNCMODE_Pos            (6U)
#define EPWM_TBCTL2_OSHTSYNCMODE_Msk            (0x1UL<<EPWM_TBCTL2_OSHTSYNCMODE_Pos)           /*!< 0x00000040 */
#define EPWM_TBCTL2_OSHTSYNCMODE                EPWM_TBCTL2_OSHTSYNCMODE_Msk                    
#define EPWM_TBCTL2_OSHTSYNC_Pos                (7U)
#define EPWM_TBCTL2_OSHTSYNC_Msk                (0x1UL<<EPWM_TBCTL2_OSHTSYNC_Pos)               /*!< 0x00000080 */
#define EPWM_TBCTL2_OSHTSYNC                    EPWM_TBCTL2_OSHTSYNC_Msk                        
#define EPWM_TBCTL2_SYNCOSELX_Pos               (12U)
#define EPWM_TBCTL2_SYNCOSELX_Msk               (0x3UL<<EPWM_TBCTL2_SYNCOSELX_Pos)              /*!< 0x00003000 */
#define EPWM_TBCTL2_SYNCOSELX                   EPWM_TBCTL2_SYNCOSELX_Msk
#define EPWM_TBCTL2_SYNCOSELX_0                 (0x1UL<<EPWM_TBCTL2_SYNCOSELX_Pos)              /*!< 0x00001000 */
#define EPWM_TBCTL2_SYNCOSELX_1                 (0x2UL<<EPWM_TBCTL2_SYNCOSELX_Pos)              /*!< 0x00002000 */
#define EPWM_TBCTL2_PRDLDSYNC_Pos               (14U)
#define EPWM_TBCTL2_PRDLDSYNC_Msk               (0x3UL<<EPWM_TBCTL2_PRDLDSYNC_Pos)              /*!< 0x0000C000 */
#define EPWM_TBCTL2_PRDLDSYNC                   EPWM_TBCTL2_PRDLDSYNC_Msk
#define EPWM_TBCTL2_PRDLDSYNC_0                 (0x1UL<<EPWM_TBCTL2_PRDLDSYNC_Pos)              /*!< 0x00004000 */
#define EPWM_TBCTL2_PRDLDSYNC_1                 (0x2UL<<EPWM_TBCTL2_PRDLDSYNC_Pos)              /*!< 0x00008000 */

/********************************* Bit definition for EPWM_TBCTR register *****************************************/
#define EPWM_TBCTR_TBCTR_Pos                    (0U)
#define EPWM_TBCTR_TBCTR_Msk                    (0xFFFFUL<<EPWM_TBCTR_TBCTR_Pos)                /*!< 0x0000FFFF */
#define EPWM_TBCTR_TBCTR                        EPWM_TBCTR_TBCTR_Msk

/********************************* Bit definition for EPWM_TBSTS register *****************************************/
#define EPWM_TBSTS_CTRDIR_Pos                   (0U)
#define EPWM_TBSTS_CTRDIR_Msk                   (0x1UL<<EPWM_TBSTS_CTRDIR_Pos)                  /*!< 0x00000001 */
#define EPWM_TBSTS_CTRDIR                       EPWM_TBSTS_CTRDIR_Msk                           
#define EPWM_TBSTS_SYNCI_Pos                    (1U)
#define EPWM_TBSTS_SYNCI_Msk                    (0x1UL<<EPWM_TBSTS_SYNCI_Pos)                   /*!< 0x00000002 */
#define EPWM_TBSTS_SYNCI                        EPWM_TBSTS_SYNCI_Msk                            
#define EPWM_TBSTS_CTRMAX_Pos                   (2U)
#define EPWM_TBSTS_CTRMAX_Msk                   (0x1UL<<EPWM_TBSTS_CTRMAX_Pos)                  /*!< 0x00000004 */
#define EPWM_TBSTS_CTRMAX                       EPWM_TBSTS_CTRMAX_Msk                           

/********************************* Bit definition for EPWM_CMPCTL register ****************************************/
#define EPWM_CMPCTL_LOADAMODE_Pos               (0U)
#define EPWM_CMPCTL_LOADAMODE_Msk               (0x3UL<<EPWM_CMPCTL_LOADAMODE_Pos)              /*!< 0x00000003 */
#define EPWM_CMPCTL_LOADAMODE                   EPWM_CMPCTL_LOADAMODE_Msk
#define EPWM_CMPCTL_LOADAMODE_0                 (0x1UL<<EPWM_CMPCTL_LOADAMODE_Pos)              /*!< 0x00000001 */
#define EPWM_CMPCTL_LOADAMODE_1                 (0x2UL<<EPWM_CMPCTL_LOADAMODE_Pos)              /*!< 0x00000002 */
#define EPWM_CMPCTL_LOADBMODE_Pos               (2U)
#define EPWM_CMPCTL_LOADBMODE_Msk               (0x3UL<<EPWM_CMPCTL_LOADBMODE_Pos)              /*!< 0x0000000C */
#define EPWM_CMPCTL_LOADBMODE                   EPWM_CMPCTL_LOADBMODE_Msk
#define EPWM_CMPCTL_LOADBMODE_0                 (0x1UL<<EPWM_CMPCTL_LOADBMODE_Pos)              /*!< 0x00000004 */
#define EPWM_CMPCTL_LOADBMODE_1                 (0x2UL<<EPWM_CMPCTL_LOADBMODE_Pos)              /*!< 0x00000008 */
#define EPWM_CMPCTL_SHDWAMODE_Pos               (4U)
#define EPWM_CMPCTL_SHDWAMODE_Msk               (0x1UL<<EPWM_CMPCTL_SHDWAMODE_Pos)              /*!< 0x00000010 */
#define EPWM_CMPCTL_SHDWAMODE                   EPWM_CMPCTL_SHDWAMODE_Msk                       
#define EPWM_CMPCTL_SHDWBMODE_Pos               (6U)
#define EPWM_CMPCTL_SHDWBMODE_Msk               (0x1UL<<EPWM_CMPCTL_SHDWBMODE_Pos)              /*!< 0x00000040 */
#define EPWM_CMPCTL_SHDWBMODE                   EPWM_CMPCTL_SHDWBMODE_Msk                       
#define EPWM_CMPCTL_SHDWAFULL_Pos               (8U)
#define EPWM_CMPCTL_SHDWAFULL_Msk               (0x1UL<<EPWM_CMPCTL_SHDWAFULL_Pos)              /*!< 0x00000100 */
#define EPWM_CMPCTL_SHDWAFULL                   EPWM_CMPCTL_SHDWAFULL_Msk                       
#define EPWM_CMPCTL_SHDWBFULL_Pos               (9U)
#define EPWM_CMPCTL_SHDWBFULL_Msk               (0x1UL<<EPWM_CMPCTL_SHDWBFULL_Pos)              /*!< 0x00000200 */
#define EPWM_CMPCTL_SHDWBFULL                   EPWM_CMPCTL_SHDWBFULL_Msk                       
#define EPWM_CMPCTL_LOADASYNC_Pos               (10U)
#define EPWM_CMPCTL_LOADASYNC_Msk               (0x3UL<<EPWM_CMPCTL_LOADASYNC_Pos)              /*!< 0x00000C00 */
#define EPWM_CMPCTL_LOADASYNC                   EPWM_CMPCTL_LOADASYNC_Msk
#define EPWM_CMPCTL_LOADASYNC_0                 (0x1UL<<EPWM_CMPCTL_LOADASYNC_Pos)              /*!< 0x00000400 */
#define EPWM_CMPCTL_LOADASYNC_1                 (0x2UL<<EPWM_CMPCTL_LOADASYNC_Pos)              /*!< 0x00000800 */
#define EPWM_CMPCTL_LOADBSYNC_Pos               (12U)
#define EPWM_CMPCTL_LOADBSYNC_Msk               (0x3UL<<EPWM_CMPCTL_LOADBSYNC_Pos)              /*!< 0x00003000 */
#define EPWM_CMPCTL_LOADBSYNC                   EPWM_CMPCTL_LOADBSYNC_Msk
#define EPWM_CMPCTL_LOADBSYNC_0                 (0x1UL<<EPWM_CMPCTL_LOADBSYNC_Pos)              /*!< 0x00001000 */
#define EPWM_CMPCTL_LOADBSYNC_1                 (0x2UL<<EPWM_CMPCTL_LOADBSYNC_Pos)              /*!< 0x00002000 */

/********************************* Bit definition for EPWM_CMPCTL2 register ***************************************/
#define EPWM_CMPCTL2_LOADCMODE_Pos              (0U)
#define EPWM_CMPCTL2_LOADCMODE_Msk              (0x3UL<<EPWM_CMPCTL2_LOADCMODE_Pos)             /*!< 0x00000003 */
#define EPWM_CMPCTL2_LOADCMODE                  EPWM_CMPCTL2_LOADCMODE_Msk
#define EPWM_CMPCTL2_LOADCMODE_0                (0x1UL<<EPWM_CMPCTL2_LOADCMODE_Pos)             /*!< 0x00000001 */
#define EPWM_CMPCTL2_LOADCMODE_1                (0x2UL<<EPWM_CMPCTL2_LOADCMODE_Pos)             /*!< 0x00000002 */
#define EPWM_CMPCTL2_LOADDMODE_Pos              (2U)
#define EPWM_CMPCTL2_LOADDMODE_Msk              (0x3UL<<EPWM_CMPCTL2_LOADDMODE_Pos)             /*!< 0x0000000C */
#define EPWM_CMPCTL2_LOADDMODE                  EPWM_CMPCTL2_LOADDMODE_Msk
#define EPWM_CMPCTL2_LOADDMODE_0                (0x1UL<<EPWM_CMPCTL2_LOADDMODE_Pos)             /*!< 0x00000004 */
#define EPWM_CMPCTL2_LOADDMODE_1                (0x2UL<<EPWM_CMPCTL2_LOADDMODE_Pos)             /*!< 0x00000008 */
#define EPWM_CMPCTL2_SHDWCMODE_Pos              (4U)
#define EPWM_CMPCTL2_SHDWCMODE_Msk              (0x1UL<<EPWM_CMPCTL2_SHDWCMODE_Pos)             /*!< 0x00000010 */
#define EPWM_CMPCTL2_SHDWCMODE                  EPWM_CMPCTL2_SHDWCMODE_Msk                      
#define EPWM_CMPCTL2_SHDWDMODE_Pos              (6U)
#define EPWM_CMPCTL2_SHDWDMODE_Msk              (0x1UL<<EPWM_CMPCTL2_SHDWDMODE_Pos)             /*!< 0x00000040 */
#define EPWM_CMPCTL2_SHDWDMODE                  EPWM_CMPCTL2_SHDWDMODE_Msk                      
#define EPWM_CMPCTL2_LOADCSYNC_Pos              (10U)
#define EPWM_CMPCTL2_LOADCSYNC_Msk              (0x3UL<<EPWM_CMPCTL2_LOADCSYNC_Pos)             /*!< 0x00000C00 */
#define EPWM_CMPCTL2_LOADCSYNC                  EPWM_CMPCTL2_LOADCSYNC_Msk
#define EPWM_CMPCTL2_LOADCSYNC_0                (0x1UL<<EPWM_CMPCTL2_LOADCSYNC_Pos)             /*!< 0x00000400 */
#define EPWM_CMPCTL2_LOADCSYNC_1                (0x2UL<<EPWM_CMPCTL2_LOADCSYNC_Pos)             /*!< 0x00000800 */
#define EPWM_CMPCTL2_LOADDSYNC_Pos              (12U)
#define EPWM_CMPCTL2_LOADDSYNC_Msk              (0x3UL<<EPWM_CMPCTL2_LOADDSYNC_Pos)             /*!< 0x00003000 */
#define EPWM_CMPCTL2_LOADDSYNC                  EPWM_CMPCTL2_LOADDSYNC_Msk
#define EPWM_CMPCTL2_LOADDSYNC_0                (0x1UL<<EPWM_CMPCTL2_LOADDSYNC_Pos)             /*!< 0x00001000 */
#define EPWM_CMPCTL2_LOADDSYNC_1                (0x2UL<<EPWM_CMPCTL2_LOADDSYNC_Pos)             /*!< 0x00002000 */

/********************************* Bit definition for EPWM_DBCTL register *****************************************/
#define EPWM_DBCTL_OUT_MODE_Pos                 (0U)
#define EPWM_DBCTL_OUT_MODE_Msk                 (0x3UL<<EPWM_DBCTL_OUT_MODE_Pos)                /*!< 0x00000003 */
#define EPWM_DBCTL_OUT_MODE                     EPWM_DBCTL_OUT_MODE_Msk
#define EPWM_DBCTL_OUT_MODE_0                   (0x1UL<<EPWM_DBCTL_OUT_MODE_Pos)                /*!< 0x00000001 */
#define EPWM_DBCTL_OUT_MODE_1                   (0x2UL<<EPWM_DBCTL_OUT_MODE_Pos)                /*!< 0x00000002 */
#define EPWM_DBCTL_POLSEL_Pos                   (2U)
#define EPWM_DBCTL_POLSEL_Msk                   (0x3UL<<EPWM_DBCTL_POLSEL_Pos)                  /*!< 0x0000000C */
#define EPWM_DBCTL_POLSEL                       EPWM_DBCTL_POLSEL_Msk
#define EPWM_DBCTL_POLSEL_0                     (0x1UL<<EPWM_DBCTL_POLSEL_Pos)                  /*!< 0x00000004 */
#define EPWM_DBCTL_POLSEL_1                     (0x2UL<<EPWM_DBCTL_POLSEL_Pos)                  /*!< 0x00000008 */
#define EPWM_DBCTL_IN_MODE_Pos                  (4U)
#define EPWM_DBCTL_IN_MODE_Msk                  (0x3UL<<EPWM_DBCTL_IN_MODE_Pos)                 /*!< 0x00000030 */
#define EPWM_DBCTL_IN_MODE                      EPWM_DBCTL_IN_MODE_Msk
#define EPWM_DBCTL_IN_MODE_0                    (0x1UL<<EPWM_DBCTL_IN_MODE_Pos)                 /*!< 0x00000010 */
#define EPWM_DBCTL_IN_MODE_1                    (0x2UL<<EPWM_DBCTL_IN_MODE_Pos)                 /*!< 0x00000020 */
#define EPWM_DBCTL_LOADREDMODE_Pos              (6U)
#define EPWM_DBCTL_LOADREDMODE_Msk              (0x3UL<<EPWM_DBCTL_LOADREDMODE_Pos)             /*!< 0x000000C0 */
#define EPWM_DBCTL_LOADREDMODE                  EPWM_DBCTL_LOADREDMODE_Msk
#define EPWM_DBCTL_LOADREDMODE_0                (0x1UL<<EPWM_DBCTL_LOADREDMODE_Pos)             /*!< 0x00000040 */
#define EPWM_DBCTL_LOADREDMODE_1                (0x2UL<<EPWM_DBCTL_LOADREDMODE_Pos)             /*!< 0x00000080 */
#define EPWM_DBCTL_LOADFEDMODE_Pos              (8U)
#define EPWM_DBCTL_LOADFEDMODE_Msk              (0x3UL<<EPWM_DBCTL_LOADFEDMODE_Pos)             /*!< 0x00000300 */
#define EPWM_DBCTL_LOADFEDMODE                  EPWM_DBCTL_LOADFEDMODE_Msk
#define EPWM_DBCTL_LOADFEDMODE_0                (0x1UL<<EPWM_DBCTL_LOADFEDMODE_Pos)             /*!< 0x00000100 */
#define EPWM_DBCTL_LOADFEDMODE_1                (0x2UL<<EPWM_DBCTL_LOADFEDMODE_Pos)             /*!< 0x00000200 */
#define EPWM_DBCTL_SHDWDBRED_MODE_Pos           (10U)
#define EPWM_DBCTL_SHDWDBRED_MODE_Msk           (0x1UL<<EPWM_DBCTL_SHDWDBRED_MODE_Pos)          /*!< 0x00000400 */
#define EPWM_DBCTL_SHDWDBRED_MODE               EPWM_DBCTL_SHDWDBRED_MODE_Msk                   
#define EPWM_DBCTL_SHDWDBFED_MODE_Pos           (11U)
#define EPWM_DBCTL_SHDWDBFED_MODE_Msk           (0x1UL<<EPWM_DBCTL_SHDWDBFED_MODE_Pos)          /*!< 0x00000800 */
#define EPWM_DBCTL_SHDWDBFED_MODE               EPWM_DBCTL_SHDWDBFED_MODE_Msk                   
#define EPWM_DBCTL_OUTSWAP_Pos                  (12U)
#define EPWM_DBCTL_OUTSWAP_Msk                  (0x3UL<<EPWM_DBCTL_OUTSWAP_Pos)                 /*!< 0x00003000 */
#define EPWM_DBCTL_OUTSWAP                      EPWM_DBCTL_OUTSWAP_Msk
#define EPWM_DBCTL_OUTSWAP_0                    (0x1UL<<EPWM_DBCTL_OUTSWAP_Pos)                 /*!< 0x00001000 */
#define EPWM_DBCTL_OUTSWAP_1                    (0x2UL<<EPWM_DBCTL_OUTSWAP_Pos)                 /*!< 0x00002000 */
#define EPWM_DBCTL_DEDB_MODE_Pos                (14U)
#define EPWM_DBCTL_DEDB_MODE_Msk                (0x1UL<<EPWM_DBCTL_DEDB_MODE_Pos)               /*!< 0x00004000 */
#define EPWM_DBCTL_DEDB_MODE                    EPWM_DBCTL_DEDB_MODE_Msk                        
#define EPWM_DBCTL_HALFCYCLE_Pos                (15U)
#define EPWM_DBCTL_HALFCYCLE_Msk                (0x1UL<<EPWM_DBCTL_HALFCYCLE_Pos)               /*!< 0x00008000 */
#define EPWM_DBCTL_HALFCYCLE                    EPWM_DBCTL_HALFCYCLE_Msk                        

/********************************* Bit definition for EPWM_DBCTL2 register ****************************************/
#define EPWM_DBCTL2_LOADDBCTLMODE_Pos           (0U)
#define EPWM_DBCTL2_LOADDBCTLMODE_Msk           (0x3UL<<EPWM_DBCTL2_LOADDBCTLMODE_Pos)          /*!< 0x00000003 */
#define EPWM_DBCTL2_LOADDBCTLMODE               EPWM_DBCTL2_LOADDBCTLMODE_Msk
#define EPWM_DBCTL2_LOADDBCTLMODE_0             (0x1UL<<EPWM_DBCTL2_LOADDBCTLMODE_Pos)          /*!< 0x00000001 */
#define EPWM_DBCTL2_LOADDBCTLMODE_1             (0x2UL<<EPWM_DBCTL2_LOADDBCTLMODE_Pos)          /*!< 0x00000002 */
#define EPWM_DBCTL2_SHDWDBCTLMODE_Pos           (2U)
#define EPWM_DBCTL2_SHDWDBCTLMODE_Msk           (0x1UL<<EPWM_DBCTL2_SHDWDBCTLMODE_Pos)          /*!< 0x00000004 */
#define EPWM_DBCTL2_SHDWDBCTLMODE               EPWM_DBCTL2_SHDWDBCTLMODE_Msk                   

/********************************* Bit definition for EPWM_AQCTL register *****************************************/
#define EPWM_AQCTL_LDAQAMODE_Pos                (0U)
#define EPWM_AQCTL_LDAQAMODE_Msk                (0x3UL<<EPWM_AQCTL_LDAQAMODE_Pos)               /*!< 0x00000003 */
#define EPWM_AQCTL_LDAQAMODE                    EPWM_AQCTL_LDAQAMODE_Msk
#define EPWM_AQCTL_LDAQAMODE_0                  (0x1UL<<EPWM_AQCTL_LDAQAMODE_Pos)               /*!< 0x00000001 */
#define EPWM_AQCTL_LDAQAMODE_1                  (0x2UL<<EPWM_AQCTL_LDAQAMODE_Pos)               /*!< 0x00000002 */
#define EPWM_AQCTL_LDAQBMODE_Pos                (2U)
#define EPWM_AQCTL_LDAQBMODE_Msk                (0x3UL<<EPWM_AQCTL_LDAQBMODE_Pos)               /*!< 0x0000000C */
#define EPWM_AQCTL_LDAQBMODE                    EPWM_AQCTL_LDAQBMODE_Msk
#define EPWM_AQCTL_LDAQBMODE_0                  (0x1UL<<EPWM_AQCTL_LDAQBMODE_Pos)               /*!< 0x00000004 */
#define EPWM_AQCTL_LDAQBMODE_1                  (0x2UL<<EPWM_AQCTL_LDAQBMODE_Pos)               /*!< 0x00000008 */
#define EPWM_AQCTL_SHDWAQAMODE_Pos              (4U)
#define EPWM_AQCTL_SHDWAQAMODE_Msk              (0x1UL<<EPWM_AQCTL_SHDWAQAMODE_Pos)             /*!< 0x00000010 */
#define EPWM_AQCTL_SHDWAQAMODE                  EPWM_AQCTL_SHDWAQAMODE_Msk                      
#define EPWM_AQCTL_SHDWAQBMODE_Pos              (6U)
#define EPWM_AQCTL_SHDWAQBMODE_Msk              (0x1UL<<EPWM_AQCTL_SHDWAQBMODE_Pos)             /*!< 0x00000040 */
#define EPWM_AQCTL_SHDWAQBMODE                  EPWM_AQCTL_SHDWAQBMODE_Msk                      
#define EPWM_AQCTL_LDAQASYNC_Pos                (8U)
#define EPWM_AQCTL_LDAQASYNC_Msk                (0x3UL<<EPWM_AQCTL_LDAQASYNC_Pos)               /*!< 0x00000300 */
#define EPWM_AQCTL_LDAQASYNC                    EPWM_AQCTL_LDAQASYNC_Msk
#define EPWM_AQCTL_LDAQASYNC_0                  (0x1UL<<EPWM_AQCTL_LDAQASYNC_Pos)               /*!< 0x00000100 */
#define EPWM_AQCTL_LDAQASYNC_1                  (0x2UL<<EPWM_AQCTL_LDAQASYNC_Pos)               /*!< 0x00000200 */
#define EPWM_AQCTL_LDAQBSYNC_Pos                (10U)
#define EPWM_AQCTL_LDAQBSYNC_Msk                (0x3UL<<EPWM_AQCTL_LDAQBSYNC_Pos)               /*!< 0x00000C00 */
#define EPWM_AQCTL_LDAQBSYNC                    EPWM_AQCTL_LDAQBSYNC_Msk
#define EPWM_AQCTL_LDAQBSYNC_0                  (0x1UL<<EPWM_AQCTL_LDAQBSYNC_Pos)               /*!< 0x00000400 */
#define EPWM_AQCTL_LDAQBSYNC_1                  (0x2UL<<EPWM_AQCTL_LDAQBSYNC_Pos)               /*!< 0x00000800 */

/********************************* Bit definition for EPWM_AQTSRCSEL register *************************************/
#define EPWM_AQTSRCSEL_T1SEL_Pos                (0U)
#define EPWM_AQTSRCSEL_T1SEL_Msk                (0xFUL<<EPWM_AQTSRCSEL_T1SEL_Pos)               /*!< 0x0000000F */
#define EPWM_AQTSRCSEL_T1SEL                    EPWM_AQTSRCSEL_T1SEL_Msk
#define EPWM_AQTSRCSEL_T1SEL_0                  (0x1UL<<EPWM_AQTSRCSEL_T1SEL_Pos)               /*!< 0x00000001 */
#define EPWM_AQTSRCSEL_T1SEL_1                  (0x2UL<<EPWM_AQTSRCSEL_T1SEL_Pos)               /*!< 0x00000002 */
#define EPWM_AQTSRCSEL_T1SEL_2                  (0x4UL<<EPWM_AQTSRCSEL_T1SEL_Pos)               /*!< 0x00000004 */
#define EPWM_AQTSRCSEL_T1SEL_3                  (0x8UL<<EPWM_AQTSRCSEL_T1SEL_Pos)               /*!< 0x00000008 */
#define EPWM_AQTSRCSEL_T2SEL_Pos                (4U)
#define EPWM_AQTSRCSEL_T2SEL_Msk                (0xFUL<<EPWM_AQTSRCSEL_T2SEL_Pos)               /*!< 0x000000F0 */
#define EPWM_AQTSRCSEL_T2SEL                    EPWM_AQTSRCSEL_T2SEL_Msk
#define EPWM_AQTSRCSEL_T2SEL_0                  (0x1UL<<EPWM_AQTSRCSEL_T2SEL_Pos)               /*!< 0x00000010 */
#define EPWM_AQTSRCSEL_T2SEL_1                  (0x2UL<<EPWM_AQTSRCSEL_T2SEL_Pos)               /*!< 0x00000020 */
#define EPWM_AQTSRCSEL_T2SEL_2                  (0x4UL<<EPWM_AQTSRCSEL_T2SEL_Pos)               /*!< 0x00000040 */
#define EPWM_AQTSRCSEL_T2SEL_3                  (0x8UL<<EPWM_AQTSRCSEL_T2SEL_Pos)               /*!< 0x00000080 */

/********************************* Bit definition for EPWM_PCCTL register *****************************************/
#define EPWM_PCCTL_CHPEN_Pos                    (0U)
#define EPWM_PCCTL_CHPEN_Msk                    (0x1UL<<EPWM_PCCTL_CHPEN_Pos)                   /*!< 0x00000001 */
#define EPWM_PCCTL_CHPEN                        EPWM_PCCTL_CHPEN_Msk                            
#define EPWM_PCCTL_OSHTWTH_Pos                  (1U)
#define EPWM_PCCTL_OSHTWTH_Msk                  (0xFUL<<EPWM_PCCTL_OSHTWTH_Pos)                 /*!< 0x0000001E */
#define EPWM_PCCTL_OSHTWTH                      EPWM_PCCTL_OSHTWTH_Msk
#define EPWM_PCCTL_OSHTWTH_0                    (0x1UL<<EPWM_PCCTL_OSHTWTH_Pos)                 /*!< 0x00000002 */
#define EPWM_PCCTL_OSHTWTH_1                    (0x2UL<<EPWM_PCCTL_OSHTWTH_Pos)                 /*!< 0x00000004 */
#define EPWM_PCCTL_OSHTWTH_2                    (0x4UL<<EPWM_PCCTL_OSHTWTH_Pos)                 /*!< 0x00000008 */
#define EPWM_PCCTL_OSHTWTH_3                    (0x8UL<<EPWM_PCCTL_OSHTWTH_Pos)                 /*!< 0x00000010 */
#define EPWM_PCCTL_CHPFREQ_Pos                  (5U)
#define EPWM_PCCTL_CHPFREQ_Msk                  (0x7UL<<EPWM_PCCTL_CHPFREQ_Pos)                 /*!< 0x000000E0 */
#define EPWM_PCCTL_CHPFREQ                      EPWM_PCCTL_CHPFREQ_Msk
#define EPWM_PCCTL_CHPFREQ_0                    (0x1UL<<EPWM_PCCTL_CHPFREQ_Pos)                 /*!< 0x00000020 */
#define EPWM_PCCTL_CHPFREQ_1                    (0x2UL<<EPWM_PCCTL_CHPFREQ_Pos)                 /*!< 0x00000040 */
#define EPWM_PCCTL_CHPFREQ_2                    (0x4UL<<EPWM_PCCTL_CHPFREQ_Pos)                 /*!< 0x00000080 */
#define EPWM_PCCTL_CHPDUTY_Pos                  (8U)
#define EPWM_PCCTL_CHPDUTY_Msk                  (0x7UL<<EPWM_PCCTL_CHPDUTY_Pos)                 /*!< 0x00000700 */
#define EPWM_PCCTL_CHPDUTY                      EPWM_PCCTL_CHPDUTY_Msk
#define EPWM_PCCTL_CHPDUTY_0                    (0x1UL<<EPWM_PCCTL_CHPDUTY_Pos)                 /*!< 0x00000100 */
#define EPWM_PCCTL_CHPDUTY_1                    (0x2UL<<EPWM_PCCTL_CHPDUTY_Pos)                 /*!< 0x00000200 */
#define EPWM_PCCTL_CHPDUTY_2                    (0x4UL<<EPWM_PCCTL_CHPDUTY_Pos)                 /*!< 0x00000400 */

/********************************* Bit definition for EPWM_VCAPCTL register ***************************************/
#define EPWM_VCAPCTL_VCAPE_Pos                  (0U)
#define EPWM_VCAPCTL_VCAPE_Msk                  (0x1UL<<EPWM_VCAPCTL_VCAPE_Pos)                 /*!< 0x00000001 */
#define EPWM_VCAPCTL_VCAPE                      EPWM_VCAPCTL_VCAPE_Msk                          
#define EPWM_VCAPCTL_VCAPSTART_Pos              (1U)
#define EPWM_VCAPCTL_VCAPSTART_Msk              (0x1UL<<EPWM_VCAPCTL_VCAPSTART_Pos)             /*!< 0x00000002 */
#define EPWM_VCAPCTL_VCAPSTART                  EPWM_VCAPCTL_VCAPSTART_Msk                      
#define EPWM_VCAPCTL_TRIGSEL_Pos                (2U)
#define EPWM_VCAPCTL_TRIGSEL_Msk                (0x7UL<<EPWM_VCAPCTL_TRIGSEL_Pos)               /*!< 0x0000001C */
#define EPWM_VCAPCTL_TRIGSEL                    EPWM_VCAPCTL_TRIGSEL_Msk
#define EPWM_VCAPCTL_TRIGSEL_0                  (0x1UL<<EPWM_VCAPCTL_TRIGSEL_Pos)               /*!< 0x00000004 */
#define EPWM_VCAPCTL_TRIGSEL_1                  (0x2UL<<EPWM_VCAPCTL_TRIGSEL_Pos)               /*!< 0x00000008 */
#define EPWM_VCAPCTL_TRIGSEL_2                  (0x4UL<<EPWM_VCAPCTL_TRIGSEL_Pos)               /*!< 0x00000010 */
#define EPWM_VCAPCTL_VDELAYDIV_Pos              (7U)
#define EPWM_VCAPCTL_VDELAYDIV_Msk              (0x7UL<<EPWM_VCAPCTL_VDELAYDIV_Pos)             /*!< 0x00000380 */
#define EPWM_VCAPCTL_VDELAYDIV                  EPWM_VCAPCTL_VDELAYDIV_Msk
#define EPWM_VCAPCTL_VDELAYDIV_0                (0x1UL<<EPWM_VCAPCTL_VDELAYDIV_Pos)             /*!< 0x00000080 */
#define EPWM_VCAPCTL_VDELAYDIV_1                (0x2UL<<EPWM_VCAPCTL_VDELAYDIV_Pos)             /*!< 0x00000100 */
#define EPWM_VCAPCTL_VDELAYDIV_2                (0x4UL<<EPWM_VCAPCTL_VDELAYDIV_Pos)             /*!< 0x00000200 */
#define EPWM_VCAPCTL_EDGEFILTDLYSEL_Pos         (10U)
#define EPWM_VCAPCTL_EDGEFILTDLYSEL_Msk         (0x1UL<<EPWM_VCAPCTL_EDGEFILTDLYSEL_Pos)        /*!< 0x00000400 */
#define EPWM_VCAPCTL_EDGEFILTDLYSEL             EPWM_VCAPCTL_EDGEFILTDLYSEL_Msk                 

/********************************* Bit definition for EPWM_VCNTCFG register ***************************************/
#define EPWM_VCNTCFG_STARTEDGE_Pos              (0U)
#define EPWM_VCNTCFG_STARTEDGE_Msk              (0xFUL<<EPWM_VCNTCFG_STARTEDGE_Pos)             /*!< 0x0000000F */
#define EPWM_VCNTCFG_STARTEDGE                  EPWM_VCNTCFG_STARTEDGE_Msk
#define EPWM_VCNTCFG_STARTEDGE_0                (0x1UL<<EPWM_VCNTCFG_STARTEDGE_Pos)             /*!< 0x00000001 */
#define EPWM_VCNTCFG_STARTEDGE_1                (0x2UL<<EPWM_VCNTCFG_STARTEDGE_Pos)             /*!< 0x00000002 */
#define EPWM_VCNTCFG_STARTEDGE_2                (0x4UL<<EPWM_VCNTCFG_STARTEDGE_Pos)             /*!< 0x00000004 */
#define EPWM_VCNTCFG_STARTEDGE_3                (0x8UL<<EPWM_VCNTCFG_STARTEDGE_Pos)             /*!< 0x00000008 */
#define EPWM_VCNTCFG_STARTEDGESTS_Pos           (7U)
#define EPWM_VCNTCFG_STARTEDGESTS_Msk           (0x1UL<<EPWM_VCNTCFG_STARTEDGESTS_Pos)          /*!< 0x00000080 */
#define EPWM_VCNTCFG_STARTEDGESTS               EPWM_VCNTCFG_STARTEDGESTS_Msk                   
#define EPWM_VCNTCFG_STOPEDGE_Pos               (8U)
#define EPWM_VCNTCFG_STOPEDGE_Msk               (0xFUL<<EPWM_VCNTCFG_STOPEDGE_Pos)              /*!< 0x00000F00 */
#define EPWM_VCNTCFG_STOPEDGE                   EPWM_VCNTCFG_STOPEDGE_Msk
#define EPWM_VCNTCFG_STOPEDGE_0                 (0x1UL<<EPWM_VCNTCFG_STOPEDGE_Pos)              /*!< 0x00000100 */
#define EPWM_VCNTCFG_STOPEDGE_1                 (0x2UL<<EPWM_VCNTCFG_STOPEDGE_Pos)              /*!< 0x00000200 */
#define EPWM_VCNTCFG_STOPEDGE_2                 (0x4UL<<EPWM_VCNTCFG_STOPEDGE_Pos)              /*!< 0x00000400 */
#define EPWM_VCNTCFG_STOPEDGE_3                 (0x8UL<<EPWM_VCNTCFG_STOPEDGE_Pos)              /*!< 0x00000800 */
#define EPWM_VCNTCFG_STOPEDGESTS_Pos            (15U)
#define EPWM_VCNTCFG_STOPEDGESTS_Msk            (0x1UL<<EPWM_VCNTCFG_STOPEDGESTS_Pos)           /*!< 0x00008000 */
#define EPWM_VCNTCFG_STOPEDGESTS                EPWM_VCNTCFG_STOPEDGESTS_Msk                    

/********************************* Bit definition for EPWM_HRCNFG register ****************************************/
#define EPWM_HRCNFG_EDGMODE_Pos                 (0U)
#define EPWM_HRCNFG_EDGMODE_Msk                 (0x3UL<<EPWM_HRCNFG_EDGMODE_Pos)                /*!< 0x00000003 */
#define EPWM_HRCNFG_EDGMODE                     EPWM_HRCNFG_EDGMODE_Msk
#define EPWM_HRCNFG_EDGMODE_0                   (0x1UL<<EPWM_HRCNFG_EDGMODE_Pos)                /*!< 0x00000001 */
#define EPWM_HRCNFG_EDGMODE_1                   (0x2UL<<EPWM_HRCNFG_EDGMODE_Pos)                /*!< 0x00000002 */
#define EPWM_HRCNFG_CTLMODE_Pos                 (2U)
#define EPWM_HRCNFG_CTLMODE_Msk                 (0x1UL<<EPWM_HRCNFG_CTLMODE_Pos)                /*!< 0x00000004 */
#define EPWM_HRCNFG_CTLMODE                     EPWM_HRCNFG_CTLMODE_Msk                         
#define EPWM_HRCNFG_HRLOAD_Pos                  (3U)
#define EPWM_HRCNFG_HRLOAD_Msk                  (0x3UL<<EPWM_HRCNFG_HRLOAD_Pos)                 /*!< 0x00000018 */
#define EPWM_HRCNFG_HRLOAD                      EPWM_HRCNFG_HRLOAD_Msk
#define EPWM_HRCNFG_HRLOAD_0                    (0x1UL<<EPWM_HRCNFG_HRLOAD_Pos)                 /*!< 0x00000008 */
#define EPWM_HRCNFG_HRLOAD_1                    (0x2UL<<EPWM_HRCNFG_HRLOAD_Pos)                 /*!< 0x00000010 */
#define EPWM_HRCNFG_SELOUTB_Pos                 (5U)
#define EPWM_HRCNFG_SELOUTB_Msk                 (0x1UL<<EPWM_HRCNFG_SELOUTB_Pos)                /*!< 0x00000020 */
#define EPWM_HRCNFG_SELOUTB                     EPWM_HRCNFG_SELOUTB_Msk                         
#define EPWM_HRCNFG_AUTOCONV_Pos                (6U)
#define EPWM_HRCNFG_AUTOCONV_Msk                (0x1UL<<EPWM_HRCNFG_AUTOCONV_Pos)               /*!< 0x00000040 */
#define EPWM_HRCNFG_AUTOCONV                    EPWM_HRCNFG_AUTOCONV_Msk                        
#define EPWM_HRCNFG_SWAPAB_Pos                  (7U)
#define EPWM_HRCNFG_SWAPAB_Msk                  (0x1UL<<EPWM_HRCNFG_SWAPAB_Pos)                 /*!< 0x00000080 */
#define EPWM_HRCNFG_SWAPAB                      EPWM_HRCNFG_SWAPAB_Msk                          
#define EPWM_HRCNFG_EDGMODEB_Pos                (8U)
#define EPWM_HRCNFG_EDGMODEB_Msk                (0x3UL<<EPWM_HRCNFG_EDGMODEB_Pos)               /*!< 0x00000300 */
#define EPWM_HRCNFG_EDGMODEB                    EPWM_HRCNFG_EDGMODEB_Msk
#define EPWM_HRCNFG_EDGMODEB_0                  (0x1UL<<EPWM_HRCNFG_EDGMODEB_Pos)               /*!< 0x00000100 */
#define EPWM_HRCNFG_EDGMODEB_1                  (0x2UL<<EPWM_HRCNFG_EDGMODEB_Pos)               /*!< 0x00000200 */
#define EPWM_HRCNFG_CTLMODEB_Pos                (10U)
#define EPWM_HRCNFG_CTLMODEB_Msk                (0x1UL<<EPWM_HRCNFG_CTLMODEB_Pos)               /*!< 0x00000400 */
#define EPWM_HRCNFG_CTLMODEB                    EPWM_HRCNFG_CTLMODEB_Msk                        
#define EPWM_HRCNFG_HRLOADB_Pos                 (11U)
#define EPWM_HRCNFG_HRLOADB_Msk                 (0x3UL<<EPWM_HRCNFG_HRLOADB_Pos)                /*!< 0x00001800 */
#define EPWM_HRCNFG_HRLOADB                     EPWM_HRCNFG_HRLOADB_Msk
#define EPWM_HRCNFG_HRLOADB_0                   (0x1UL<<EPWM_HRCNFG_HRLOADB_Pos)                /*!< 0x00000800 */
#define EPWM_HRCNFG_HRLOADB_1                   (0x2UL<<EPWM_HRCNFG_HRLOADB_Pos)                /*!< 0x00001000 */

/********************************* Bit definition for EPWM_HRPWR register *****************************************/
#define EPWM_HRPWR_CALPWRON_Pos                 (15U)
#define EPWM_HRPWR_CALPWRON_Msk                 (0x1UL<<EPWM_HRPWR_CALPWRON_Pos)                /*!< 0x00008000 */
#define EPWM_HRPWR_CALPWRON                     EPWM_HRPWR_CALPWRON_Msk                         

/********************************* Bit definition for EPWM_HRMSTEP register ***************************************/
#define EPWM_HRMSTEP_HRMSTEP_Pos                (0U)
#define EPWM_HRMSTEP_HRMSTEP_Msk                (0xFFUL<<EPWM_HRMSTEP_HRMSTEP_Pos)              /*!< 0x000000FF */
#define EPWM_HRMSTEP_HRMSTEP                    EPWM_HRMSTEP_HRMSTEP_Msk

/********************************* Bit definition for EPWM_HRCNFG2 register ***************************************/
#define EPWM_HRCNFG2_EDGMODEDB_Pos              (0U)
#define EPWM_HRCNFG2_EDGMODEDB_Msk              (0x3UL<<EPWM_HRCNFG2_EDGMODEDB_Pos)             /*!< 0x00000003 */
#define EPWM_HRCNFG2_EDGMODEDB                  EPWM_HRCNFG2_EDGMODEDB_Msk
#define EPWM_HRCNFG2_EDGMODEDB_0                (0x1UL<<EPWM_HRCNFG2_EDGMODEDB_Pos)             /*!< 0x00000001 */
#define EPWM_HRCNFG2_EDGMODEDB_1                (0x2UL<<EPWM_HRCNFG2_EDGMODEDB_Pos)             /*!< 0x00000002 */
#define EPWM_HRCNFG2_CTLMODEDBRED_Pos           (2U)
#define EPWM_HRCNFG2_CTLMODEDBRED_Msk           (0x3UL<<EPWM_HRCNFG2_CTLMODEDBRED_Pos)          /*!< 0x0000000C */
#define EPWM_HRCNFG2_CTLMODEDBRED               EPWM_HRCNFG2_CTLMODEDBRED_Msk
#define EPWM_HRCNFG2_CTLMODEDBRED_0             (0x1UL<<EPWM_HRCNFG2_CTLMODEDBRED_Pos)          /*!< 0x00000004 */
#define EPWM_HRCNFG2_CTLMODEDBRED_1             (0x2UL<<EPWM_HRCNFG2_CTLMODEDBRED_Pos)          /*!< 0x00000008 */
#define EPWM_HRCNFG2_CTLMODEDBFED_Pos           (4U)
#define EPWM_HRCNFG2_CTLMODEDBFED_Msk           (0x3UL<<EPWM_HRCNFG2_CTLMODEDBFED_Pos)          /*!< 0x00000030 */
#define EPWM_HRCNFG2_CTLMODEDBFED               EPWM_HRCNFG2_CTLMODEDBFED_Msk
#define EPWM_HRCNFG2_CTLMODEDBFED_0             (0x1UL<<EPWM_HRCNFG2_CTLMODEDBFED_Pos)          /*!< 0x00000010 */
#define EPWM_HRCNFG2_CTLMODEDBFED_1             (0x2UL<<EPWM_HRCNFG2_CTLMODEDBFED_Pos)          /*!< 0x00000020 */

/********************************* Bit definition for EPWM_HRPCTL register ****************************************/
#define EPWM_HRPCTL_HRPE_Pos                    (0U)
#define EPWM_HRPCTL_HRPE_Msk                    (0x1UL<<EPWM_HRPCTL_HRPE_Pos)                   /*!< 0x00000001 */
#define EPWM_HRPCTL_HRPE                        EPWM_HRPCTL_HRPE_Msk                            
#define EPWM_HRPCTL_EPWMSYNCSEL_Pos            (1U)
#define EPWM_HRPCTL_EPWMSYNCSEL_Msk            (0x1UL<<EPWM_HRPCTL_EPWMSYNCSEL_Pos)           /*!< 0x00000002 */
#define EPWM_HRPCTL_EPWMSYNCSEL                EPWM_HRPCTL_EPWMSYNCSEL_Msk                    
#define EPWM_HRPCTL_TBPHSHRLOADE_Pos            (2U)
#define EPWM_HRPCTL_TBPHSHRLOADE_Msk            (0x1UL<<EPWM_HRPCTL_TBPHSHRLOADE_Pos)           /*!< 0x00000004 */
#define EPWM_HRPCTL_TBPHSHRLOADE                EPWM_HRPCTL_TBPHSHRLOADE_Msk                    
#define EPWM_HRPCTL_EPWMSYNCSELX_Pos           (4U)
#define EPWM_HRPCTL_EPWMSYNCSELX_Msk           (0x7UL<<EPWM_HRPCTL_EPWMSYNCSELX_Pos)          /*!< 0x00000070 */
#define EPWM_HRPCTL_EPWMSYNCSELX               EPWM_HRPCTL_EPWMSYNCSELX_Msk
#define EPWM_HRPCTL_EPWMSYNCSELX_0             (0x1UL<<EPWM_HRPCTL_EPWMSYNCSELX_Pos)          /*!< 0x00000010 */
#define EPWM_HRPCTL_EPWMSYNCSELX_1             (0x2UL<<EPWM_HRPCTL_EPWMSYNCSELX_Pos)          /*!< 0x00000020 */
#define EPWM_HRPCTL_EPWMSYNCSELX_2             (0x4UL<<EPWM_HRPCTL_EPWMSYNCSELX_Pos)          /*!< 0x00000040 */

/********************************* Bit definition for EPWM_TRREM register *****************************************/
#define EPWM_TRREM_TREEM_Pos                    (0U)
#define EPWM_TRREM_TREEM_Msk                    (0x7FFUL<<EPWM_TRREM_TREEM_Pos)                 /*!< 0x000007FF */
#define EPWM_TRREM_TREEM                        EPWM_TRREM_TREEM_Msk

/********************************* Bit definition for EPWM_GLDCTL register ****************************************/
#define EPWM_GLDCTL_GLD_Pos                     (0U)
#define EPWM_GLDCTL_GLD_Msk                     (0x1UL<<EPWM_GLDCTL_GLD_Pos)                    /*!< 0x00000001 */
#define EPWM_GLDCTL_GLD                         EPWM_GLDCTL_GLD_Msk                             
#define EPWM_GLDCTL_GLDMODE_Pos                 (1U)
#define EPWM_GLDCTL_GLDMODE_Msk                 (0xFUL<<EPWM_GLDCTL_GLDMODE_Pos)                /*!< 0x0000001E */
#define EPWM_GLDCTL_GLDMODE                     EPWM_GLDCTL_GLDMODE_Msk
#define EPWM_GLDCTL_GLDMODE_0                   (0x1UL<<EPWM_GLDCTL_GLDMODE_Pos)                /*!< 0x00000002 */
#define EPWM_GLDCTL_GLDMODE_1                   (0x2UL<<EPWM_GLDCTL_GLDMODE_Pos)                /*!< 0x00000004 */
#define EPWM_GLDCTL_GLDMODE_2                   (0x4UL<<EPWM_GLDCTL_GLDMODE_Pos)                /*!< 0x00000008 */
#define EPWM_GLDCTL_GLDMODE_3                   (0x8UL<<EPWM_GLDCTL_GLDMODE_Pos)                /*!< 0x00000010 */
#define EPWM_GLDCTL_OSHTMODE_Pos                (5U)
#define EPWM_GLDCTL_OSHTMODE_Msk                (0x1UL<<EPWM_GLDCTL_OSHTMODE_Pos)               /*!< 0x00000020 */
#define EPWM_GLDCTL_OSHTMODE                    EPWM_GLDCTL_OSHTMODE_Msk                        
#define EPWM_GLDCTL_GLDPRD_Pos                  (7U)
#define EPWM_GLDCTL_GLDPRD_Msk                  (0x7UL<<EPWM_GLDCTL_GLDPRD_Pos)                 /*!< 0x00000380 */
#define EPWM_GLDCTL_GLDPRD                      EPWM_GLDCTL_GLDPRD_Msk
#define EPWM_GLDCTL_GLDPRD_0                    (0x1UL<<EPWM_GLDCTL_GLDPRD_Pos)                 /*!< 0x00000080 */
#define EPWM_GLDCTL_GLDPRD_1                    (0x2UL<<EPWM_GLDCTL_GLDPRD_Pos)                 /*!< 0x00000100 */
#define EPWM_GLDCTL_GLDPRD_2                    (0x4UL<<EPWM_GLDCTL_GLDPRD_Pos)                 /*!< 0x00000200 */
#define EPWM_GLDCTL_GLDCNT_Pos                  (10U)
#define EPWM_GLDCTL_GLDCNT_Msk                  (0x7UL<<EPWM_GLDCTL_GLDCNT_Pos)                 /*!< 0x00001C00 */
#define EPWM_GLDCTL_GLDCNT                      EPWM_GLDCTL_GLDCNT_Msk
#define EPWM_GLDCTL_GLDCNT_0                    (0x1UL<<EPWM_GLDCTL_GLDCNT_Pos)                 /*!< 0x00000400 */
#define EPWM_GLDCTL_GLDCNT_1                    (0x2UL<<EPWM_GLDCTL_GLDCNT_Pos)                 /*!< 0x00000800 */
#define EPWM_GLDCTL_GLDCNT_2                    (0x4UL<<EPWM_GLDCTL_GLDCNT_Pos)                 /*!< 0x00001000 */

/********************************* Bit definition for EPWM_GLDCFG register ****************************************/
#define EPWM_GLDCFG_TBPRD_TBPRDRHR_Pos          (0U)
#define EPWM_GLDCFG_TBPRD_TBPRDRHR_Msk          (0x1UL<<EPWM_GLDCFG_TBPRD_TBPRDRHR_Pos)         /*!< 0x00000001 */
#define EPWM_GLDCFG_TBPRD_TBPRDRHR              EPWM_GLDCFG_TBPRD_TBPRDRHR_Msk                  
#define EPWM_GLDCFG_CMPA_CMPAHR_Pos             (1U)
#define EPWM_GLDCFG_CMPA_CMPAHR_Msk             (0x1UL<<EPWM_GLDCFG_CMPA_CMPAHR_Pos)            /*!< 0x00000002 */
#define EPWM_GLDCFG_CMPA_CMPAHR                 EPWM_GLDCFG_CMPA_CMPAHR_Msk                     
#define EPWM_GLDCFG_CMPB_CMPBHR_Pos             (2U)
#define EPWM_GLDCFG_CMPB_CMPBHR_Msk             (0x1UL<<EPWM_GLDCFG_CMPB_CMPBHR_Pos)            /*!< 0x00000004 */
#define EPWM_GLDCFG_CMPB_CMPBHR                 EPWM_GLDCFG_CMPB_CMPBHR_Msk                     
#define EPWM_GLDCFG_CMPC_Pos                    (3U)
#define EPWM_GLDCFG_CMPC_Msk                    (0x1UL<<EPWM_GLDCFG_CMPC_Pos)                   /*!< 0x00000008 */
#define EPWM_GLDCFG_CMPC                        EPWM_GLDCFG_CMPC_Msk                            
#define EPWM_GLDCFG_CMPD_Pos                    (4U)
#define EPWM_GLDCFG_CMPD_Msk                    (0x1UL<<EPWM_GLDCFG_CMPD_Pos)                   /*!< 0x00000010 */
#define EPWM_GLDCFG_CMPD                        EPWM_GLDCFG_CMPD_Msk                            
#define EPWM_GLDCFG_DBRED_DBREDHR_Pos           (5U)
#define EPWM_GLDCFG_DBRED_DBREDHR_Msk           (0x1UL<<EPWM_GLDCFG_DBRED_DBREDHR_Pos)          /*!< 0x00000020 */
#define EPWM_GLDCFG_DBRED_DBREDHR               EPWM_GLDCFG_DBRED_DBREDHR_Msk                   
#define EPWM_GLDCFG_DBFED_DBFEDHR_Pos           (6U)
#define EPWM_GLDCFG_DBFED_DBFEDHR_Msk           (0x1UL<<EPWM_GLDCFG_DBFED_DBFEDHR_Pos)          /*!< 0x00000040 */
#define EPWM_GLDCFG_DBFED_DBFEDHR               EPWM_GLDCFG_DBFED_DBFEDHR_Msk                   
#define EPWM_GLDCFG_DBCTL_Pos                   (7U)
#define EPWM_GLDCFG_DBCTL_Msk                   (0x1UL<<EPWM_GLDCFG_DBCTL_Pos)                  /*!< 0x00000080 */
#define EPWM_GLDCFG_DBCTL                       EPWM_GLDCFG_DBCTL_Msk                           
#define EPWM_GLDCFG_AQCTLA_AQCTLA2_Pos          (8U)
#define EPWM_GLDCFG_AQCTLA_AQCTLA2_Msk          (0x1UL<<EPWM_GLDCFG_AQCTLA_AQCTLA2_Pos)         /*!< 0x00000100 */
#define EPWM_GLDCFG_AQCTLA_AQCTLA2              EPWM_GLDCFG_AQCTLA_AQCTLA2_Msk                  
#define EPWM_GLDCFG_AQCTLB_AQCTLB2_Pos          (9U)
#define EPWM_GLDCFG_AQCTLB_AQCTLB2_Msk          (0x1UL<<EPWM_GLDCFG_AQCTLB_AQCTLB2_Pos)         /*!< 0x00000200 */
#define EPWM_GLDCFG_AQCTLB_AQCTLB2              EPWM_GLDCFG_AQCTLB_AQCTLB2_Msk                  
#define EPWM_GLDCFG_AQCSPRC_Pos                 (10U)
#define EPWM_GLDCFG_AQCSPRC_Msk                 (0x1UL<<EPWM_GLDCFG_AQCSPRC_Pos)                /*!< 0x00000400 */
#define EPWM_GLDCFG_AQCSPRC                     EPWM_GLDCFG_AQCSPRC_Msk                         

/********************************* Bit definition for EPWM_EPWMLINK register ************************************/
#define EPWM_XLINK_TBPRDLINK_Pos                (0U)
#define EPWM_XLINK_TBPRDLINK_Msk                (0xFUL<<EPWM_XLINK_TBPRDLINK_Pos)          /*!< 0x0000000F */
#define EPWM_XLINK_TBPRDLINK                    EPWM_XLINK_TBPRDLINK_Msk
#define EPWM_XLINK_TBPRDLINK_0                  (0x1UL<<EPWM_XLINK_TBPRDLINK_Pos)          /*!< 0x00000001 */
#define EPWM_XLINK_TBPRDLINK_1                  (0x2UL<<EPWM_XLINK_TBPRDLINK_Pos)          /*!< 0x00000002 */
#define EPWM_XLINK_TBPRDLINK_2                  (0x4UL<<EPWM_XLINK_TBPRDLINK_Pos)          /*!< 0x00000004 */
#define EPWM_XLINK_TBPRDLINK_3                  (0x8UL<<EPWM_XLINK_TBPRDLINK_Pos)          /*!< 0x00000008 */
#define EPWM_XLINK_CMPALINK_Pos                 (4U)
#define EPWM_XLINK_CMPALINK_Msk                 (0xFUL<<EPWM_XLINK_CMPALINK_Pos)           /*!< 0x000000F0 */
#define EPWM_XLINK_CMPALINK                     EPWM_XLINK_CMPALINK_Msk
#define EPWM_XLINK_CMPALINK_0                   (0x1UL<<EPWM_XLINK_CMPALINK_Pos)           /*!< 0x00000010 */
#define EPWM_XLINK_CMPALINK_1                   (0x2UL<<EPWM_XLINK_CMPALINK_Pos)           /*!< 0x00000020 */
#define EPWM_XLINK_CMPALINK_2                   (0x4UL<<EPWM_XLINK_CMPALINK_Pos)           /*!< 0x00000040 */
#define EPWM_XLINK_CMPALINK_3                   (0x8UL<<EPWM_XLINK_CMPALINK_Pos)           /*!< 0x00000080 */
#define EPWM_XLINK_CMPBLINK_Pos                 (8U)
#define EPWM_XLINK_CMPBLINK_Msk                 (0xFUL<<EPWM_XLINK_CMPBLINK_Pos)           /*!< 0x00000F00 */
#define EPWM_XLINK_CMPBLINK                     EPWM_XLINK_CMPBLINK_Msk
#define EPWM_XLINK_CMPBLINK_0                   (0x1UL<<EPWM_XLINK_CMPBLINK_Pos)           /*!< 0x00000100 */
#define EPWM_XLINK_CMPBLINK_1                   (0x2UL<<EPWM_XLINK_CMPBLINK_Pos)           /*!< 0x00000200 */
#define EPWM_XLINK_CMPBLINK_2                   (0x4UL<<EPWM_XLINK_CMPBLINK_Pos)           /*!< 0x00000400 */
#define EPWM_XLINK_CMPBLINK_3                   (0x8UL<<EPWM_XLINK_CMPBLINK_Pos)           /*!< 0x00000800 */
#define EPWM_XLINK_CMPCLINK_Pos                 (12U)
#define EPWM_XLINK_CMPCLINK_Msk                 (0xFUL<<EPWM_XLINK_CMPCLINK_Pos)           /*!< 0x0000F000 */
#define EPWM_XLINK_CMPCLINK                     EPWM_XLINK_CMPCLINK_Msk
#define EPWM_XLINK_CMPCLINK_0                   (0x1UL<<EPWM_XLINK_CMPCLINK_Pos)           /*!< 0x00001000 */
#define EPWM_XLINK_CMPCLINK_1                   (0x2UL<<EPWM_XLINK_CMPCLINK_Pos)           /*!< 0x00002000 */
#define EPWM_XLINK_CMPCLINK_2                   (0x4UL<<EPWM_XLINK_CMPCLINK_Pos)           /*!< 0x00004000 */
#define EPWM_XLINK_CMPCLINK_3                   (0x8UL<<EPWM_XLINK_CMPCLINK_Pos)           /*!< 0x00008000 */
#define EPWM_XLINK_CMPDLINK_Pos                 (16U)
#define EPWM_XLINK_CMPDLINK_Msk                 (0xFUL<<EPWM_XLINK_CMPDLINK_Pos)           /*!< 0x000F0000 */
#define EPWM_XLINK_CMPDLINK                     EPWM_XLINK_CMPDLINK_Msk
#define EPWM_XLINK_CMPDLINK_0                   (0x1UL<<EPWM_XLINK_CMPDLINK_Pos)           /*!< 0x00010000 */
#define EPWM_XLINK_CMPDLINK_1                   (0x2UL<<EPWM_XLINK_CMPDLINK_Pos)           /*!< 0x00020000 */
#define EPWM_XLINK_CMPDLINK_2                   (0x4UL<<EPWM_XLINK_CMPDLINK_Pos)           /*!< 0x00040000 */
#define EPWM_XLINK_CMPDLINK_3                   (0x8UL<<EPWM_XLINK_CMPDLINK_Pos)           /*!< 0x00080000 */
#define EPWM_XLINK_GLDCTL2LINK_Pos              (28U)
#define EPWM_XLINK_GLDCTL2LINK_Msk              (0xFUL<<EPWM_XLINK_GLDCTL2LINK_Pos)        /*!< 0xF0000000 */
#define EPWM_XLINK_GLDCTL2LINK                  EPWM_XLINK_GLDCTL2LINK_Msk
#define EPWM_XLINK_GLDCTL2LINK_0                (0x1UL<<EPWM_XLINK_GLDCTL2LINK_Pos)        /*!< 0x10000000 */
#define EPWM_XLINK_GLDCTL2LINK_1                (0x2UL<<EPWM_XLINK_GLDCTL2LINK_Pos)        /*!< 0x20000000 */
#define EPWM_XLINK_GLDCTL2LINK_2                (0x4UL<<EPWM_XLINK_GLDCTL2LINK_Pos)        /*!< 0x40000000 */
#define EPWM_XLINK_GLDCTL2LINK_3                (0x8UL<<EPWM_XLINK_GLDCTL2LINK_Pos)        /*!< 0x80000000 */

/********************************* Bit definition for EPWM_AQCTLA register ****************************************/
#define EPWM_AQCTLA_ZRO_Pos                     (0U)
#define EPWM_AQCTLA_ZRO_Msk                     (0x3UL<<EPWM_AQCTLA_ZRO_Pos)                    /*!< 0x00000003 */
#define EPWM_AQCTLA_ZRO                         EPWM_AQCTLA_ZRO_Msk
#define EPWM_AQCTLA_ZRO_0                       (0x1UL<<EPWM_AQCTLA_ZRO_Pos)                    /*!< 0x00000001 */
#define EPWM_AQCTLA_ZRO_1                       (0x2UL<<EPWM_AQCTLA_ZRO_Pos)                    /*!< 0x00000002 */
#define EPWM_AQCTLA_PRD_Pos                     (2U)
#define EPWM_AQCTLA_PRD_Msk                     (0x3UL<<EPWM_AQCTLA_PRD_Pos)                    /*!< 0x0000000C */
#define EPWM_AQCTLA_PRD                         EPWM_AQCTLA_PRD_Msk
#define EPWM_AQCTLA_PRD_0                       (0x1UL<<EPWM_AQCTLA_PRD_Pos)                    /*!< 0x00000004 */
#define EPWM_AQCTLA_PRD_1                       (0x2UL<<EPWM_AQCTLA_PRD_Pos)                    /*!< 0x00000008 */
#define EPWM_AQCTLA_CAU_Pos                     (4U)
#define EPWM_AQCTLA_CAU_Msk                     (0x3UL<<EPWM_AQCTLA_CAU_Pos)                    /*!< 0x00000030 */
#define EPWM_AQCTLA_CAU                         EPWM_AQCTLA_CAU_Msk
#define EPWM_AQCTLA_CAU_0                       (0x1UL<<EPWM_AQCTLA_CAU_Pos)                    /*!< 0x00000010 */
#define EPWM_AQCTLA_CAU_1                       (0x2UL<<EPWM_AQCTLA_CAU_Pos)                    /*!< 0x00000020 */
#define EPWM_AQCTLA_CAD_Pos                     (6U)
#define EPWM_AQCTLA_CAD_Msk                     (0x3UL<<EPWM_AQCTLA_CAD_Pos)                    /*!< 0x000000C0 */
#define EPWM_AQCTLA_CAD                         EPWM_AQCTLA_CAD_Msk
#define EPWM_AQCTLA_CAD_0                       (0x1UL<<EPWM_AQCTLA_CAD_Pos)                    /*!< 0x00000040 */
#define EPWM_AQCTLA_CAD_1                       (0x2UL<<EPWM_AQCTLA_CAD_Pos)                    /*!< 0x00000080 */
#define EPWM_AQCTLA_CBU_Pos                     (8U)
#define EPWM_AQCTLA_CBU_Msk                     (0x3UL<<EPWM_AQCTLA_CBU_Pos)                    /*!< 0x00000300 */
#define EPWM_AQCTLA_CBU                         EPWM_AQCTLA_CBU_Msk
#define EPWM_AQCTLA_CBU_0                       (0x1UL<<EPWM_AQCTLA_CBU_Pos)                    /*!< 0x00000100 */
#define EPWM_AQCTLA_CBU_1                       (0x2UL<<EPWM_AQCTLA_CBU_Pos)                    /*!< 0x00000200 */
#define EPWM_AQCTLA_CBD_Pos                     (10U)
#define EPWM_AQCTLA_CBD_Msk                     (0x3UL<<EPWM_AQCTLA_CBD_Pos)                    /*!< 0x00000C00 */
#define EPWM_AQCTLA_CBD                         EPWM_AQCTLA_CBD_Msk
#define EPWM_AQCTLA_CBD_0                       (0x1UL<<EPWM_AQCTLA_CBD_Pos)                    /*!< 0x00000400 */
#define EPWM_AQCTLA_CBD_1                       (0x2UL<<EPWM_AQCTLA_CBD_Pos)                    /*!< 0x00000800 */

/********************************* Bit definition for EPWM_AQCTLA2 register ***************************************/
#define EPWM_AQCTLA2_T1U_Pos                    (0U)
#define EPWM_AQCTLA2_T1U_Msk                    (0x3UL<<EPWM_AQCTLA2_T1U_Pos)                   /*!< 0x00000003 */
#define EPWM_AQCTLA2_T1U                        EPWM_AQCTLA2_T1U_Msk
#define EPWM_AQCTLA2_T1U_0                      (0x1UL<<EPWM_AQCTLA2_T1U_Pos)                   /*!< 0x00000001 */
#define EPWM_AQCTLA2_T1U_1                      (0x2UL<<EPWM_AQCTLA2_T1U_Pos)                   /*!< 0x00000002 */
#define EPWM_AQCTLA2_T1D_Pos                    (2U)
#define EPWM_AQCTLA2_T1D_Msk                    (0x3UL<<EPWM_AQCTLA2_T1D_Pos)                   /*!< 0x0000000C */
#define EPWM_AQCTLA2_T1D                        EPWM_AQCTLA2_T1D_Msk
#define EPWM_AQCTLA2_T1D_0                      (0x1UL<<EPWM_AQCTLA2_T1D_Pos)                   /*!< 0x00000004 */
#define EPWM_AQCTLA2_T1D_1                      (0x2UL<<EPWM_AQCTLA2_T1D_Pos)                   /*!< 0x00000008 */
#define EPWM_AQCTLA2_T2U_Pos                    (4U)
#define EPWM_AQCTLA2_T2U_Msk                    (0x3UL<<EPWM_AQCTLA2_T2U_Pos)                   /*!< 0x00000030 */
#define EPWM_AQCTLA2_T2U                        EPWM_AQCTLA2_T2U_Msk
#define EPWM_AQCTLA2_T2U_0                      (0x1UL<<EPWM_AQCTLA2_T2U_Pos)                   /*!< 0x00000010 */
#define EPWM_AQCTLA2_T2U_1                      (0x2UL<<EPWM_AQCTLA2_T2U_Pos)                   /*!< 0x00000020 */
#define EPWM_AQCTLA2_T2D_Pos                    (6U)
#define EPWM_AQCTLA2_T2D_Msk                    (0x3UL<<EPWM_AQCTLA2_T2D_Pos)                   /*!< 0x000000C0 */
#define EPWM_AQCTLA2_T2D                        EPWM_AQCTLA2_T2D_Msk
#define EPWM_AQCTLA2_T2D_0                      (0x1UL<<EPWM_AQCTLA2_T2D_Pos)                   /*!< 0x00000040 */
#define EPWM_AQCTLA2_T2D_1                      (0x2UL<<EPWM_AQCTLA2_T2D_Pos)                   /*!< 0x00000080 */

/********************************* Bit definition for EPWM_AQCTLB register ****************************************/
#define EPWM_AQCTLB_ZRO_Pos                     (0U)
#define EPWM_AQCTLB_ZRO_Msk                     (0x3UL<<EPWM_AQCTLB_ZRO_Pos)                    /*!< 0x00000003 */
#define EPWM_AQCTLB_ZRO                         EPWM_AQCTLB_ZRO_Msk
#define EPWM_AQCTLB_ZRO_0                       (0x1UL<<EPWM_AQCTLB_ZRO_Pos)                    /*!< 0x00000001 */
#define EPWM_AQCTLB_ZRO_1                       (0x2UL<<EPWM_AQCTLB_ZRO_Pos)                    /*!< 0x00000002 */
#define EPWM_AQCTLB_PRD_Pos                     (2U)
#define EPWM_AQCTLB_PRD_Msk                     (0x3UL<<EPWM_AQCTLB_PRD_Pos)                    /*!< 0x0000000C */
#define EPWM_AQCTLB_PRD                         EPWM_AQCTLB_PRD_Msk
#define EPWM_AQCTLB_PRD_0                       (0x1UL<<EPWM_AQCTLB_PRD_Pos)                    /*!< 0x00000004 */
#define EPWM_AQCTLB_PRD_1                       (0x2UL<<EPWM_AQCTLB_PRD_Pos)                    /*!< 0x00000008 */
#define EPWM_AQCTLB_CAU_Pos                     (4U)
#define EPWM_AQCTLB_CAU_Msk                     (0x3UL<<EPWM_AQCTLB_CAU_Pos)                    /*!< 0x00000030 */
#define EPWM_AQCTLB_CAU                         EPWM_AQCTLB_CAU_Msk
#define EPWM_AQCTLB_CAU_0                       (0x1UL<<EPWM_AQCTLB_CAU_Pos)                    /*!< 0x00000010 */
#define EPWM_AQCTLB_CAU_1                       (0x2UL<<EPWM_AQCTLB_CAU_Pos)                    /*!< 0x00000020 */
#define EPWM_AQCTLB_CAD_Pos                     (6U)
#define EPWM_AQCTLB_CAD_Msk                     (0x3UL<<EPWM_AQCTLB_CAD_Pos)                    /*!< 0x000000C0 */
#define EPWM_AQCTLB_CAD                         EPWM_AQCTLB_CAD_Msk
#define EPWM_AQCTLB_CAD_0                       (0x1UL<<EPWM_AQCTLB_CAD_Pos)                    /*!< 0x00000040 */
#define EPWM_AQCTLB_CAD_1                       (0x2UL<<EPWM_AQCTLB_CAD_Pos)                    /*!< 0x00000080 */
#define EPWM_AQCTLB_CBU_Pos                     (8U)
#define EPWM_AQCTLB_CBU_Msk                     (0x3UL<<EPWM_AQCTLB_CBU_Pos)                    /*!< 0x00000300 */
#define EPWM_AQCTLB_CBU                         EPWM_AQCTLB_CBU_Msk
#define EPWM_AQCTLB_CBU_0                       (0x1UL<<EPWM_AQCTLB_CBU_Pos)                    /*!< 0x00000100 */
#define EPWM_AQCTLB_CBU_1                       (0x2UL<<EPWM_AQCTLB_CBU_Pos)                    /*!< 0x00000200 */
#define EPWM_AQCTLB_CBD_Pos                     (10U)
#define EPWM_AQCTLB_CBD_Msk                     (0x3UL<<EPWM_AQCTLB_CBD_Pos)                    /*!< 0x00000C00 */
#define EPWM_AQCTLB_CBD                         EPWM_AQCTLB_CBD_Msk
#define EPWM_AQCTLB_CBD_0                       (0x1UL<<EPWM_AQCTLB_CBD_Pos)                    /*!< 0x00000400 */
#define EPWM_AQCTLB_CBD_1                       (0x2UL<<EPWM_AQCTLB_CBD_Pos)                    /*!< 0x00000800 */

/********************************* Bit definition for EPWM_AQCTLB2 register ***************************************/
#define EPWM_AQCTLB2_T1U_Pos                    (0U)
#define EPWM_AQCTLB2_T1U_Msk                    (0x3UL<<EPWM_AQCTLB2_T1U_Pos)                   /*!< 0x00000003 */
#define EPWM_AQCTLB2_T1U                        EPWM_AQCTLB2_T1U_Msk
#define EPWM_AQCTLB2_T1U_0                      (0x1UL<<EPWM_AQCTLB2_T1U_Pos)                   /*!< 0x00000001 */
#define EPWM_AQCTLB2_T1U_1                      (0x2UL<<EPWM_AQCTLB2_T1U_Pos)                   /*!< 0x00000002 */
#define EPWM_AQCTLB2_T1D_Pos                    (2U)
#define EPWM_AQCTLB2_T1D_Msk                    (0x3UL<<EPWM_AQCTLB2_T1D_Pos)                   /*!< 0x0000000C */
#define EPWM_AQCTLB2_T1D                        EPWM_AQCTLB2_T1D_Msk
#define EPWM_AQCTLB2_T1D_0                      (0x1UL<<EPWM_AQCTLB2_T1D_Pos)                   /*!< 0x00000004 */
#define EPWM_AQCTLB2_T1D_1                      (0x2UL<<EPWM_AQCTLB2_T1D_Pos)                   /*!< 0x00000008 */
#define EPWM_AQCTLB2_T2U_Pos                    (4U)
#define EPWM_AQCTLB2_T2U_Msk                    (0x3UL<<EPWM_AQCTLB2_T2U_Pos)                   /*!< 0x00000030 */
#define EPWM_AQCTLB2_T2U                        EPWM_AQCTLB2_T2U_Msk
#define EPWM_AQCTLB2_T2U_0                      (0x1UL<<EPWM_AQCTLB2_T2U_Pos)                   /*!< 0x00000010 */
#define EPWM_AQCTLB2_T2U_1                      (0x2UL<<EPWM_AQCTLB2_T2U_Pos)                   /*!< 0x00000020 */
#define EPWM_AQCTLB2_T2D_Pos                    (6U)
#define EPWM_AQCTLB2_T2D_Msk                    (0x3UL<<EPWM_AQCTLB2_T2D_Pos)                   /*!< 0x000000C0 */
#define EPWM_AQCTLB2_T2D                        EPWM_AQCTLB2_T2D_Msk
#define EPWM_AQCTLB2_T2D_0                      (0x1UL<<EPWM_AQCTLB2_T2D_Pos)                   /*!< 0x00000040 */
#define EPWM_AQCTLB2_T2D_1                      (0x2UL<<EPWM_AQCTLB2_T2D_Pos)                   /*!< 0x00000080 */

/********************************* Bit definition for EPWM_AQSFRC register ****************************************/
#define EPWM_AQSFRC_ACTSFA_Pos                  (0U)
#define EPWM_AQSFRC_ACTSFA_Msk                  (0x3UL<<EPWM_AQSFRC_ACTSFA_Pos)                 /*!< 0x00000003 */
#define EPWM_AQSFRC_ACTSFA                      EPWM_AQSFRC_ACTSFA_Msk
#define EPWM_AQSFRC_ACTSFA_0                    (0x1UL<<EPWM_AQSFRC_ACTSFA_Pos)                 /*!< 0x00000001 */
#define EPWM_AQSFRC_ACTSFA_1                    (0x2UL<<EPWM_AQSFRC_ACTSFA_Pos)                 /*!< 0x00000002 */
#define EPWM_AQSFRC_OTSFA_Pos                   (2U)
#define EPWM_AQSFRC_OTSFA_Msk                   (0x1UL<<EPWM_AQSFRC_OTSFA_Pos)                  /*!< 0x00000004 */
#define EPWM_AQSFRC_OTSFA                       EPWM_AQSFRC_OTSFA_Msk                           
#define EPWM_AQSFRC_ACTSFB_Pos                  (3U)
#define EPWM_AQSFRC_ACTSFB_Msk                  (0x3UL<<EPWM_AQSFRC_ACTSFB_Pos)                 /*!< 0x00000018 */
#define EPWM_AQSFRC_ACTSFB                      EPWM_AQSFRC_ACTSFB_Msk
#define EPWM_AQSFRC_ACTSFB_0                    (0x1UL<<EPWM_AQSFRC_ACTSFB_Pos)                 /*!< 0x00000008 */
#define EPWM_AQSFRC_ACTSFB_1                    (0x2UL<<EPWM_AQSFRC_ACTSFB_Pos)                 /*!< 0x00000010 */
#define EPWM_AQSFRC_OTSFB_Pos                   (5U)
#define EPWM_AQSFRC_OTSFB_Msk                   (0x1UL<<EPWM_AQSFRC_OTSFB_Pos)                  /*!< 0x00000020 */
#define EPWM_AQSFRC_OTSFB                       EPWM_AQSFRC_OTSFB_Msk                           
#define EPWM_AQSFRC_RLDCSF_Pos                  (6U)
#define EPWM_AQSFRC_RLDCSF_Msk                  (0x3UL<<EPWM_AQSFRC_RLDCSF_Pos)                 /*!< 0x000000C0 */
#define EPWM_AQSFRC_RLDCSF                      EPWM_AQSFRC_RLDCSF_Msk
#define EPWM_AQSFRC_RLDCSF_0                    (0x1UL<<EPWM_AQSFRC_RLDCSF_Pos)                 /*!< 0x00000040 */
#define EPWM_AQSFRC_RLDCSF_1                    (0x2UL<<EPWM_AQSFRC_RLDCSF_Pos)                 /*!< 0x00000080 */

/********************************* Bit definition for EPWM_AQCSFRC register **************************************/
#define EPWM_AQCSFRC_CSFA_Pos                  (0U)
#define EPWM_AQCSFRC_CSFA_Msk                  (0x3UL<<EPWM_AQCSFRC_CSFA_Pos)                 /*!< 0x00000003 */
#define EPWM_AQCSFRC_CSFA                      EPWM_AQCSFRC_CSFA_Msk
#define EPWM_AQCSFRC_CSFA_0                    (0x1UL<<EPWM_AQCSFRC_CSFA_Pos)                 /*!< 0x00000001 */
#define EPWM_AQCSFRC_CSFA_1                    (0x2UL<<EPWM_AQCSFRC_CSFA_Pos)                 /*!< 0x00000002 */
#define EPWM_AQCSFRC_CSFB_Pos                  (2U)
#define EPWM_AQCSFRC_CSFB_Msk                  (0x3UL<<EPWM_AQCSFRC_CSFB_Pos)                 /*!< 0x0000000C */
#define EPWM_AQCSFRC_CSFB                      EPWM_AQCSFRC_CSFB_Msk
#define EPWM_AQCSFRC_CSFB_0                    (0x1UL<<EPWM_AQCSFRC_CSFB_Pos)                 /*!< 0x00000004 */
#define EPWM_AQCSFRC_CSFB_1                    (0x2UL<<EPWM_AQCSFRC_CSFB_Pos)                 /*!< 0x00000008 */

/********************************* Bit definition for EPWM_DBREDHR register ***************************************/
#define EPWM_DBREDHR_DBREDHR_Pos                (9U)
#define EPWM_DBREDHR_DBREDHR_Msk                (0x7FUL<<EPWM_DBREDHR_DBREDHR_Pos)              /*!< 0x0000FE00 */
#define EPWM_DBREDHR_DBREDHR                    EPWM_DBREDHR_DBREDHR_Msk

/********************************* Bit definition for EPWM_DBRED register *****************************************/
#define EPWM_DBRED_DBRED_Pos                    (0U)
#define EPWM_DBRED_DBRED_Msk                    (0x3FFFUL<<EPWM_DBRED_DBRED_Pos)                /*!< 0x00003FFF */
#define EPWM_DBRED_DBRED                        EPWM_DBRED_DBRED_Msk

/********************************* Bit definition for EPWM_DBFEDHR register ***************************************/
#define EPWM_DBFEDHR_DBFEDHR_Pos                (9U)
#define EPWM_DBFEDHR_DBFEDHR_Msk                (0x7FUL<<EPWM_DBFEDHR_DBFEDHR_Pos)              /*!< 0x0000FE00 */
#define EPWM_DBFEDHR_DBFEDHR                    EPWM_DBFEDHR_DBFEDHR_Msk

/********************************* Bit definition for EPWM_DBFED register *****************************************/
#define EPWM_DBFED_DBFED_Pos                    (0U)
#define EPWM_DBFED_DBFED_Msk                    (0x3FFFUL<<EPWM_DBFED_DBFED_Pos)                /*!< 0x00003FFF */
#define EPWM_DBFED_DBFED                        EPWM_DBFED_DBFED_Msk

/********************************* Bit definition for EPWM_TBPHS register *****************************************/
#define EPWM_TBPHS_TBPHSHR_Pos                  (0U)
#define EPWM_TBPHS_TBPHSHR_Msk                  (0xFFFFUL<<EPWM_TBPHS_TBPHSHR_Pos)              /*!< 0x0000FFFF */
#define EPWM_TBPHS_TBPHSHR                      EPWM_TBPHS_TBPHSHR_Msk
#define EPWM_TBPHS_TBPHS_Pos                    (16U)
#define EPWM_TBPHS_TBPHS_Msk                    (0xFFFFUL<<EPWM_TBPHS_TBPHS_Pos)                /*!< 0xFFFF0000 */
#define EPWM_TBPHS_TBPHS                        EPWM_TBPHS_TBPHS_Msk

/********************************* Bit definition for EPWM_TBPRDHR register ***************************************/
#define EPWM_TBPRDHR_TBPRDHR_Pos                (0U)
#define EPWM_TBPRDHR_TBPRDHR_Msk                (0xFFFFUL<<EPWM_TBPRDHR_TBPRDHR_Pos)            /*!< 0x0000FFFF */
#define EPWM_TBPRDHR_TBPRDHR                    EPWM_TBPRDHR_TBPRDHR_Msk

/********************************* Bit definition for EPWM_TBPRD register *****************************************/
#define EPWM_TBPRD_TBPRD_Pos                    (0U)
#define EPWM_TBPRD_TBPRD_Msk                    (0xFFFFUL<<EPWM_TBPRD_TBPRD_Pos)                /*!< 0x0000FFFF */
#define EPWM_TBPRD_TBPRD                        EPWM_TBPRD_TBPRD_Msk

/********************************* Bit definition for EPWM_CMPA register ******************************************/
#define EPWM_CMPA_CMPAHR_Pos                    (0U)
#define EPWM_CMPA_CMPAHR_Msk                    (0xFFFFUL<<EPWM_CMPA_CMPAHR_Pos)                /*!< 0x0000FFFF */
#define EPWM_CMPA_CMPAHR                        EPWM_CMPA_CMPAHR_Msk
#define EPWM_CMPA_CMPA_Pos                      (16U)
#define EPWM_CMPA_CMPA_Msk                      (0xFFFFUL<<EPWM_CMPA_CMPA_Pos)                  /*!< 0xFFFF0000 */
#define EPWM_CMPA_CMPA                          EPWM_CMPA_CMPA_Msk

/********************************* Bit definition for EPWM_CMPB register ******************************************/
#define EPWM_CMPB_CMPBHR_Pos                    (0U)
#define EPWM_CMPB_CMPBHR_Msk                    (0xFFFFUL<<EPWM_CMPB_CMPBHR_Pos)                /*!< 0x0000FFFF */
#define EPWM_CMPB_CMPBHR                        EPWM_CMPB_CMPBHR_Msk
#define EPWM_CMPB_CMPB_Pos                      (16U)
#define EPWM_CMPB_CMPB_Msk                      (0xFFFFUL<<EPWM_CMPB_CMPB_Pos)                  /*!< 0xFFFF0000 */
#define EPWM_CMPB_CMPB                          EPWM_CMPB_CMPB_Msk

/********************************* Bit definition for EPWM_CMPC register ******************************************/
#define EPWM_CMPC_CMPC_Pos                      (0U)
#define EPWM_CMPC_CMPC_Msk                      (0xFFFFUL<<EPWM_CMPC_CMPC_Pos)                  /*!< 0x0000FFFF */
#define EPWM_CMPC_CMPC                          EPWM_CMPC_CMPC_Msk

/********************************* Bit definition for EPWM_CMPD register ******************************************/
#define EPWM_CMPD_CMPD_Pos                      (0U)
#define EPWM_CMPD_CMPD_Msk                      (0xFFFFUL<<EPWM_CMPD_CMPD_Pos)                  /*!< 0x0000FFFF */
#define EPWM_CMPD_CMPD                          EPWM_CMPD_CMPD_Msk

/********************************* Bit definition for EPWM_GLDCTL2 register ***************************************/
#define EPWM_GLDCTL2_OSHTLD_Pos                 (0U)
#define EPWM_GLDCTL2_OSHTLD_Msk                 (0x1UL<<EPWM_GLDCTL2_OSHTLD_Pos)                /*!< 0x00000001 */
#define EPWM_GLDCTL2_OSHTLD                     EPWM_GLDCTL2_OSHTLD_Msk                         
#define EPWM_GLDCTL2_GFRCLD_Pos                 (1U)
#define EPWM_GLDCTL2_GFRCLD_Msk                 (0x1UL<<EPWM_GLDCTL2_GFRCLD_Pos)                /*!< 0x00000002 */
#define EPWM_GLDCTL2_GFRCLD                     EPWM_GLDCTL2_GFRCLD_Msk                         

/********************************* Bit definition for EPWM_SWVDELVAL register *************************************/
#define EPWM_SWVDELVAL_SWVDELVAL_Pos            (0U)
#define EPWM_SWVDELVAL_SWVDELVAL_Msk            (0xFFFFUL<<EPWM_SWVDELVAL_SWVDELVAL_Pos)        /*!< 0x0000FFFF */
#define EPWM_SWVDELVAL_SWVDELVAL                EPWM_SWVDELVAL_SWVDELVAL_Msk

/********************************* Bit definition for EPWM_TZSEL register *****************************************/
#define EPWM_TZSEL_CBC1_Pos                     (0U)
#define EPWM_TZSEL_CBC1_Msk                     (0x1UL<<EPWM_TZSEL_CBC1_Pos)                    /*!< 0x00000001 */
#define EPWM_TZSEL_CBC1                         EPWM_TZSEL_CBC1_Msk                             
#define EPWM_TZSEL_CBC2_Pos                     (1U)
#define EPWM_TZSEL_CBC2_Msk                     (0x1UL<<EPWM_TZSEL_CBC2_Pos)                    /*!< 0x00000002 */
#define EPWM_TZSEL_CBC2                         EPWM_TZSEL_CBC2_Msk                             
#define EPWM_TZSEL_CBC3_Pos                     (2U)
#define EPWM_TZSEL_CBC3_Msk                     (0x1UL<<EPWM_TZSEL_CBC3_Pos)                    /*!< 0x00000004 */
#define EPWM_TZSEL_CBC3                         EPWM_TZSEL_CBC3_Msk                             
#define EPWM_TZSEL_CBC4_Pos                     (3U)
#define EPWM_TZSEL_CBC4_Msk                     (0x1UL<<EPWM_TZSEL_CBC4_Pos)                    /*!< 0x00000008 */
#define EPWM_TZSEL_CBC4                         EPWM_TZSEL_CBC4_Msk                             
#define EPWM_TZSEL_CBC5_Pos                     (4U)
#define EPWM_TZSEL_CBC5_Msk                     (0x1UL<<EPWM_TZSEL_CBC5_Pos)                    /*!< 0x00000010 */
#define EPWM_TZSEL_CBC5                         EPWM_TZSEL_CBC5_Msk                             
#define EPWM_TZSEL_CBC6_Pos                     (5U)
#define EPWM_TZSEL_CBC6_Msk                     (0x1UL<<EPWM_TZSEL_CBC6_Pos)                    /*!< 0x00000020 */
#define EPWM_TZSEL_CBC6                         EPWM_TZSEL_CBC6_Msk                             
#define EPWM_TZSEL_DCAEVT2_Pos                  (6U)
#define EPWM_TZSEL_DCAEVT2_Msk                  (0x1UL<<EPWM_TZSEL_DCAEVT2_Pos)                 /*!< 0x00000040 */
#define EPWM_TZSEL_DCAEVT2                      EPWM_TZSEL_DCAEVT2_Msk                          
#define EPWM_TZSEL_DCBEVT2_Pos                  (7U)
#define EPWM_TZSEL_DCBEVT2_Msk                  (0x1UL<<EPWM_TZSEL_DCBEVT2_Pos)                 /*!< 0x00000080 */
#define EPWM_TZSEL_DCBEVT2                      EPWM_TZSEL_DCBEVT2_Msk                          
#define EPWM_TZSEL_OSHT1_Pos                    (8U)
#define EPWM_TZSEL_OSHT1_Msk                    (0x1UL<<EPWM_TZSEL_OSHT1_Pos)                   /*!< 0x00000100 */
#define EPWM_TZSEL_OSHT1                        EPWM_TZSEL_OSHT1_Msk                            
#define EPWM_TZSEL_OSHT2_Pos                    (9U)
#define EPWM_TZSEL_OSHT2_Msk                    (0x1UL<<EPWM_TZSEL_OSHT2_Pos)                   /*!< 0x00000200 */
#define EPWM_TZSEL_OSHT2                        EPWM_TZSEL_OSHT2_Msk                            
#define EPWM_TZSEL_OSHT3_Pos                    (10U)
#define EPWM_TZSEL_OSHT3_Msk                    (0x1UL<<EPWM_TZSEL_OSHT3_Pos)                   /*!< 0x00000400 */
#define EPWM_TZSEL_OSHT3                        EPWM_TZSEL_OSHT3_Msk                            
#define EPWM_TZSEL_OSHT4_Pos                    (11U)
#define EPWM_TZSEL_OSHT4_Msk                    (0x1UL<<EPWM_TZSEL_OSHT4_Pos)                   /*!< 0x00000800 */
#define EPWM_TZSEL_OSHT4                        EPWM_TZSEL_OSHT4_Msk                            
#define EPWM_TZSEL_OSHT5_Pos                    (12U)
#define EPWM_TZSEL_OSHT5_Msk                    (0x1UL<<EPWM_TZSEL_OSHT5_Pos)                   /*!< 0x00001000 */
#define EPWM_TZSEL_OSHT5                        EPWM_TZSEL_OSHT5_Msk                            
#define EPWM_TZSEL_OSHT6_Pos                    (13U)
#define EPWM_TZSEL_OSHT6_Msk                    (0x1UL<<EPWM_TZSEL_OSHT6_Pos)                   /*!< 0x00002000 */
#define EPWM_TZSEL_OSHT6                        EPWM_TZSEL_OSHT6_Msk                            
#define EPWM_TZSEL_DCAEVT1_Pos                  (14U)
#define EPWM_TZSEL_DCAEVT1_Msk                  (0x1UL<<EPWM_TZSEL_DCAEVT1_Pos)                 /*!< 0x00004000 */
#define EPWM_TZSEL_DCAEVT1                      EPWM_TZSEL_DCAEVT1_Msk                          
#define EPWM_TZSEL_DCBEVT1_Pos                  (15U)
#define EPWM_TZSEL_DCBEVT1_Msk                  (0x1UL<<EPWM_TZSEL_DCBEVT1_Pos)                 /*!< 0x00008000 */
#define EPWM_TZSEL_DCBEVT1                      EPWM_TZSEL_DCBEVT1_Msk                          

/********************************* Bit definition for EPWM_TZDCSEL register ***************************************/
#define EPWM_TZDCSEL_DCAEVT1_Pos                (0U)
#define EPWM_TZDCSEL_DCAEVT1_Msk                (0x7UL<<EPWM_TZDCSEL_DCAEVT1_Pos)               /*!< 0x00000007 */
#define EPWM_TZDCSEL_DCAEVT1                    EPWM_TZDCSEL_DCAEVT1_Msk
#define EPWM_TZDCSEL_DCAEVT1_0                  (0x1UL<<EPWM_TZDCSEL_DCAEVT1_Pos)               /*!< 0x00000001 */
#define EPWM_TZDCSEL_DCAEVT1_1                  (0x2UL<<EPWM_TZDCSEL_DCAEVT1_Pos)               /*!< 0x00000002 */
#define EPWM_TZDCSEL_DCAEVT1_2                  (0x4UL<<EPWM_TZDCSEL_DCAEVT1_Pos)               /*!< 0x00000004 */
#define EPWM_TZDCSEL_DCAEVT2_Pos                (3U)
#define EPWM_TZDCSEL_DCAEVT2_Msk                (0x7UL<<EPWM_TZDCSEL_DCAEVT2_Pos)               /*!< 0x00000038 */
#define EPWM_TZDCSEL_DCAEVT2                    EPWM_TZDCSEL_DCAEVT2_Msk
#define EPWM_TZDCSEL_DCAEVT2_0                  (0x1UL<<EPWM_TZDCSEL_DCAEVT2_Pos)               /*!< 0x00000008 */
#define EPWM_TZDCSEL_DCAEVT2_1                  (0x2UL<<EPWM_TZDCSEL_DCAEVT2_Pos)               /*!< 0x00000010 */
#define EPWM_TZDCSEL_DCAEVT2_2                  (0x4UL<<EPWM_TZDCSEL_DCAEVT2_Pos)               /*!< 0x00000020 */
#define EPWM_TZDCSEL_DCBEVT1_Pos                (6U)
#define EPWM_TZDCSEL_DCBEVT1_Msk                (0x7UL<<EPWM_TZDCSEL_DCBEVT1_Pos)               /*!< 0x000001C0 */
#define EPWM_TZDCSEL_DCBEVT1                    EPWM_TZDCSEL_DCBEVT1_Msk
#define EPWM_TZDCSEL_DCBEVT1_0                  (0x1UL<<EPWM_TZDCSEL_DCBEVT1_Pos)               /*!< 0x00000040 */
#define EPWM_TZDCSEL_DCBEVT1_1                  (0x2UL<<EPWM_TZDCSEL_DCBEVT1_Pos)               /*!< 0x00000080 */
#define EPWM_TZDCSEL_DCBEVT1_2                  (0x4UL<<EPWM_TZDCSEL_DCBEVT1_Pos)               /*!< 0x00000100 */
#define EPWM_TZDCSEL_DCBEVT2_Pos                (9U)
#define EPWM_TZDCSEL_DCBEVT2_Msk                (0x7UL<<EPWM_TZDCSEL_DCBEVT2_Pos)               /*!< 0x00000E00 */
#define EPWM_TZDCSEL_DCBEVT2                    EPWM_TZDCSEL_DCBEVT2_Msk
#define EPWM_TZDCSEL_DCBEVT2_0                  (0x1UL<<EPWM_TZDCSEL_DCBEVT2_Pos)               /*!< 0x00000200 */
#define EPWM_TZDCSEL_DCBEVT2_1                  (0x2UL<<EPWM_TZDCSEL_DCBEVT2_Pos)               /*!< 0x00000400 */
#define EPWM_TZDCSEL_DCBEVT2_2                  (0x4UL<<EPWM_TZDCSEL_DCBEVT2_Pos)               /*!< 0x00000800 */

/********************************* Bit definition for EPWM_TZCTL register *****************************************/
#define EPWM_TZCTL_TZA_Pos                      (0U)
#define EPWM_TZCTL_TZA_Msk                      (0x3UL<<EPWM_TZCTL_TZA_Pos)                     /*!< 0x00000003 */
#define EPWM_TZCTL_TZA                          EPWM_TZCTL_TZA_Msk
#define EPWM_TZCTL_TZA_0                        (0x1UL<<EPWM_TZCTL_TZA_Pos)                     /*!< 0x00000001 */
#define EPWM_TZCTL_TZA_1                        (0x2UL<<EPWM_TZCTL_TZA_Pos)                     /*!< 0x00000002 */
#define EPWM_TZCTL_TZB_Pos                      (2U)
#define EPWM_TZCTL_TZB_Msk                      (0x3UL<<EPWM_TZCTL_TZB_Pos)                     /*!< 0x0000000C */
#define EPWM_TZCTL_TZB                          EPWM_TZCTL_TZB_Msk
#define EPWM_TZCTL_TZB_0                        (0x1UL<<EPWM_TZCTL_TZB_Pos)                     /*!< 0x00000004 */
#define EPWM_TZCTL_TZB_1                        (0x2UL<<EPWM_TZCTL_TZB_Pos)                     /*!< 0x00000008 */
#define EPWM_TZCTL_DCAEVT1_Pos                  (4U)
#define EPWM_TZCTL_DCAEVT1_Msk                  (0x3UL<<EPWM_TZCTL_DCAEVT1_Pos)                 /*!< 0x00000030 */
#define EPWM_TZCTL_DCAEVT1                      EPWM_TZCTL_DCAEVT1_Msk
#define EPWM_TZCTL_DCAEVT1_0                    (0x1UL<<EPWM_TZCTL_DCAEVT1_Pos)                 /*!< 0x00000010 */
#define EPWM_TZCTL_DCAEVT1_1                    (0x2UL<<EPWM_TZCTL_DCAEVT1_Pos)                 /*!< 0x00000020 */
#define EPWM_TZCTL_DCAEVT2_Pos                  (6U)
#define EPWM_TZCTL_DCAEVT2_Msk                  (0x3UL<<EPWM_TZCTL_DCAEVT2_Pos)                 /*!< 0x000000C0 */
#define EPWM_TZCTL_DCAEVT2                      EPWM_TZCTL_DCAEVT2_Msk
#define EPWM_TZCTL_DCAEVT2_0                    (0x1UL<<EPWM_TZCTL_DCAEVT2_Pos)                 /*!< 0x00000040 */
#define EPWM_TZCTL_DCAEVT2_1                    (0x2UL<<EPWM_TZCTL_DCAEVT2_Pos)                 /*!< 0x00000080 */
#define EPWM_TZCTL_DCBEVT1_Pos                  (8U)
#define EPWM_TZCTL_DCBEVT1_Msk                  (0x3UL<<EPWM_TZCTL_DCBEVT1_Pos)                 /*!< 0x00000300 */
#define EPWM_TZCTL_DCBEVT1                      EPWM_TZCTL_DCBEVT1_Msk
#define EPWM_TZCTL_DCBEVT1_0                    (0x1UL<<EPWM_TZCTL_DCBEVT1_Pos)                 /*!< 0x00000100 */
#define EPWM_TZCTL_DCBEVT1_1                    (0x2UL<<EPWM_TZCTL_DCBEVT1_Pos)                 /*!< 0x00000200 */
#define EPWM_TZCTL_DCBEVT2_Pos                  (10U)
#define EPWM_TZCTL_DCBEVT2_Msk                  (0x3UL<<EPWM_TZCTL_DCBEVT2_Pos)                 /*!< 0x00000C00 */
#define EPWM_TZCTL_DCBEVT2                      EPWM_TZCTL_DCBEVT2_Msk
#define EPWM_TZCTL_DCBEVT2_0                    (0x1UL<<EPWM_TZCTL_DCBEVT2_Pos)                 /*!< 0x00000400 */
#define EPWM_TZCTL_DCBEVT2_1                    (0x2UL<<EPWM_TZCTL_DCBEVT2_Pos)                 /*!< 0x00000800 */

/********************************* Bit definition for EPWM_TZCTL2 register ****************************************/
#define EPWM_TZCTL2_TZAU_Pos                    (0U)
#define EPWM_TZCTL2_TZAU_Msk                    (0x7UL<<EPWM_TZCTL2_TZAU_Pos)                   /*!< 0x00000007 */
#define EPWM_TZCTL2_TZAU                        EPWM_TZCTL2_TZAU_Msk
#define EPWM_TZCTL2_TZAU_0                      (0x1UL<<EPWM_TZCTL2_TZAU_Pos)                   /*!< 0x00000001 */
#define EPWM_TZCTL2_TZAU_1                      (0x2UL<<EPWM_TZCTL2_TZAU_Pos)                   /*!< 0x00000002 */
#define EPWM_TZCTL2_TZAU_2                      (0x4UL<<EPWM_TZCTL2_TZAU_Pos)                   /*!< 0x00000004 */
#define EPWM_TZCTL2_TZAD_Pos                    (3U)
#define EPWM_TZCTL2_TZAD_Msk                    (0x7UL<<EPWM_TZCTL2_TZAD_Pos)                   /*!< 0x00000038 */
#define EPWM_TZCTL2_TZAD                        EPWM_TZCTL2_TZAD_Msk
#define EPWM_TZCTL2_TZAD_0                      (0x1UL<<EPWM_TZCTL2_TZAD_Pos)                   /*!< 0x00000008 */
#define EPWM_TZCTL2_TZAD_1                      (0x2UL<<EPWM_TZCTL2_TZAD_Pos)                   /*!< 0x00000010 */
#define EPWM_TZCTL2_TZAD_2                      (0x4UL<<EPWM_TZCTL2_TZAD_Pos)                   /*!< 0x00000020 */
#define EPWM_TZCTL2_TZBU_Pos                    (6U)
#define EPWM_TZCTL2_TZBU_Msk                    (0x7UL<<EPWM_TZCTL2_TZBU_Pos)                   /*!< 0x000001C0 */
#define EPWM_TZCTL2_TZBU                        EPWM_TZCTL2_TZBU_Msk
#define EPWM_TZCTL2_TZBU_0                      (0x1UL<<EPWM_TZCTL2_TZBU_Pos)                   /*!< 0x00000040 */
#define EPWM_TZCTL2_TZBU_1                      (0x2UL<<EPWM_TZCTL2_TZBU_Pos)                   /*!< 0x00000080 */
#define EPWM_TZCTL2_TZBU_2                      (0x4UL<<EPWM_TZCTL2_TZBU_Pos)                   /*!< 0x00000100 */
#define EPWM_TZCTL2_TZBD_Pos                    (9U)
#define EPWM_TZCTL2_TZBD_Msk                    (0x7UL<<EPWM_TZCTL2_TZBD_Pos)                   /*!< 0x00000E00 */
#define EPWM_TZCTL2_TZBD                        EPWM_TZCTL2_TZBD_Msk
#define EPWM_TZCTL2_TZBD_0                      (0x1UL<<EPWM_TZCTL2_TZBD_Pos)                   /*!< 0x00000200 */
#define EPWM_TZCTL2_TZBD_1                      (0x2UL<<EPWM_TZCTL2_TZBD_Pos)                   /*!< 0x00000400 */
#define EPWM_TZCTL2_TZBD_2                      (0x4UL<<EPWM_TZCTL2_TZBD_Pos)                   /*!< 0x00000800 */
#define EPWM_TZCTL2_ETZE_Pos                    (15U)
#define EPWM_TZCTL2_ETZE_Msk                    (0x1UL<<EPWM_TZCTL2_ETZE_Pos)                   /*!< 0x00008000 */
#define EPWM_TZCTL2_ETZE                        EPWM_TZCTL2_ETZE_Msk                            

/********************************* Bit definition for EPWM_TZCTLDCA register **************************************/
#define EPWM_TZCTLDCA_DCAEVT1U_Pos              (0U)
#define EPWM_TZCTLDCA_DCAEVT1U_Msk              (0x7UL<<EPWM_TZCTLDCA_DCAEVT1U_Pos)             /*!< 0x00000007 */
#define EPWM_TZCTLDCA_DCAEVT1U                  EPWM_TZCTLDCA_DCAEVT1U_Msk
#define EPWM_TZCTLDCA_DCAEVT1U_0                (0x1UL<<EPWM_TZCTLDCA_DCAEVT1U_Pos)             /*!< 0x00000001 */
#define EPWM_TZCTLDCA_DCAEVT1U_1                (0x2UL<<EPWM_TZCTLDCA_DCAEVT1U_Pos)             /*!< 0x00000002 */
#define EPWM_TZCTLDCA_DCAEVT1U_2                (0x4UL<<EPWM_TZCTLDCA_DCAEVT1U_Pos)             /*!< 0x00000004 */
#define EPWM_TZCTLDCA_DCAEVT1D_Pos              (3U)
#define EPWM_TZCTLDCA_DCAEVT1D_Msk              (0x7UL<<EPWM_TZCTLDCA_DCAEVT1D_Pos)             /*!< 0x00000038 */
#define EPWM_TZCTLDCA_DCAEVT1D                  EPWM_TZCTLDCA_DCAEVT1D_Msk
#define EPWM_TZCTLDCA_DCAEVT1D_0                (0x1UL<<EPWM_TZCTLDCA_DCAEVT1D_Pos)             /*!< 0x00000008 */
#define EPWM_TZCTLDCA_DCAEVT1D_1                (0x2UL<<EPWM_TZCTLDCA_DCAEVT1D_Pos)             /*!< 0x00000010 */
#define EPWM_TZCTLDCA_DCAEVT1D_2                (0x4UL<<EPWM_TZCTLDCA_DCAEVT1D_Pos)             /*!< 0x00000020 */
#define EPWM_TZCTLDCA_DCAEVT2U_Pos              (6U)
#define EPWM_TZCTLDCA_DCAEVT2U_Msk              (0x7UL<<EPWM_TZCTLDCA_DCAEVT2U_Pos)             /*!< 0x000001C0 */
#define EPWM_TZCTLDCA_DCAEVT2U                  EPWM_TZCTLDCA_DCAEVT2U_Msk
#define EPWM_TZCTLDCA_DCAEVT2U_0                (0x1UL<<EPWM_TZCTLDCA_DCAEVT2U_Pos)             /*!< 0x00000040 */
#define EPWM_TZCTLDCA_DCAEVT2U_1                (0x2UL<<EPWM_TZCTLDCA_DCAEVT2U_Pos)             /*!< 0x00000080 */
#define EPWM_TZCTLDCA_DCAEVT2U_2                (0x4UL<<EPWM_TZCTLDCA_DCAEVT2U_Pos)             /*!< 0x00000100 */
#define EPWM_TZCTLDCA_DCAEVT2D_Pos              (9U)
#define EPWM_TZCTLDCA_DCAEVT2D_Msk              (0x7UL<<EPWM_TZCTLDCA_DCAEVT2D_Pos)             /*!< 0x00000E00 */
#define EPWM_TZCTLDCA_DCAEVT2D                  EPWM_TZCTLDCA_DCAEVT2D_Msk
#define EPWM_TZCTLDCA_DCAEVT2D_0                (0x1UL<<EPWM_TZCTLDCA_DCAEVT2D_Pos)             /*!< 0x00000200 */
#define EPWM_TZCTLDCA_DCAEVT2D_1                (0x2UL<<EPWM_TZCTLDCA_DCAEVT2D_Pos)             /*!< 0x00000400 */
#define EPWM_TZCTLDCA_DCAEVT2D_2                (0x4UL<<EPWM_TZCTLDCA_DCAEVT2D_Pos)             /*!< 0x00000800 */

/********************************* Bit definition for EPWM_TZCTLDCB register **************************************/
#define EPWM_TZCTLDCB_DCBEVT1U_Pos              (0U)
#define EPWM_TZCTLDCB_DCBEVT1U_Msk              (0x7UL<<EPWM_TZCTLDCB_DCBEVT1U_Pos)             /*!< 0x00000007 */
#define EPWM_TZCTLDCB_DCBEVT1U                  EPWM_TZCTLDCB_DCBEVT1U_Msk
#define EPWM_TZCTLDCB_DCBEVT1U_0                (0x1UL<<EPWM_TZCTLDCB_DCBEVT1U_Pos)             /*!< 0x00000001 */
#define EPWM_TZCTLDCB_DCBEVT1U_1                (0x2UL<<EPWM_TZCTLDCB_DCBEVT1U_Pos)             /*!< 0x00000002 */
#define EPWM_TZCTLDCB_DCBEVT1U_2                (0x4UL<<EPWM_TZCTLDCB_DCBEVT1U_Pos)             /*!< 0x00000004 */
#define EPWM_TZCTLDCB_DCBEVT1D_Pos              (3U)
#define EPWM_TZCTLDCB_DCBEVT1D_Msk              (0x7UL<<EPWM_TZCTLDCB_DCBEVT1D_Pos)             /*!< 0x00000038 */
#define EPWM_TZCTLDCB_DCBEVT1D                  EPWM_TZCTLDCB_DCBEVT1D_Msk
#define EPWM_TZCTLDCB_DCBEVT1D_0                (0x1UL<<EPWM_TZCTLDCB_DCBEVT1D_Pos)             /*!< 0x00000008 */
#define EPWM_TZCTLDCB_DCBEVT1D_1                (0x2UL<<EPWM_TZCTLDCB_DCBEVT1D_Pos)             /*!< 0x00000010 */
#define EPWM_TZCTLDCB_DCBEVT1D_2                (0x4UL<<EPWM_TZCTLDCB_DCBEVT1D_Pos)             /*!< 0x00000020 */
#define EPWM_TZCTLDCB_DCBEVT2U_Pos              (6U)
#define EPWM_TZCTLDCB_DCBEVT2U_Msk              (0x7UL<<EPWM_TZCTLDCB_DCBEVT2U_Pos)             /*!< 0x000001C0 */
#define EPWM_TZCTLDCB_DCBEVT2U                  EPWM_TZCTLDCB_DCBEVT2U_Msk
#define EPWM_TZCTLDCB_DCBEVT2U_0                (0x1UL<<EPWM_TZCTLDCB_DCBEVT2U_Pos)             /*!< 0x00000040 */
#define EPWM_TZCTLDCB_DCBEVT2U_1                (0x2UL<<EPWM_TZCTLDCB_DCBEVT2U_Pos)             /*!< 0x00000080 */
#define EPWM_TZCTLDCB_DCBEVT2U_2                (0x4UL<<EPWM_TZCTLDCB_DCBEVT2U_Pos)             /*!< 0x00000100 */
#define EPWM_TZCTLDCB_DCBEVT2D_Pos              (9U)
#define EPWM_TZCTLDCB_DCBEVT2D_Msk              (0x7UL<<EPWM_TZCTLDCB_DCBEVT2D_Pos)             /*!< 0x00000E00 */
#define EPWM_TZCTLDCB_DCBEVT2D                  EPWM_TZCTLDCB_DCBEVT2D_Msk
#define EPWM_TZCTLDCB_DCBEVT2D_0                (0x1UL<<EPWM_TZCTLDCB_DCBEVT2D_Pos)             /*!< 0x00000200 */
#define EPWM_TZCTLDCB_DCBEVT2D_1                (0x2UL<<EPWM_TZCTLDCB_DCBEVT2D_Pos)             /*!< 0x00000400 */
#define EPWM_TZCTLDCB_DCBEVT2D_2                (0x4UL<<EPWM_TZCTLDCB_DCBEVT2D_Pos)             /*!< 0x00000800 */

/********************************* Bit definition for EPWM_TZEINT register ****************************************/
#define EPWM_TZEINT_CBC_Pos                     (1U)
#define EPWM_TZEINT_CBC_Msk                     (0x1UL<<EPWM_TZEINT_CBC_Pos)                    /*!< 0x00000002 */
#define EPWM_TZEINT_CBC                         EPWM_TZEINT_CBC_Msk                             
#define EPWM_TZEINT_OST_Pos                     (2U)
#define EPWM_TZEINT_OST_Msk                     (0x1UL<<EPWM_TZEINT_OST_Pos)                    /*!< 0x00000004 */
#define EPWM_TZEINT_OST                         EPWM_TZEINT_OST_Msk                             
#define EPWM_TZEINT_DCAEVT1_Pos                 (3U)
#define EPWM_TZEINT_DCAEVT1_Msk                 (0x1UL<<EPWM_TZEINT_DCAEVT1_Pos)                /*!< 0x00000008 */
#define EPWM_TZEINT_DCAEVT1                     EPWM_TZEINT_DCAEVT1_Msk                         
#define EPWM_TZEINT_DCAEVT2_Pos                 (4U)
#define EPWM_TZEINT_DCAEVT2_Msk                 (0x1UL<<EPWM_TZEINT_DCAEVT2_Pos)                /*!< 0x00000010 */
#define EPWM_TZEINT_DCAEVT2                     EPWM_TZEINT_DCAEVT2_Msk                         
#define EPWM_TZEINT_DCBEVT1_Pos                 (5U)
#define EPWM_TZEINT_DCBEVT1_Msk                 (0x1UL<<EPWM_TZEINT_DCBEVT1_Pos)                /*!< 0x00000020 */
#define EPWM_TZEINT_DCBEVT1                     EPWM_TZEINT_DCBEVT1_Msk                         
#define EPWM_TZEINT_DCBEVT2_Pos                 (6U)
#define EPWM_TZEINT_DCBEVT2_Msk                 (0x1UL<<EPWM_TZEINT_DCBEVT2_Pos)                /*!< 0x00000040 */
#define EPWM_TZEINT_DCBEVT2                     EPWM_TZEINT_DCBEVT2_Msk                         

/********************************* Bit definition for EPWM_TZFLG register *****************************************/
#define EPWM_TZFLG_INT_Pos                      (0U)
#define EPWM_TZFLG_INT_Msk                      (0x1UL<<EPWM_TZFLG_INT_Pos)                     /*!< 0x00000001 */
#define EPWM_TZFLG_INT                          EPWM_TZFLG_INT_Msk                              
#define EPWM_TZFLG_CBC_Pos                      (1U)
#define EPWM_TZFLG_CBC_Msk                      (0x1UL<<EPWM_TZFLG_CBC_Pos)                     /*!< 0x00000002 */
#define EPWM_TZFLG_CBC                          EPWM_TZFLG_CBC_Msk                              
#define EPWM_TZFLG_OST_Pos                      (2U)
#define EPWM_TZFLG_OST_Msk                      (0x1UL<<EPWM_TZFLG_OST_Pos)                     /*!< 0x00000004 */
#define EPWM_TZFLG_OST                          EPWM_TZFLG_OST_Msk                              
#define EPWM_TZFLG_DCAEVT1_Pos                  (3U)
#define EPWM_TZFLG_DCAEVT1_Msk                  (0x1UL<<EPWM_TZFLG_DCAEVT1_Pos)                 /*!< 0x00000008 */
#define EPWM_TZFLG_DCAEVT1                      EPWM_TZFLG_DCAEVT1_Msk                          
#define EPWM_TZFLG_DCAEVT2_Pos                  (4U)
#define EPWM_TZFLG_DCAEVT2_Msk                  (0x1UL<<EPWM_TZFLG_DCAEVT2_Pos)                 /*!< 0x00000010 */
#define EPWM_TZFLG_DCAEVT2                      EPWM_TZFLG_DCAEVT2_Msk                          
#define EPWM_TZFLG_DCBEVT1_Pos                  (5U)
#define EPWM_TZFLG_DCBEVT1_Msk                  (0x1UL<<EPWM_TZFLG_DCBEVT1_Pos)                 /*!< 0x00000020 */
#define EPWM_TZFLG_DCBEVT1                      EPWM_TZFLG_DCBEVT1_Msk                          
#define EPWM_TZFLG_DCBEVT2_Pos                  (6U)
#define EPWM_TZFLG_DCBEVT2_Msk                  (0x1UL<<EPWM_TZFLG_DCBEVT2_Pos)                 /*!< 0x00000040 */
#define EPWM_TZFLG_DCBEVT2                      EPWM_TZFLG_DCBEVT2_Msk                          

/********************************* Bit definition for EPWM_TZCBCFLG register **************************************/
#define EPWM_TZCBCFLG_CBC1_Pos                  (0U)
#define EPWM_TZCBCFLG_CBC1_Msk                  (0x1UL<<EPWM_TZCBCFLG_CBC1_Pos)                 /*!< 0x00000001 */
#define EPWM_TZCBCFLG_CBC1                      EPWM_TZCBCFLG_CBC1_Msk                          
#define EPWM_TZCBCFLG_CBC2_Pos                  (1U)
#define EPWM_TZCBCFLG_CBC2_Msk                  (0x1UL<<EPWM_TZCBCFLG_CBC2_Pos)                 /*!< 0x00000002 */
#define EPWM_TZCBCFLG_CBC2                      EPWM_TZCBCFLG_CBC2_Msk                          
#define EPWM_TZCBCFLG_CBC3_Pos                  (2U)
#define EPWM_TZCBCFLG_CBC3_Msk                  (0x1UL<<EPWM_TZCBCFLG_CBC3_Pos)                 /*!< 0x00000004 */
#define EPWM_TZCBCFLG_CBC3                      EPWM_TZCBCFLG_CBC3_Msk                          
#define EPWM_TZCBCFLG_CBC4_Pos                  (3U)
#define EPWM_TZCBCFLG_CBC4_Msk                  (0x1UL<<EPWM_TZCBCFLG_CBC4_Pos)                 /*!< 0x00000008 */
#define EPWM_TZCBCFLG_CBC4                      EPWM_TZCBCFLG_CBC4_Msk                          
#define EPWM_TZCBCFLG_CBC5_Pos                  (4U)
#define EPWM_TZCBCFLG_CBC5_Msk                  (0x1UL<<EPWM_TZCBCFLG_CBC5_Pos)                 /*!< 0x00000010 */
#define EPWM_TZCBCFLG_CBC5                      EPWM_TZCBCFLG_CBC5_Msk                          
#define EPWM_TZCBCFLG_CBC6_Pos                  (5U)
#define EPWM_TZCBCFLG_CBC6_Msk                  (0x1UL<<EPWM_TZCBCFLG_CBC6_Pos)                 /*!< 0x00000020 */
#define EPWM_TZCBCFLG_CBC6                      EPWM_TZCBCFLG_CBC6_Msk                          
#define EPWM_TZCBCFLG_DCAEVT2_Pos               (6U)
#define EPWM_TZCBCFLG_DCAEVT2_Msk               (0x1UL<<EPWM_TZCBCFLG_DCAEVT2_Pos)              /*!< 0x00000040 */
#define EPWM_TZCBCFLG_DCAEVT2                   EPWM_TZCBCFLG_DCAEVT2_Msk                       
#define EPWM_TZCBCFLG_DCBEVT2_Pos               (7U)
#define EPWM_TZCBCFLG_DCBEVT2_Msk               (0x1UL<<EPWM_TZCBCFLG_DCBEVT2_Pos)              /*!< 0x00000080 */
#define EPWM_TZCBCFLG_DCBEVT2                   EPWM_TZCBCFLG_DCBEVT2_Msk                       

/********************************* Bit definition for EPWM_TZOSTFLG register **************************************/
#define EPWM_TZOSTFLG_OST1_Pos                  (0U)
#define EPWM_TZOSTFLG_OST1_Msk                  (0x1UL<<EPWM_TZOSTFLG_OST1_Pos)                 /*!< 0x00000001 */
#define EPWM_TZOSTFLG_OST1                      EPWM_TZOSTFLG_OST1_Msk                          
#define EPWM_TZOSTFLG_OST2_Pos                  (1U)
#define EPWM_TZOSTFLG_OST2_Msk                  (0x1UL<<EPWM_TZOSTFLG_OST2_Pos)                 /*!< 0x00000002 */
#define EPWM_TZOSTFLG_OST2                      EPWM_TZOSTFLG_OST2_Msk                          
#define EPWM_TZOSTFLG_OST3_Pos                  (2U)
#define EPWM_TZOSTFLG_OST3_Msk                  (0x1UL<<EPWM_TZOSTFLG_OST3_Pos)                 /*!< 0x00000004 */
#define EPWM_TZOSTFLG_OST3                      EPWM_TZOSTFLG_OST3_Msk                          
#define EPWM_TZOSTFLG_OST4_Pos                  (3U)
#define EPWM_TZOSTFLG_OST4_Msk                  (0x1UL<<EPWM_TZOSTFLG_OST4_Pos)                 /*!< 0x00000008 */
#define EPWM_TZOSTFLG_OST4                      EPWM_TZOSTFLG_OST4_Msk                          
#define EPWM_TZOSTFLG_OST5_Pos                  (4U)
#define EPWM_TZOSTFLG_OST5_Msk                  (0x1UL<<EPWM_TZOSTFLG_OST5_Pos)                 /*!< 0x00000010 */
#define EPWM_TZOSTFLG_OST5                      EPWM_TZOSTFLG_OST5_Msk                          
#define EPWM_TZOSTFLG_OST6_Pos                  (5U)
#define EPWM_TZOSTFLG_OST6_Msk                  (0x1UL<<EPWM_TZOSTFLG_OST6_Pos)                 /*!< 0x00000020 */
#define EPWM_TZOSTFLG_OST6                      EPWM_TZOSTFLG_OST6_Msk                          
#define EPWM_TZOSTFLG_DCAEVT1_Pos               (6U)
#define EPWM_TZOSTFLG_DCAEVT1_Msk               (0x1UL<<EPWM_TZOSTFLG_DCAEVT1_Pos)              /*!< 0x00000040 */
#define EPWM_TZOSTFLG_DCAEVT1                   EPWM_TZOSTFLG_DCAEVT1_Msk                       
#define EPWM_TZOSTFLG_DCBEVT1_Pos               (7U)
#define EPWM_TZOSTFLG_DCBEVT1_Msk               (0x1UL<<EPWM_TZOSTFLG_DCBEVT1_Pos)              /*!< 0x00000080 */
#define EPWM_TZOSTFLG_DCBEVT1                   EPWM_TZOSTFLG_DCBEVT1_Msk                       

/********************************* Bit definition for EPWM_TZCLR register *****************************************/
#define EPWM_TZCLR_INT_Pos                      (0U)
#define EPWM_TZCLR_INT_Msk                      (0x1UL<<EPWM_TZCLR_INT_Pos)                     /*!< 0x00000001 */
#define EPWM_TZCLR_INT                          EPWM_TZCLR_INT_Msk                              
#define EPWM_TZCLR_CBC_Pos                      (1U)
#define EPWM_TZCLR_CBC_Msk                      (0x1UL<<EPWM_TZCLR_CBC_Pos)                     /*!< 0x00000002 */
#define EPWM_TZCLR_CBC                          EPWM_TZCLR_CBC_Msk                              
#define EPWM_TZCLR_OST_Pos                      (2U)
#define EPWM_TZCLR_OST_Msk                      (0x1UL<<EPWM_TZCLR_OST_Pos)                     /*!< 0x00000004 */
#define EPWM_TZCLR_OST                          EPWM_TZCLR_OST_Msk                              
#define EPWM_TZCLR_DCAEVT1_Pos                  (3U)
#define EPWM_TZCLR_DCAEVT1_Msk                  (0x1UL<<EPWM_TZCLR_DCAEVT1_Pos)                 /*!< 0x00000008 */
#define EPWM_TZCLR_DCAEVT1                      EPWM_TZCLR_DCAEVT1_Msk                          
#define EPWM_TZCLR_DCAEVT2_Pos                  (4U)
#define EPWM_TZCLR_DCAEVT2_Msk                  (0x1UL<<EPWM_TZCLR_DCAEVT2_Pos)                 /*!< 0x00000010 */
#define EPWM_TZCLR_DCAEVT2                      EPWM_TZCLR_DCAEVT2_Msk                          
#define EPWM_TZCLR_DCBEVT1_Pos                  (5U)
#define EPWM_TZCLR_DCBEVT1_Msk                  (0x1UL<<EPWM_TZCLR_DCBEVT1_Pos)                 /*!< 0x00000020 */
#define EPWM_TZCLR_DCBEVT1                      EPWM_TZCLR_DCBEVT1_Msk                          
#define EPWM_TZCLR_DCBEVT2_Pos                  (6U)
#define EPWM_TZCLR_DCBEVT2_Msk                  (0x1UL<<EPWM_TZCLR_DCBEVT2_Pos)                 /*!< 0x00000040 */
#define EPWM_TZCLR_DCBEVT2                      EPWM_TZCLR_DCBEVT2_Msk                          
#define EPWM_TZCLR_CBCPULSE_Pos                 (14U)
#define EPWM_TZCLR_CBCPULSE_Msk                 (0x3UL<<EPWM_TZCLR_CBCPULSE_Pos)                /*!< 0x0000C000 */
#define EPWM_TZCLR_CBCPULSE                     EPWM_TZCLR_CBCPULSE_Msk
#define EPWM_TZCLR_CBCPULSE_0                   (0x1UL<<EPWM_TZCLR_CBCPULSE_Pos)                /*!< 0x00004000 */
#define EPWM_TZCLR_CBCPULSE_1                   (0x2UL<<EPWM_TZCLR_CBCPULSE_Pos)                /*!< 0x00008000 */

/********************************* Bit definition for EPWM_TZCBCCLR register **************************************/
#define EPWM_TZCBCCLR_CBC1_Pos                  (0U)
#define EPWM_TZCBCCLR_CBC1_Msk                  (0x1UL<<EPWM_TZCBCCLR_CBC1_Pos)                 /*!< 0x00000001 */
#define EPWM_TZCBCCLR_CBC1                      EPWM_TZCBCCLR_CBC1_Msk                          
#define EPWM_TZCBCCLR_CBC2_Pos                  (1U)
#define EPWM_TZCBCCLR_CBC2_Msk                  (0x1UL<<EPWM_TZCBCCLR_CBC2_Pos)                 /*!< 0x00000002 */
#define EPWM_TZCBCCLR_CBC2                      EPWM_TZCBCCLR_CBC2_Msk                          
#define EPWM_TZCBCCLR_CBC3_Pos                  (2U)
#define EPWM_TZCBCCLR_CBC3_Msk                  (0x1UL<<EPWM_TZCBCCLR_CBC3_Pos)                 /*!< 0x00000004 */
#define EPWM_TZCBCCLR_CBC3                      EPWM_TZCBCCLR_CBC3_Msk                          
#define EPWM_TZCBCCLR_CBC4_Pos                  (3U)
#define EPWM_TZCBCCLR_CBC4_Msk                  (0x1UL<<EPWM_TZCBCCLR_CBC4_Pos)                 /*!< 0x00000008 */
#define EPWM_TZCBCCLR_CBC4                      EPWM_TZCBCCLR_CBC4_Msk                          
#define EPWM_TZCBCCLR_CBC5_Pos                  (4U)
#define EPWM_TZCBCCLR_CBC5_Msk                  (0x1UL<<EPWM_TZCBCCLR_CBC5_Pos)                 /*!< 0x00000010 */
#define EPWM_TZCBCCLR_CBC5                      EPWM_TZCBCCLR_CBC5_Msk                          
#define EPWM_TZCBCCLR_CBC6_Pos                  (5U)
#define EPWM_TZCBCCLR_CBC6_Msk                  (0x1UL<<EPWM_TZCBCCLR_CBC6_Pos)                 /*!< 0x00000020 */
#define EPWM_TZCBCCLR_CBC6                      EPWM_TZCBCCLR_CBC6_Msk                          
#define EPWM_TZCBCCLR_DCAEVT2_Pos               (6U)
#define EPWM_TZCBCCLR_DCAEVT2_Msk               (0x1UL<<EPWM_TZCBCCLR_DCAEVT2_Pos)              /*!< 0x00000040 */
#define EPWM_TZCBCCLR_DCAEVT2                   EPWM_TZCBCCLR_DCAEVT2_Msk                       
#define EPWM_TZCBCCLR_DCBEVT2_Pos               (7U)
#define EPWM_TZCBCCLR_DCBEVT2_Msk               (0x1UL<<EPWM_TZCBCCLR_DCBEVT2_Pos)              /*!< 0x00000080 */
#define EPWM_TZCBCCLR_DCBEVT2                   EPWM_TZCBCCLR_DCBEVT2_Msk                       

/********************************* Bit definition for EPWM_TZOSTCLR register **************************************/
#define EPWM_TZOSTCLR_OST1_Pos                  (0U)
#define EPWM_TZOSTCLR_OST1_Msk                  (0x1UL<<EPWM_TZOSTCLR_OST1_Pos)                 /*!< 0x00000001 */
#define EPWM_TZOSTCLR_OST1                      EPWM_TZOSTCLR_OST1_Msk                          
#define EPWM_TZOSTCLR_OST2_Pos                  (1U)
#define EPWM_TZOSTCLR_OST2_Msk                  (0x1UL<<EPWM_TZOSTCLR_OST2_Pos)                 /*!< 0x00000002 */
#define EPWM_TZOSTCLR_OST2                      EPWM_TZOSTCLR_OST2_Msk                          
#define EPWM_TZOSTCLR_OST3_Pos                  (2U)
#define EPWM_TZOSTCLR_OST3_Msk                  (0x1UL<<EPWM_TZOSTCLR_OST3_Pos)                 /*!< 0x00000004 */
#define EPWM_TZOSTCLR_OST3                      EPWM_TZOSTCLR_OST3_Msk                          
#define EPWM_TZOSTCLR_OST4_Pos                  (3U)
#define EPWM_TZOSTCLR_OST4_Msk                  (0x1UL<<EPWM_TZOSTCLR_OST4_Pos)                 /*!< 0x00000008 */
#define EPWM_TZOSTCLR_OST4                      EPWM_TZOSTCLR_OST4_Msk                          
#define EPWM_TZOSTCLR_OST5_Pos                  (4U)
#define EPWM_TZOSTCLR_OST5_Msk                  (0x1UL<<EPWM_TZOSTCLR_OST5_Pos)                 /*!< 0x00000010 */
#define EPWM_TZOSTCLR_OST5                      EPWM_TZOSTCLR_OST5_Msk                          
#define EPWM_TZOSTCLR_OST6_Pos                  (5U)
#define EPWM_TZOSTCLR_OST6_Msk                  (0x1UL<<EPWM_TZOSTCLR_OST6_Pos)                 /*!< 0x00000020 */
#define EPWM_TZOSTCLR_OST6                      EPWM_TZOSTCLR_OST6_Msk                          
#define EPWM_TZOSTCLR_DCAEVT1_Pos               (6U)
#define EPWM_TZOSTCLR_DCAEVT1_Msk               (0x1UL<<EPWM_TZOSTCLR_DCAEVT1_Pos)              /*!< 0x00000040 */
#define EPWM_TZOSTCLR_DCAEVT1                   EPWM_TZOSTCLR_DCAEVT1_Msk                       
#define EPWM_TZOSTCLR_DCBEVT1_Pos               (7U)
#define EPWM_TZOSTCLR_DCBEVT1_Msk               (0x1UL<<EPWM_TZOSTCLR_DCBEVT1_Pos)              /*!< 0x00000080 */
#define EPWM_TZOSTCLR_DCBEVT1                   EPWM_TZOSTCLR_DCBEVT1_Msk                       

/********************************* Bit definition for EPWM_TZFRC register *****************************************/
#define EPWM_TZFRC_CBC_Pos                      (1U)
#define EPWM_TZFRC_CBC_Msk                      (0x1UL<<EPWM_TZFRC_CBC_Pos)                     /*!< 0x00000002 */
#define EPWM_TZFRC_CBC                          EPWM_TZFRC_CBC_Msk                              
#define EPWM_TZFRC_OST_Pos                      (2U)
#define EPWM_TZFRC_OST_Msk                      (0x1UL<<EPWM_TZFRC_OST_Pos)                     /*!< 0x00000004 */
#define EPWM_TZFRC_OST                          EPWM_TZFRC_OST_Msk                              
#define EPWM_TZFRC_DCAEVT1_Pos                  (3U)
#define EPWM_TZFRC_DCAEVT1_Msk                  (0x1UL<<EPWM_TZFRC_DCAEVT1_Pos)                 /*!< 0x00000008 */
#define EPWM_TZFRC_DCAEVT1                      EPWM_TZFRC_DCAEVT1_Msk                          
#define EPWM_TZFRC_DCAEVT2_Pos                  (4U)
#define EPWM_TZFRC_DCAEVT2_Msk                  (0x1UL<<EPWM_TZFRC_DCAEVT2_Pos)                 /*!< 0x00000010 */
#define EPWM_TZFRC_DCAEVT2                      EPWM_TZFRC_DCAEVT2_Msk                          
#define EPWM_TZFRC_DCBEVT1_Pos                  (5U)
#define EPWM_TZFRC_DCBEVT1_Msk                  (0x1UL<<EPWM_TZFRC_DCBEVT1_Pos)                 /*!< 0x00000020 */
#define EPWM_TZFRC_DCBEVT1                      EPWM_TZFRC_DCBEVT1_Msk                          
#define EPWM_TZFRC_DCBEVT2_Pos                  (6U)
#define EPWM_TZFRC_DCBEVT2_Msk                  (0x1UL<<EPWM_TZFRC_DCBEVT2_Pos)                 /*!< 0x00000040 */
#define EPWM_TZFRC_DCBEVT2                      EPWM_TZFRC_DCBEVT2_Msk                          

/********************************* Bit definition for EPWM_ETSEL register *****************************************/
#define EPWM_ETSEL_INTSEL_Pos                   (0U)
#define EPWM_ETSEL_INTSEL_Msk                   (0x7UL<<EPWM_ETSEL_INTSEL_Pos)                  /*!< 0x00000007 */
#define EPWM_ETSEL_INTSEL                       EPWM_ETSEL_INTSEL_Msk
#define EPWM_ETSEL_INTSEL_0                     (0x1UL<<EPWM_ETSEL_INTSEL_Pos)                  /*!< 0x00000001 */
#define EPWM_ETSEL_INTSEL_1                     (0x2UL<<EPWM_ETSEL_INTSEL_Pos)                  /*!< 0x00000002 */
#define EPWM_ETSEL_INTSEL_2                     (0x4UL<<EPWM_ETSEL_INTSEL_Pos)                  /*!< 0x00000004 */
#define EPWM_ETSEL_INTEN_Pos                    (3U)
#define EPWM_ETSEL_INTEN_Msk                    (0x1UL<<EPWM_ETSEL_INTEN_Pos)                   /*!< 0x00000008 */
#define EPWM_ETSEL_INTEN                        EPWM_ETSEL_INTEN_Msk                            
#define EPWM_ETSEL_SOCASELCMP_Pos               (4U)
#define EPWM_ETSEL_SOCASELCMP_Msk               (0x1UL<<EPWM_ETSEL_SOCASELCMP_Pos)              /*!< 0x00000010 */
#define EPWM_ETSEL_SOCASELCMP                   EPWM_ETSEL_SOCASELCMP_Msk                       
#define EPWM_ETSEL_SOCBSELCMP_Pos               (5U)
#define EPWM_ETSEL_SOCBSELCMP_Msk               (0x1UL<<EPWM_ETSEL_SOCBSELCMP_Pos)              /*!< 0x00000020 */
#define EPWM_ETSEL_SOCBSELCMP                   EPWM_ETSEL_SOCBSELCMP_Msk                       
#define EPWM_ETSEL_INTSELCMP_Pos                (6U)
#define EPWM_ETSEL_INTSELCMP_Msk                (0x1UL<<EPWM_ETSEL_INTSELCMP_Pos)               /*!< 0x00000040 */
#define EPWM_ETSEL_INTSELCMP                    EPWM_ETSEL_INTSELCMP_Msk                        
#define EPWM_ETSEL_SOCASEL_Pos                  (8U)
#define EPWM_ETSEL_SOCASEL_Msk                  (0x7UL<<EPWM_ETSEL_SOCASEL_Pos)                 /*!< 0x00000700 */
#define EPWM_ETSEL_SOCASEL                      EPWM_ETSEL_SOCASEL_Msk
#define EPWM_ETSEL_SOCASEL_0                    (0x1UL<<EPWM_ETSEL_SOCASEL_Pos)                 /*!< 0x00000100 */
#define EPWM_ETSEL_SOCASEL_1                    (0x2UL<<EPWM_ETSEL_SOCASEL_Pos)                 /*!< 0x00000200 */
#define EPWM_ETSEL_SOCASEL_2                    (0x4UL<<EPWM_ETSEL_SOCASEL_Pos)                 /*!< 0x00000400 */
#define EPWM_ETSEL_SOCAEN_Pos                   (11U)
#define EPWM_ETSEL_SOCAEN_Msk                   (0x1UL<<EPWM_ETSEL_SOCAEN_Pos)                  /*!< 0x00000800 */
#define EPWM_ETSEL_SOCAEN                       EPWM_ETSEL_SOCAEN_Msk                           
#define EPWM_ETSEL_SOCBSEL_Pos                  (12U)
#define EPWM_ETSEL_SOCBSEL_Msk                  (0x7UL<<EPWM_ETSEL_SOCBSEL_Pos)                 /*!< 0x00007000 */
#define EPWM_ETSEL_SOCBSEL                      EPWM_ETSEL_SOCBSEL_Msk
#define EPWM_ETSEL_SOCBSEL_0                    (0x1UL<<EPWM_ETSEL_SOCBSEL_Pos)                 /*!< 0x00001000 */
#define EPWM_ETSEL_SOCBSEL_1                    (0x2UL<<EPWM_ETSEL_SOCBSEL_Pos)                 /*!< 0x00002000 */
#define EPWM_ETSEL_SOCBSEL_2                    (0x4UL<<EPWM_ETSEL_SOCBSEL_Pos)                 /*!< 0x00004000 */
#define EPWM_ETSEL_SOCBEN_Pos                   (15U)
#define EPWM_ETSEL_SOCBEN_Msk                   (0x1UL<<EPWM_ETSEL_SOCBEN_Pos)                  /*!< 0x00008000 */
#define EPWM_ETSEL_SOCBEN                       EPWM_ETSEL_SOCBEN_Msk                           

/********************************* Bit definition for EPWM_ETPS register ******************************************/
#define EPWM_ETPS_INTPRD_Pos                    (0U)
#define EPWM_ETPS_INTPRD_Msk                    (0x3UL<<EPWM_ETPS_INTPRD_Pos)                   /*!< 0x00000003 */
#define EPWM_ETPS_INTPRD                        EPWM_ETPS_INTPRD_Msk
#define EPWM_ETPS_INTPRD_0                      (0x1UL<<EPWM_ETPS_INTPRD_Pos)                   /*!< 0x00000001 */
#define EPWM_ETPS_INTPRD_1                      (0x2UL<<EPWM_ETPS_INTPRD_Pos)                   /*!< 0x00000002 */
#define EPWM_ETPS_INTCNT_Pos                    (2U)
#define EPWM_ETPS_INTCNT_Msk                    (0x3UL<<EPWM_ETPS_INTCNT_Pos)                   /*!< 0x0000000C */
#define EPWM_ETPS_INTCNT                        EPWM_ETPS_INTCNT_Msk
#define EPWM_ETPS_INTCNT_0                      (0x1UL<<EPWM_ETPS_INTCNT_Pos)                   /*!< 0x00000004 */
#define EPWM_ETPS_INTCNT_1                      (0x2UL<<EPWM_ETPS_INTCNT_Pos)                   /*!< 0x00000008 */
#define EPWM_ETPS_INTPSSEL_Pos                  (4U)
#define EPWM_ETPS_INTPSSEL_Msk                  (0x1UL<<EPWM_ETPS_INTPSSEL_Pos)                 /*!< 0x00000010 */
#define EPWM_ETPS_INTPSSEL                      EPWM_ETPS_INTPSSEL_Msk                          
#define EPWM_ETPS_SOCPSSEL_Pos                  (5U)
#define EPWM_ETPS_SOCPSSEL_Msk                  (0x1UL<<EPWM_ETPS_SOCPSSEL_Pos)                 /*!< 0x00000020 */
#define EPWM_ETPS_SOCPSSEL                      EPWM_ETPS_SOCPSSEL_Msk                          
#define EPWM_ETPS_SOCAPRD_Pos                   (8U)
#define EPWM_ETPS_SOCAPRD_Msk                   (0x3UL<<EPWM_ETPS_SOCAPRD_Pos)                  /*!< 0x00000300 */
#define EPWM_ETPS_SOCAPRD                       EPWM_ETPS_SOCAPRD_Msk
#define EPWM_ETPS_SOCAPRD_0                     (0x1UL<<EPWM_ETPS_SOCAPRD_Pos)                  /*!< 0x00000100 */
#define EPWM_ETPS_SOCAPRD_1                     (0x2UL<<EPWM_ETPS_SOCAPRD_Pos)                  /*!< 0x00000200 */
#define EPWM_ETPS_SOCACNT_Pos                   (10U)
#define EPWM_ETPS_SOCACNT_Msk                   (0x3UL<<EPWM_ETPS_SOCACNT_Pos)                  /*!< 0x00000C00 */
#define EPWM_ETPS_SOCACNT                       EPWM_ETPS_SOCACNT_Msk
#define EPWM_ETPS_SOCACNT_0                     (0x1UL<<EPWM_ETPS_SOCACNT_Pos)                  /*!< 0x00000400 */
#define EPWM_ETPS_SOCACNT_1                     (0x2UL<<EPWM_ETPS_SOCACNT_Pos)                  /*!< 0x00000800 */
#define EPWM_ETPS_SOCBPRD_Pos                   (12U)
#define EPWM_ETPS_SOCBPRD_Msk                   (0x3UL<<EPWM_ETPS_SOCBPRD_Pos)                  /*!< 0x00003000 */
#define EPWM_ETPS_SOCBPRD                       EPWM_ETPS_SOCBPRD_Msk
#define EPWM_ETPS_SOCBPRD_0                     (0x1UL<<EPWM_ETPS_SOCBPRD_Pos)                  /*!< 0x00001000 */
#define EPWM_ETPS_SOCBPRD_1                     (0x2UL<<EPWM_ETPS_SOCBPRD_Pos)                  /*!< 0x00002000 */
#define EPWM_ETPS_SOCBCNT_Pos                   (14U)
#define EPWM_ETPS_SOCBCNT_Msk                   (0x3UL<<EPWM_ETPS_SOCBCNT_Pos)                  /*!< 0x0000C000 */
#define EPWM_ETPS_SOCBCNT                       EPWM_ETPS_SOCBCNT_Msk
#define EPWM_ETPS_SOCBCNT_0                     (0x1UL<<EPWM_ETPS_SOCBCNT_Pos)                  /*!< 0x00004000 */
#define EPWM_ETPS_SOCBCNT_1                     (0x2UL<<EPWM_ETPS_SOCBCNT_Pos)                  /*!< 0x00008000 */

/********************************* Bit definition for EPWM_ETFLG register *****************************************/
#define EPWM_ETFLG_INT_Pos                      (0U)
#define EPWM_ETFLG_INT_Msk                      (0x1UL<<EPWM_ETFLG_INT_Pos)                     /*!< 0x00000001 */
#define EPWM_ETFLG_INT                          EPWM_ETFLG_INT_Msk                              
#define EPWM_ETFLG_SOCA_Pos                     (2U)
#define EPWM_ETFLG_SOCA_Msk                     (0x1UL<<EPWM_ETFLG_SOCA_Pos)                    /*!< 0x00000004 */
#define EPWM_ETFLG_SOCA                         EPWM_ETFLG_SOCA_Msk                             
#define EPWM_ETFLG_SOCB_Pos                     (3U)
#define EPWM_ETFLG_SOCB_Msk                     (0x1UL<<EPWM_ETFLG_SOCB_Pos)                    /*!< 0x00000008 */
#define EPWM_ETFLG_SOCB                         EPWM_ETFLG_SOCB_Msk                             

/********************************* Bit definition for EPWM_ETCLR register *****************************************/
#define EPWM_ETCLR_INT_Pos                      (0U)
#define EPWM_ETCLR_INT_Msk                      (0x1UL<<EPWM_ETCLR_INT_Pos)                     /*!< 0x00000001 */
#define EPWM_ETCLR_INT                          EPWM_ETCLR_INT_Msk                              
#define EPWM_ETCLR_SOCA_Pos                     (2U)
#define EPWM_ETCLR_SOCA_Msk                     (0x1UL<<EPWM_ETCLR_SOCA_Pos)                    /*!< 0x00000004 */
#define EPWM_ETCLR_SOCA                         EPWM_ETCLR_SOCA_Msk                             
#define EPWM_ETCLR_SOCB_Pos                     (3U)
#define EPWM_ETCLR_SOCB_Msk                     (0x1UL<<EPWM_ETCLR_SOCB_Pos)                    /*!< 0x00000008 */
#define EPWM_ETCLR_SOCB                         EPWM_ETCLR_SOCB_Msk                             

/********************************* Bit definition for EPWM_ETFRC register *****************************************/
#define EPWM_ETFRC_INT_Pos                      (0U)
#define EPWM_ETFRC_INT_Msk                      (0x1UL<<EPWM_ETFRC_INT_Pos)                     /*!< 0x00000001 */
#define EPWM_ETFRC_INT                          EPWM_ETFRC_INT_Msk                              
#define EPWM_ETFRC_SOCA_Pos                     (2U)
#define EPWM_ETFRC_SOCA_Msk                     (0x1UL<<EPWM_ETFRC_SOCA_Pos)                    /*!< 0x00000004 */
#define EPWM_ETFRC_SOCA                         EPWM_ETFRC_SOCA_Msk                             
#define EPWM_ETFRC_SOCB_Pos                     (3U)
#define EPWM_ETFRC_SOCB_Msk                     (0x1UL<<EPWM_ETFRC_SOCB_Pos)                    /*!< 0x00000008 */
#define EPWM_ETFRC_SOCB                         EPWM_ETFRC_SOCB_Msk                             

/********************************* Bit definition for EPWM_ETINTPS register ***************************************/
#define EPWM_ETINTPS_INTPRD2_Pos                (0U)
#define EPWM_ETINTPS_INTPRD2_Msk                (0xFUL<<EPWM_ETINTPS_INTPRD2_Pos)               /*!< 0x0000000F */
#define EPWM_ETINTPS_INTPRD2                    EPWM_ETINTPS_INTPRD2_Msk
#define EPWM_ETINTPS_INTPRD2_0                  (0x1UL<<EPWM_ETINTPS_INTPRD2_Pos)               /*!< 0x00000001 */
#define EPWM_ETINTPS_INTPRD2_1                  (0x2UL<<EPWM_ETINTPS_INTPRD2_Pos)               /*!< 0x00000002 */
#define EPWM_ETINTPS_INTPRD2_2                  (0x4UL<<EPWM_ETINTPS_INTPRD2_Pos)               /*!< 0x00000004 */
#define EPWM_ETINTPS_INTPRD2_3                  (0x8UL<<EPWM_ETINTPS_INTPRD2_Pos)               /*!< 0x00000008 */
#define EPWM_ETINTPS_INTCNT2_Pos                (4U)
#define EPWM_ETINTPS_INTCNT2_Msk                (0xFUL<<EPWM_ETINTPS_INTCNT2_Pos)               /*!< 0x000000F0 */
#define EPWM_ETINTPS_INTCNT2                    EPWM_ETINTPS_INTCNT2_Msk
#define EPWM_ETINTPS_INTCNT2_0                  (0x1UL<<EPWM_ETINTPS_INTCNT2_Pos)               /*!< 0x00000010 */
#define EPWM_ETINTPS_INTCNT2_1                  (0x2UL<<EPWM_ETINTPS_INTCNT2_Pos)               /*!< 0x00000020 */
#define EPWM_ETINTPS_INTCNT2_2                  (0x4UL<<EPWM_ETINTPS_INTCNT2_Pos)               /*!< 0x00000040 */
#define EPWM_ETINTPS_INTCNT2_3                  (0x8UL<<EPWM_ETINTPS_INTCNT2_Pos)               /*!< 0x00000080 */

/********************************* Bit definition for EPWM_ETSOCPS register ***************************************/
#define EPWM_ETSOCPS_SOCAPRD2_Pos               (0U)
#define EPWM_ETSOCPS_SOCAPRD2_Msk               (0xFUL<<EPWM_ETSOCPS_SOCAPRD2_Pos)              /*!< 0x0000000F */
#define EPWM_ETSOCPS_SOCAPRD2                   EPWM_ETSOCPS_SOCAPRD2_Msk
#define EPWM_ETSOCPS_SOCAPRD2_0                 (0x1UL<<EPWM_ETSOCPS_SOCAPRD2_Pos)              /*!< 0x00000001 */
#define EPWM_ETSOCPS_SOCAPRD2_1                 (0x2UL<<EPWM_ETSOCPS_SOCAPRD2_Pos)              /*!< 0x00000002 */
#define EPWM_ETSOCPS_SOCAPRD2_2                 (0x4UL<<EPWM_ETSOCPS_SOCAPRD2_Pos)              /*!< 0x00000004 */
#define EPWM_ETSOCPS_SOCAPRD2_3                 (0x8UL<<EPWM_ETSOCPS_SOCAPRD2_Pos)              /*!< 0x00000008 */
#define EPWM_ETSOCPS_SOCACNT2_Pos               (4U)
#define EPWM_ETSOCPS_SOCACNT2_Msk               (0xFUL<<EPWM_ETSOCPS_SOCACNT2_Pos)              /*!< 0x000000F0 */
#define EPWM_ETSOCPS_SOCACNT2                   EPWM_ETSOCPS_SOCACNT2_Msk
#define EPWM_ETSOCPS_SOCACNT2_0                 (0x1UL<<EPWM_ETSOCPS_SOCACNT2_Pos)              /*!< 0x00000010 */
#define EPWM_ETSOCPS_SOCACNT2_1                 (0x2UL<<EPWM_ETSOCPS_SOCACNT2_Pos)              /*!< 0x00000020 */
#define EPWM_ETSOCPS_SOCACNT2_2                 (0x4UL<<EPWM_ETSOCPS_SOCACNT2_Pos)              /*!< 0x00000040 */
#define EPWM_ETSOCPS_SOCACNT2_3                 (0x8UL<<EPWM_ETSOCPS_SOCACNT2_Pos)              /*!< 0x00000080 */
#define EPWM_ETSOCPS_SOCBPRD2_Pos               (8U)
#define EPWM_ETSOCPS_SOCBPRD2_Msk               (0xFUL<<EPWM_ETSOCPS_SOCBPRD2_Pos)              /*!< 0x00000F00 */
#define EPWM_ETSOCPS_SOCBPRD2                   EPWM_ETSOCPS_SOCBPRD2_Msk
#define EPWM_ETSOCPS_SOCBPRD2_0                 (0x1UL<<EPWM_ETSOCPS_SOCBPRD2_Pos)              /*!< 0x00000100 */
#define EPWM_ETSOCPS_SOCBPRD2_1                 (0x2UL<<EPWM_ETSOCPS_SOCBPRD2_Pos)              /*!< 0x00000200 */
#define EPWM_ETSOCPS_SOCBPRD2_2                 (0x4UL<<EPWM_ETSOCPS_SOCBPRD2_Pos)              /*!< 0x00000400 */
#define EPWM_ETSOCPS_SOCBPRD2_3                 (0x8UL<<EPWM_ETSOCPS_SOCBPRD2_Pos)              /*!< 0x00000800 */
#define EPWM_ETSOCPS_SOCBCNT2_Pos               (12U)
#define EPWM_ETSOCPS_SOCBCNT2_Msk               (0xFUL<<EPWM_ETSOCPS_SOCBCNT2_Pos)              /*!< 0x0000F000 */
#define EPWM_ETSOCPS_SOCBCNT2                   EPWM_ETSOCPS_SOCBCNT2_Msk
#define EPWM_ETSOCPS_SOCBCNT2_0                 (0x1UL<<EPWM_ETSOCPS_SOCBCNT2_Pos)              /*!< 0x00001000 */
#define EPWM_ETSOCPS_SOCBCNT2_1                 (0x2UL<<EPWM_ETSOCPS_SOCBCNT2_Pos)              /*!< 0x00002000 */
#define EPWM_ETSOCPS_SOCBCNT2_2                 (0x4UL<<EPWM_ETSOCPS_SOCBCNT2_Pos)              /*!< 0x00004000 */
#define EPWM_ETSOCPS_SOCBCNT2_3                 (0x8UL<<EPWM_ETSOCPS_SOCBCNT2_Pos)              /*!< 0x00008000 */

/********************************* Bit definition for EPWM_ETCNTINITCTL register **********************************/
#define EPWM_ETCNTINITCTL_INTINITFRC_Pos        (10U)
#define EPWM_ETCNTINITCTL_INTINITFRC_Msk        (0x1UL<<EPWM_ETCNTINITCTL_INTINITFRC_Pos)       /*!< 0x00000400 */
#define EPWM_ETCNTINITCTL_INTINITFRC            EPWM_ETCNTINITCTL_INTINITFRC_Msk                
#define EPWM_ETCNTINITCTL_SOCAINITFRC_Pos       (11U)
#define EPWM_ETCNTINITCTL_SOCAINITFRC_Msk       (0x1UL<<EPWM_ETCNTINITCTL_SOCAINITFRC_Pos)      /*!< 0x00000800 */
#define EPWM_ETCNTINITCTL_SOCAINITFRC           EPWM_ETCNTINITCTL_SOCAINITFRC_Msk               
#define EPWM_ETCNTINITCTL_SOCBINITFRC_Pos       (12U)
#define EPWM_ETCNTINITCTL_SOCBINITFRC_Msk       (0x1UL<<EPWM_ETCNTINITCTL_SOCBINITFRC_Pos)      /*!< 0x00001000 */
#define EPWM_ETCNTINITCTL_SOCBINITFRC           EPWM_ETCNTINITCTL_SOCBINITFRC_Msk               
#define EPWM_ETCNTINITCTL_INTINTEN_Pos          (13U)
#define EPWM_ETCNTINITCTL_INTINTEN_Msk          (0x1UL<<EPWM_ETCNTINITCTL_INTINTEN_Pos)         /*!< 0x00002000 */
#define EPWM_ETCNTINITCTL_INTINTEN              EPWM_ETCNTINITCTL_INTINTEN_Msk                  
#define EPWM_ETCNTINITCTL_SOCAINTEN_Pos         (14U)
#define EPWM_ETCNTINITCTL_SOCAINTEN_Msk         (0x1UL<<EPWM_ETCNTINITCTL_SOCAINTEN_Pos)        /*!< 0x00004000 */
#define EPWM_ETCNTINITCTL_SOCAINTEN             EPWM_ETCNTINITCTL_SOCAINTEN_Msk                 
#define EPWM_ETCNTINITCTL_SOCBINTEN_Pos         (15U)
#define EPWM_ETCNTINITCTL_SOCBINTEN_Msk         (0x1UL<<EPWM_ETCNTINITCTL_SOCBINTEN_Pos)        /*!< 0x00008000 */
#define EPWM_ETCNTINITCTL_SOCBINTEN             EPWM_ETCNTINITCTL_SOCBINTEN_Msk                 

/********************************* Bit definition for EPWM_ETCNTINIT register *************************************/
#define EPWM_ETCNTINIT_INTINT_Pos               (0U)
#define EPWM_ETCNTINIT_INTINT_Msk               (0xFUL<<EPWM_ETCNTINIT_INTINT_Pos)              /*!< 0x0000000F */
#define EPWM_ETCNTINIT_INTINT                   EPWM_ETCNTINIT_INTINT_Msk
#define EPWM_ETCNTINIT_INTINT_0                 (0x1UL<<EPWM_ETCNTINIT_INTINT_Pos)              /*!< 0x00000001 */
#define EPWM_ETCNTINIT_INTINT_1                 (0x2UL<<EPWM_ETCNTINIT_INTINT_Pos)              /*!< 0x00000002 */
#define EPWM_ETCNTINIT_INTINT_2                 (0x4UL<<EPWM_ETCNTINIT_INTINT_Pos)              /*!< 0x00000004 */
#define EPWM_ETCNTINIT_INTINT_3                 (0x8UL<<EPWM_ETCNTINIT_INTINT_Pos)              /*!< 0x00000008 */
#define EPWM_ETCNTINIT_SOCAINT_Pos              (4U)
#define EPWM_ETCNTINIT_SOCAINT_Msk              (0xFUL<<EPWM_ETCNTINIT_SOCAINT_Pos)             /*!< 0x000000F0 */
#define EPWM_ETCNTINIT_SOCAINT                  EPWM_ETCNTINIT_SOCAINT_Msk
#define EPWM_ETCNTINIT_SOCAINT_0                (0x1UL<<EPWM_ETCNTINIT_SOCAINT_Pos)             /*!< 0x00000010 */
#define EPWM_ETCNTINIT_SOCAINT_1                (0x2UL<<EPWM_ETCNTINIT_SOCAINT_Pos)             /*!< 0x00000020 */
#define EPWM_ETCNTINIT_SOCAINT_2                (0x4UL<<EPWM_ETCNTINIT_SOCAINT_Pos)             /*!< 0x00000040 */
#define EPWM_ETCNTINIT_SOCAINT_3                (0x8UL<<EPWM_ETCNTINIT_SOCAINT_Pos)             /*!< 0x00000080 */
#define EPWM_ETCNTINIT_SOCBINT_Pos              (8U)
#define EPWM_ETCNTINIT_SOCBINT_Msk              (0xFUL<<EPWM_ETCNTINIT_SOCBINT_Pos)             /*!< 0x00000F00 */
#define EPWM_ETCNTINIT_SOCBINT                  EPWM_ETCNTINIT_SOCBINT_Msk
#define EPWM_ETCNTINIT_SOCBINT_0                (0x1UL<<EPWM_ETCNTINIT_SOCBINT_Pos)             /*!< 0x00000100 */
#define EPWM_ETCNTINIT_SOCBINT_1                (0x2UL<<EPWM_ETCNTINIT_SOCBINT_Pos)             /*!< 0x00000200 */
#define EPWM_ETCNTINIT_SOCBINT_2                (0x4UL<<EPWM_ETCNTINIT_SOCBINT_Pos)             /*!< 0x00000400 */
#define EPWM_ETCNTINIT_SOCBINT_3                (0x8UL<<EPWM_ETCNTINIT_SOCBINT_Pos)             /*!< 0x00000800 */

/********************************* Bit definition for EPWM_DCTRIPSEL register *************************************/
#define EPWM_DCTRIPSEL_DCAHCOMPSEL_Pos          (0U)
#define EPWM_DCTRIPSEL_DCAHCOMPSEL_Msk          (0xFUL<<EPWM_DCTRIPSEL_DCAHCOMPSEL_Pos)         /*!< 0x0000000F */
#define EPWM_DCTRIPSEL_DCAHCOMPSEL              EPWM_DCTRIPSEL_DCAHCOMPSEL_Msk
#define EPWM_DCTRIPSEL_DCAHCOMPSEL_0            (0x1UL<<EPWM_DCTRIPSEL_DCAHCOMPSEL_Pos)         /*!< 0x00000001 */
#define EPWM_DCTRIPSEL_DCAHCOMPSEL_1            (0x2UL<<EPWM_DCTRIPSEL_DCAHCOMPSEL_Pos)         /*!< 0x00000002 */
#define EPWM_DCTRIPSEL_DCAHCOMPSEL_2            (0x4UL<<EPWM_DCTRIPSEL_DCAHCOMPSEL_Pos)         /*!< 0x00000004 */
#define EPWM_DCTRIPSEL_DCAHCOMPSEL_3            (0x8UL<<EPWM_DCTRIPSEL_DCAHCOMPSEL_Pos)         /*!< 0x00000008 */
#define EPWM_DCTRIPSEL_DCALCOMPSEL_Pos          (4U)
#define EPWM_DCTRIPSEL_DCALCOMPSEL_Msk          (0xFUL<<EPWM_DCTRIPSEL_DCALCOMPSEL_Pos)         /*!< 0x000000F0 */
#define EPWM_DCTRIPSEL_DCALCOMPSEL              EPWM_DCTRIPSEL_DCALCOMPSEL_Msk
#define EPWM_DCTRIPSEL_DCALCOMPSEL_0            (0x1UL<<EPWM_DCTRIPSEL_DCALCOMPSEL_Pos)         /*!< 0x00000010 */
#define EPWM_DCTRIPSEL_DCALCOMPSEL_1            (0x2UL<<EPWM_DCTRIPSEL_DCALCOMPSEL_Pos)         /*!< 0x00000020 */
#define EPWM_DCTRIPSEL_DCALCOMPSEL_2            (0x4UL<<EPWM_DCTRIPSEL_DCALCOMPSEL_Pos)         /*!< 0x00000040 */
#define EPWM_DCTRIPSEL_DCALCOMPSEL_3            (0x8UL<<EPWM_DCTRIPSEL_DCALCOMPSEL_Pos)         /*!< 0x00000080 */
#define EPWM_DCTRIPSEL_DCBHCOMPSEL_Pos          (8U)
#define EPWM_DCTRIPSEL_DCBHCOMPSEL_Msk          (0xFUL<<EPWM_DCTRIPSEL_DCBHCOMPSEL_Pos)         /*!< 0x00000F00 */
#define EPWM_DCTRIPSEL_DCBHCOMPSEL              EPWM_DCTRIPSEL_DCBHCOMPSEL_Msk
#define EPWM_DCTRIPSEL_DCBHCOMPSEL_0            (0x1UL<<EPWM_DCTRIPSEL_DCBHCOMPSEL_Pos)         /*!< 0x00000100 */
#define EPWM_DCTRIPSEL_DCBHCOMPSEL_1            (0x2UL<<EPWM_DCTRIPSEL_DCBHCOMPSEL_Pos)         /*!< 0x00000200 */
#define EPWM_DCTRIPSEL_DCBHCOMPSEL_2            (0x4UL<<EPWM_DCTRIPSEL_DCBHCOMPSEL_Pos)         /*!< 0x00000400 */
#define EPWM_DCTRIPSEL_DCBHCOMPSEL_3            (0x8UL<<EPWM_DCTRIPSEL_DCBHCOMPSEL_Pos)         /*!< 0x00000800 */
#define EPWM_DCTRIPSEL_DCBLCOMPSEL_Pos          (12U)
#define EPWM_DCTRIPSEL_DCBLCOMPSEL_Msk          (0xFUL<<EPWM_DCTRIPSEL_DCBLCOMPSEL_Pos)         /*!< 0x0000F000 */
#define EPWM_DCTRIPSEL_DCBLCOMPSEL              EPWM_DCTRIPSEL_DCBLCOMPSEL_Msk
#define EPWM_DCTRIPSEL_DCBLCOMPSEL_0            (0x1UL<<EPWM_DCTRIPSEL_DCBLCOMPSEL_Pos)         /*!< 0x00001000 */
#define EPWM_DCTRIPSEL_DCBLCOMPSEL_1            (0x2UL<<EPWM_DCTRIPSEL_DCBLCOMPSEL_Pos)         /*!< 0x00002000 */
#define EPWM_DCTRIPSEL_DCBLCOMPSEL_2            (0x4UL<<EPWM_DCTRIPSEL_DCBLCOMPSEL_Pos)         /*!< 0x00004000 */
#define EPWM_DCTRIPSEL_DCBLCOMPSEL_3            (0x8UL<<EPWM_DCTRIPSEL_DCBLCOMPSEL_Pos)         /*!< 0x00008000 */

/********************************* Bit definition for EPWM_DCACTL register ****************************************/
#define EPWM_DCACTL_EVT1SRCSEL_Pos              (0U)
#define EPWM_DCACTL_EVT1SRCSEL_Msk              (0x1UL<<EPWM_DCACTL_EVT1SRCSEL_Pos)             /*!< 0x00000001 */
#define EPWM_DCACTL_EVT1SRCSEL                  EPWM_DCACTL_EVT1SRCSEL_Msk                      
#define EPWM_DCACTL_EVT1FRCSYNCSEL_Pos          (1U)
#define EPWM_DCACTL_EVT1FRCSYNCSEL_Msk          (0x1UL<<EPWM_DCACTL_EVT1FRCSYNCSEL_Pos)         /*!< 0x00000002 */
#define EPWM_DCACTL_EVT1FRCSYNCSEL              EPWM_DCACTL_EVT1FRCSYNCSEL_Msk                  
#define EPWM_DCACTL_EVT1SOCE_Pos                (2U)
#define EPWM_DCACTL_EVT1SOCE_Msk                (0x1UL<<EPWM_DCACTL_EVT1SOCE_Pos)               /*!< 0x00000004 */
#define EPWM_DCACTL_EVT1SOCE                    EPWM_DCACTL_EVT1SOCE_Msk                        
#define EPWM_DCACTL_EVT1SYNCE_Pos               (3U)
#define EPWM_DCACTL_EVT1SYNCE_Msk               (0x1UL<<EPWM_DCACTL_EVT1SYNCE_Pos)              /*!< 0x00000008 */
#define EPWM_DCACTL_EVT1SYNCE                   EPWM_DCACTL_EVT1SYNCE_Msk                       
#define EPWM_DCACTL_EVT2SRCSEL_Pos              (8U)
#define EPWM_DCACTL_EVT2SRCSEL_Msk              (0x1UL<<EPWM_DCACTL_EVT2SRCSEL_Pos)             /*!< 0x00000100 */
#define EPWM_DCACTL_EVT2SRCSEL                  EPWM_DCACTL_EVT2SRCSEL_Msk                      
#define EPWM_DCACTL_EVT2FRCSYNCSEL_Pos          (9U)
#define EPWM_DCACTL_EVT2FRCSYNCSEL_Msk          (0x1UL<<EPWM_DCACTL_EVT2FRCSYNCSEL_Pos)         /*!< 0x00000200 */
#define EPWM_DCACTL_EVT2FRCSYNCSEL              EPWM_DCACTL_EVT2FRCSYNCSEL_Msk                  

/********************************* Bit definition for EPWM_DCBCTL register ****************************************/
#define EPWM_DCBCTL_EVT1SRCSEL_Pos              (0U)
#define EPWM_DCBCTL_EVT1SRCSEL_Msk              (0x1UL<<EPWM_DCBCTL_EVT1SRCSEL_Pos)             /*!< 0x00000001 */
#define EPWM_DCBCTL_EVT1SRCSEL                  EPWM_DCBCTL_EVT1SRCSEL_Msk                      
#define EPWM_DCBCTL_EVT1FRCSYNCSEL_Pos          (1U)
#define EPWM_DCBCTL_EVT1FRCSYNCSEL_Msk          (0x1UL<<EPWM_DCBCTL_EVT1FRCSYNCSEL_Pos)         /*!< 0x00000002 */
#define EPWM_DCBCTL_EVT1FRCSYNCSEL              EPWM_DCBCTL_EVT1FRCSYNCSEL_Msk                  
#define EPWM_DCBCTL_EVT1SOCE_Pos                (2U)
#define EPWM_DCBCTL_EVT1SOCE_Msk                (0x1UL<<EPWM_DCBCTL_EVT1SOCE_Pos)               /*!< 0x00000004 */
#define EPWM_DCBCTL_EVT1SOCE                    EPWM_DCBCTL_EVT1SOCE_Msk                        
#define EPWM_DCBCTL_EVT1SYNCE_Pos               (3U)
#define EPWM_DCBCTL_EVT1SYNCE_Msk               (0x1UL<<EPWM_DCBCTL_EVT1SYNCE_Pos)              /*!< 0x00000008 */
#define EPWM_DCBCTL_EVT1SYNCE                   EPWM_DCBCTL_EVT1SYNCE_Msk                       
#define EPWM_DCBCTL_EVT2SRCSEL_Pos              (8U)
#define EPWM_DCBCTL_EVT2SRCSEL_Msk              (0x1UL<<EPWM_DCBCTL_EVT2SRCSEL_Pos)             /*!< 0x00000100 */
#define EPWM_DCBCTL_EVT2SRCSEL                  EPWM_DCBCTL_EVT2SRCSEL_Msk                      
#define EPWM_DCBCTL_EVT2FRCSYNCSEL_Pos          (9U)
#define EPWM_DCBCTL_EVT2FRCSYNCSEL_Msk          (0x1UL<<EPWM_DCBCTL_EVT2FRCSYNCSEL_Pos)         /*!< 0x00000200 */
#define EPWM_DCBCTL_EVT2FRCSYNCSEL              EPWM_DCBCTL_EVT2FRCSYNCSEL_Msk                  

/********************************* Bit definition for EPWM_DCFCTL register ****************************************/
#define EPWM_DCFCTL_SRCSEL_Pos                  (0U)
#define EPWM_DCFCTL_SRCSEL_Msk                  (0x3UL<<EPWM_DCFCTL_SRCSEL_Pos)                 /*!< 0x00000003 */
#define EPWM_DCFCTL_SRCSEL                      EPWM_DCFCTL_SRCSEL_Msk
#define EPWM_DCFCTL_SRCSEL_0                    (0x1UL<<EPWM_DCFCTL_SRCSEL_Pos)                 /*!< 0x00000001 */
#define EPWM_DCFCTL_SRCSEL_1                    (0x2UL<<EPWM_DCFCTL_SRCSEL_Pos)                 /*!< 0x00000002 */
#define EPWM_DCFCTL_BLANKE_Pos                  (2U)
#define EPWM_DCFCTL_BLANKE_Msk                  (0x1UL<<EPWM_DCFCTL_BLANKE_Pos)                 /*!< 0x00000004 */
#define EPWM_DCFCTL_BLANKE                      EPWM_DCFCTL_BLANKE_Msk                          
#define EPWM_DCFCTL_BLANKINV_Pos                (3U)
#define EPWM_DCFCTL_BLANKINV_Msk                (0x1UL<<EPWM_DCFCTL_BLANKINV_Pos)               /*!< 0x00000008 */
#define EPWM_DCFCTL_BLANKINV                    EPWM_DCFCTL_BLANKINV_Msk                        
#define EPWM_DCFCTL_PULSESEL_Pos                (4U)
#define EPWM_DCFCTL_PULSESEL_Msk                (0x3UL<<EPWM_DCFCTL_PULSESEL_Pos)               /*!< 0x00000030 */
#define EPWM_DCFCTL_PULSESEL                    EPWM_DCFCTL_PULSESEL_Msk
#define EPWM_DCFCTL_PULSESEL_0                  (0x1UL<<EPWM_DCFCTL_PULSESEL_Pos)               /*!< 0x00000010 */
#define EPWM_DCFCTL_PULSESEL_1                  (0x2UL<<EPWM_DCFCTL_PULSESEL_Pos)               /*!< 0x00000020 */
#define EPWM_DCFCTL_EDGEFILTSEL_Pos             (6U)
#define EPWM_DCFCTL_EDGEFILTSEL_Msk             (0x1UL<<EPWM_DCFCTL_EDGEFILTSEL_Pos)            /*!< 0x00000040 */
#define EPWM_DCFCTL_EDGEFILTSEL                 EPWM_DCFCTL_EDGEFILTSEL_Msk                     
#define EPWM_DCFCTL_EDGEMODE_Pos                (8U)
#define EPWM_DCFCTL_EDGEMODE_Msk                (0x3UL<<EPWM_DCFCTL_EDGEMODE_Pos)               /*!< 0x00000300 */
#define EPWM_DCFCTL_EDGEMODE                    EPWM_DCFCTL_EDGEMODE_Msk
#define EPWM_DCFCTL_EDGEMODE_0                  (0x1UL<<EPWM_DCFCTL_EDGEMODE_Pos)               /*!< 0x00000100 */
#define EPWM_DCFCTL_EDGEMODE_1                  (0x2UL<<EPWM_DCFCTL_EDGEMODE_Pos)               /*!< 0x00000200 */
#define EPWM_DCFCTL_EDGECOUNT_Pos               (10U)
#define EPWM_DCFCTL_EDGECOUNT_Msk               (0x7UL<<EPWM_DCFCTL_EDGECOUNT_Pos)              /*!< 0x00001C00 */
#define EPWM_DCFCTL_EDGECOUNT                   EPWM_DCFCTL_EDGECOUNT_Msk
#define EPWM_DCFCTL_EDGECOUNT_0                 (0x1UL<<EPWM_DCFCTL_EDGECOUNT_Pos)              /*!< 0x00000400 */
#define EPWM_DCFCTL_EDGECOUNT_1                 (0x2UL<<EPWM_DCFCTL_EDGECOUNT_Pos)              /*!< 0x00000800 */
#define EPWM_DCFCTL_EDGECOUNT_2                 (0x4UL<<EPWM_DCFCTL_EDGECOUNT_Pos)              /*!< 0x00001000 */
#define EPWM_DCFCTL_EDGESTATUS_Pos              (13U)
#define EPWM_DCFCTL_EDGESTATUS_Msk              (0x7UL<<EPWM_DCFCTL_EDGESTATUS_Pos)             /*!< 0x0000E000 */
#define EPWM_DCFCTL_EDGESTATUS                  EPWM_DCFCTL_EDGESTATUS_Msk
#define EPWM_DCFCTL_EDGESTATUS_0                (0x1UL<<EPWM_DCFCTL_EDGESTATUS_Pos)             /*!< 0x00002000 */
#define EPWM_DCFCTL_EDGESTATUS_1                (0x2UL<<EPWM_DCFCTL_EDGESTATUS_Pos)             /*!< 0x00004000 */
#define EPWM_DCFCTL_EDGESTATUS_2                (0x4UL<<EPWM_DCFCTL_EDGESTATUS_Pos)             /*!< 0x00008000 */

/********************************* Bit definition for EPWM_DCCAPCTL register **************************************/
#define EPWM_DCCAPCTL_CAPE_Pos                  (0U)
#define EPWM_DCCAPCTL_CAPE_Msk                  (0x1UL<<EPWM_DCCAPCTL_CAPE_Pos)                 /*!< 0x00000001 */
#define EPWM_DCCAPCTL_CAPE                      EPWM_DCCAPCTL_CAPE_Msk                          
#define EPWM_DCCAPCTL_SHDWMODE_Pos              (1U)
#define EPWM_DCCAPCTL_SHDWMODE_Msk              (0x1UL<<EPWM_DCCAPCTL_SHDWMODE_Pos)             /*!< 0x00000002 */
#define EPWM_DCCAPCTL_SHDWMODE                  EPWM_DCCAPCTL_SHDWMODE_Msk                      
#define EPWM_DCCAPCTL_CAPSTS_Pos                (13U)
#define EPWM_DCCAPCTL_CAPSTS_Msk                (0x1UL<<EPWM_DCCAPCTL_CAPSTS_Pos)               /*!< 0x00002000 */
#define EPWM_DCCAPCTL_CAPSTS                    EPWM_DCCAPCTL_CAPSTS_Msk                        
#define EPWM_DCCAPCTL_CAPCLR_Pos                (14U)
#define EPWM_DCCAPCTL_CAPCLR_Msk                (0x1UL<<EPWM_DCCAPCTL_CAPCLR_Pos)               /*!< 0x00004000 */
#define EPWM_DCCAPCTL_CAPCLR                    EPWM_DCCAPCTL_CAPCLR_Msk                        
#define EPWM_DCCAPCTL_CAPMODE_Pos               (15U)
#define EPWM_DCCAPCTL_CAPMODE_Msk               (0x1UL<<EPWM_DCCAPCTL_CAPMODE_Pos)              /*!< 0x00008000 */
#define EPWM_DCCAPCTL_CAPMODE                   EPWM_DCCAPCTL_CAPMODE_Msk                       

/********************************* Bit definition for EPWM_DCFOFFSET register *************************************/
#define EPWM_DCFOFFSET_DCFOFFSET_Pos            (0U)
#define EPWM_DCFOFFSET_DCFOFFSET_Msk            (0xFFFFUL<<EPWM_DCFOFFSET_DCFOFFSET_Pos)        /*!< 0x0000FFFF */
#define EPWM_DCFOFFSET_DCFOFFSET                EPWM_DCFOFFSET_DCFOFFSET_Msk

/********************************* Bit definition for EPWM_DCFOFFSETCNT register **********************************/
#define EPWM_DCFOFFSETCNT_DCFOFFSETCNT_Pos      (0U)
#define EPWM_DCFOFFSETCNT_DCFOFFSETCNT_Msk      (0xFFFFUL<<EPWM_DCFOFFSETCNT_DCFOFFSETCNT_Pos)  /*!< 0x0000FFFF */
#define EPWM_DCFOFFSETCNT_DCFOFFSETCNT          EPWM_DCFOFFSETCNT_DCFOFFSETCNT_Msk

/********************************* Bit definition for EPWM_DCFWINDOW register *************************************/
#define EPWM_DCFWINDOW_DCFWINDOW_Pos            (0U)
#define EPWM_DCFWINDOW_DCFWINDOW_Msk            (0xFFFFUL<<EPWM_DCFWINDOW_DCFWINDOW_Pos)        /*!< 0x0000FFFF */
#define EPWM_DCFWINDOW_DCFWINDOW                EPWM_DCFWINDOW_DCFWINDOW_Msk

/********************************* Bit definition for EPWM_DCFWINDOWCNT register **********************************/
#define EPWM_DCFWINDOWCNT_DCFWINDOWCNT_Pos      (0U)
#define EPWM_DCFWINDOWCNT_DCFWINDOWCNT_Msk      (0xFFFFUL<<EPWM_DCFWINDOWCNT_DCFWINDOWCNT_Pos)  /*!< 0x0000FFFF */
#define EPWM_DCFWINDOWCNT_DCFWINDOWCNT          EPWM_DCFWINDOWCNT_DCFWINDOWCNT_Msk

/********************************* Bit definition for EPWM_DCCAP register *****************************************/
#define EPWM_DCCAP_DCCAP_Pos                    (0U)
#define EPWM_DCCAP_DCCAP_Msk                    (0xFFFFUL<<EPWM_DCCAP_DCCAP_Pos)                /*!< 0x0000FFFF */
#define EPWM_DCCAP_DCCAP                        EPWM_DCCAP_DCCAP_Msk

/********************************* Bit definition for EPWM_DCAHTRIPSEL register ***********************************/
#define EPWM_DCAHTRIPSEL_TRIPINPUT1_Pos         (0U)
#define EPWM_DCAHTRIPSEL_TRIPINPUT1_Msk         (0x1UL<<EPWM_DCAHTRIPSEL_TRIPINPUT1_Pos)        /*!< 0x00000001 */
#define EPWM_DCAHTRIPSEL_TRIPINPUT1             EPWM_DCAHTRIPSEL_TRIPINPUT1_Msk                 
#define EPWM_DCAHTRIPSEL_TRIPINPUT2_Pos         (1U)
#define EPWM_DCAHTRIPSEL_TRIPINPUT2_Msk         (0x1UL<<EPWM_DCAHTRIPSEL_TRIPINPUT2_Pos)        /*!< 0x00000002 */
#define EPWM_DCAHTRIPSEL_TRIPINPUT2             EPWM_DCAHTRIPSEL_TRIPINPUT2_Msk                 
#define EPWM_DCAHTRIPSEL_TRIPINPUT3_Pos         (2U)
#define EPWM_DCAHTRIPSEL_TRIPINPUT3_Msk         (0x1UL<<EPWM_DCAHTRIPSEL_TRIPINPUT3_Pos)        /*!< 0x00000004 */
#define EPWM_DCAHTRIPSEL_TRIPINPUT3             EPWM_DCAHTRIPSEL_TRIPINPUT3_Msk                 
#define EPWM_DCAHTRIPSEL_TRIPINPUT4_Pos         (3U)
#define EPWM_DCAHTRIPSEL_TRIPINPUT4_Msk         (0x1UL<<EPWM_DCAHTRIPSEL_TRIPINPUT4_Pos)        /*!< 0x00000008 */
#define EPWM_DCAHTRIPSEL_TRIPINPUT4             EPWM_DCAHTRIPSEL_TRIPINPUT4_Msk                 
#define EPWM_DCAHTRIPSEL_TRIPINPUT5_Pos         (4U)
#define EPWM_DCAHTRIPSEL_TRIPINPUT5_Msk         (0x1UL<<EPWM_DCAHTRIPSEL_TRIPINPUT5_Pos)        /*!< 0x00000010 */
#define EPWM_DCAHTRIPSEL_TRIPINPUT5             EPWM_DCAHTRIPSEL_TRIPINPUT5_Msk                 
#define EPWM_DCAHTRIPSEL_TRIPINPUT6_Pos         (5U)
#define EPWM_DCAHTRIPSEL_TRIPINPUT6_Msk         (0x1UL<<EPWM_DCAHTRIPSEL_TRIPINPUT6_Pos)        /*!< 0x00000020 */
#define EPWM_DCAHTRIPSEL_TRIPINPUT6             EPWM_DCAHTRIPSEL_TRIPINPUT6_Msk                 
#define EPWM_DCAHTRIPSEL_TRIPINPUT7_Pos         (6U)
#define EPWM_DCAHTRIPSEL_TRIPINPUT7_Msk         (0x1UL<<EPWM_DCAHTRIPSEL_TRIPINPUT7_Pos)        /*!< 0x00000040 */
#define EPWM_DCAHTRIPSEL_TRIPINPUT7             EPWM_DCAHTRIPSEL_TRIPINPUT7_Msk                 
#define EPWM_DCAHTRIPSEL_TRIPINPUT8_Pos         (7U)
#define EPWM_DCAHTRIPSEL_TRIPINPUT8_Msk         (0x1UL<<EPWM_DCAHTRIPSEL_TRIPINPUT8_Pos)        /*!< 0x00000080 */
#define EPWM_DCAHTRIPSEL_TRIPINPUT8             EPWM_DCAHTRIPSEL_TRIPINPUT8_Msk                 
#define EPWM_DCAHTRIPSEL_TRIPINPUT9_Pos         (8U)
#define EPWM_DCAHTRIPSEL_TRIPINPUT9_Msk         (0x1UL<<EPWM_DCAHTRIPSEL_TRIPINPUT9_Pos)        /*!< 0x00000100 */
#define EPWM_DCAHTRIPSEL_TRIPINPUT9             EPWM_DCAHTRIPSEL_TRIPINPUT9_Msk                 
#define EPWM_DCAHTRIPSEL_TRIPINPUT10_Pos        (9U)
#define EPWM_DCAHTRIPSEL_TRIPINPUT10_Msk        (0x1UL<<EPWM_DCAHTRIPSEL_TRIPINPUT10_Pos)       /*!< 0x00000200 */
#define EPWM_DCAHTRIPSEL_TRIPINPUT10            EPWM_DCAHTRIPSEL_TRIPINPUT10_Msk                
#define EPWM_DCAHTRIPSEL_TRIPINPUT11_Pos        (10U)
#define EPWM_DCAHTRIPSEL_TRIPINPUT11_Msk        (0x1UL<<EPWM_DCAHTRIPSEL_TRIPINPUT11_Pos)       /*!< 0x00000400 */
#define EPWM_DCAHTRIPSEL_TRIPINPUT11            EPWM_DCAHTRIPSEL_TRIPINPUT11_Msk                
#define EPWM_DCAHTRIPSEL_TRIPINPUT12_Pos        (11U)
#define EPWM_DCAHTRIPSEL_TRIPINPUT12_Msk        (0x1UL<<EPWM_DCAHTRIPSEL_TRIPINPUT12_Pos)       /*!< 0x00000800 */
#define EPWM_DCAHTRIPSEL_TRIPINPUT12            EPWM_DCAHTRIPSEL_TRIPINPUT12_Msk                

/********************************* Bit definition for EPWM_DCALTRIPSEL register ***********************************/
#define EPWM_DCALTRIPSEL_TRIPINPUT1_Pos         (0U)
#define EPWM_DCALTRIPSEL_TRIPINPUT1_Msk         (0x1UL<<EPWM_DCALTRIPSEL_TRIPINPUT1_Pos)        /*!< 0x00000001 */
#define EPWM_DCALTRIPSEL_TRIPINPUT1             EPWM_DCALTRIPSEL_TRIPINPUT1_Msk                 
#define EPWM_DCALTRIPSEL_TRIPINPUT2_Pos         (1U)
#define EPWM_DCALTRIPSEL_TRIPINPUT2_Msk         (0x1UL<<EPWM_DCALTRIPSEL_TRIPINPUT2_Pos)        /*!< 0x00000002 */
#define EPWM_DCALTRIPSEL_TRIPINPUT2             EPWM_DCALTRIPSEL_TRIPINPUT2_Msk                 
#define EPWM_DCALTRIPSEL_TRIPINPUT3_Pos         (2U)
#define EPWM_DCALTRIPSEL_TRIPINPUT3_Msk         (0x1UL<<EPWM_DCALTRIPSEL_TRIPINPUT3_Pos)        /*!< 0x00000004 */
#define EPWM_DCALTRIPSEL_TRIPINPUT3             EPWM_DCALTRIPSEL_TRIPINPUT3_Msk                 
#define EPWM_DCALTRIPSEL_TRIPINPUT4_Pos         (3U)
#define EPWM_DCALTRIPSEL_TRIPINPUT4_Msk         (0x1UL<<EPWM_DCALTRIPSEL_TRIPINPUT4_Pos)        /*!< 0x00000008 */
#define EPWM_DCALTRIPSEL_TRIPINPUT4             EPWM_DCALTRIPSEL_TRIPINPUT4_Msk                 
#define EPWM_DCALTRIPSEL_TRIPINPUT5_Pos         (4U)
#define EPWM_DCALTRIPSEL_TRIPINPUT5_Msk         (0x1UL<<EPWM_DCALTRIPSEL_TRIPINPUT5_Pos)        /*!< 0x00000010 */
#define EPWM_DCALTRIPSEL_TRIPINPUT5             EPWM_DCALTRIPSEL_TRIPINPUT5_Msk                 
#define EPWM_DCALTRIPSEL_TRIPINPUT6_Pos         (5U)
#define EPWM_DCALTRIPSEL_TRIPINPUT6_Msk         (0x1UL<<EPWM_DCALTRIPSEL_TRIPINPUT6_Pos)        /*!< 0x00000020 */
#define EPWM_DCALTRIPSEL_TRIPINPUT6             EPWM_DCALTRIPSEL_TRIPINPUT6_Msk                 
#define EPWM_DCALTRIPSEL_TRIPINPUT7_Pos         (6U)
#define EPWM_DCALTRIPSEL_TRIPINPUT7_Msk         (0x1UL<<EPWM_DCALTRIPSEL_TRIPINPUT7_Pos)        /*!< 0x00000040 */
#define EPWM_DCALTRIPSEL_TRIPINPUT7             EPWM_DCALTRIPSEL_TRIPINPUT7_Msk                 
#define EPWM_DCALTRIPSEL_TRIPINPUT8_Pos         (7U)
#define EPWM_DCALTRIPSEL_TRIPINPUT8_Msk         (0x1UL<<EPWM_DCALTRIPSEL_TRIPINPUT8_Pos)        /*!< 0x00000080 */
#define EPWM_DCALTRIPSEL_TRIPINPUT8             EPWM_DCALTRIPSEL_TRIPINPUT8_Msk                 
#define EPWM_DCALTRIPSEL_TRIPINPUT9_Pos         (8U)
#define EPWM_DCALTRIPSEL_TRIPINPUT9_Msk         (0x1UL<<EPWM_DCALTRIPSEL_TRIPINPUT9_Pos)        /*!< 0x00000100 */
#define EPWM_DCALTRIPSEL_TRIPINPUT9             EPWM_DCALTRIPSEL_TRIPINPUT9_Msk                 
#define EPWM_DCALTRIPSEL_TRIPINPUT10_Pos        (9U)
#define EPWM_DCALTRIPSEL_TRIPINPUT10_Msk        (0x1UL<<EPWM_DCALTRIPSEL_TRIPINPUT10_Pos)       /*!< 0x00000200 */
#define EPWM_DCALTRIPSEL_TRIPINPUT10            EPWM_DCALTRIPSEL_TRIPINPUT10_Msk                
#define EPWM_DCALTRIPSEL_TRIPINPUT11_Pos        (10U)
#define EPWM_DCALTRIPSEL_TRIPINPUT11_Msk        (0x1UL<<EPWM_DCALTRIPSEL_TRIPINPUT11_Pos)       /*!< 0x00000400 */
#define EPWM_DCALTRIPSEL_TRIPINPUT11            EPWM_DCALTRIPSEL_TRIPINPUT11_Msk                
#define EPWM_DCALTRIPSEL_TRIPINPUT12_Pos        (11U)
#define EPWM_DCALTRIPSEL_TRIPINPUT12_Msk        (0x1UL<<EPWM_DCALTRIPSEL_TRIPINPUT12_Pos)       /*!< 0x00000800 */
#define EPWM_DCALTRIPSEL_TRIPINPUT12            EPWM_DCALTRIPSEL_TRIPINPUT12_Msk                

/********************************* Bit definition for EPWM_DCBHTRIPSEL register ***********************************/
#define EPWM_DCBHTRIPSEL_TRIPINPUT1_Pos         (0U)
#define EPWM_DCBHTRIPSEL_TRIPINPUT1_Msk         (0x1UL<<EPWM_DCBHTRIPSEL_TRIPINPUT1_Pos)        /*!< 0x00000001 */
#define EPWM_DCBHTRIPSEL_TRIPINPUT1             EPWM_DCBHTRIPSEL_TRIPINPUT1_Msk                 
#define EPWM_DCBHTRIPSEL_TRIPINPUT2_Pos         (1U)
#define EPWM_DCBHTRIPSEL_TRIPINPUT2_Msk         (0x1UL<<EPWM_DCBHTRIPSEL_TRIPINPUT2_Pos)        /*!< 0x00000002 */
#define EPWM_DCBHTRIPSEL_TRIPINPUT2             EPWM_DCBHTRIPSEL_TRIPINPUT2_Msk                 
#define EPWM_DCBHTRIPSEL_TRIPINPUT3_Pos         (2U)
#define EPWM_DCBHTRIPSEL_TRIPINPUT3_Msk         (0x1UL<<EPWM_DCBHTRIPSEL_TRIPINPUT3_Pos)        /*!< 0x00000004 */
#define EPWM_DCBHTRIPSEL_TRIPINPUT3             EPWM_DCBHTRIPSEL_TRIPINPUT3_Msk                 
#define EPWM_DCBHTRIPSEL_TRIPINPUT4_Pos         (3U)
#define EPWM_DCBHTRIPSEL_TRIPINPUT4_Msk         (0x1UL<<EPWM_DCBHTRIPSEL_TRIPINPUT4_Pos)        /*!< 0x00000008 */
#define EPWM_DCBHTRIPSEL_TRIPINPUT4             EPWM_DCBHTRIPSEL_TRIPINPUT4_Msk                 
#define EPWM_DCBHTRIPSEL_TRIPINPUT5_Pos         (4U)
#define EPWM_DCBHTRIPSEL_TRIPINPUT5_Msk         (0x1UL<<EPWM_DCBHTRIPSEL_TRIPINPUT5_Pos)        /*!< 0x00000010 */
#define EPWM_DCBHTRIPSEL_TRIPINPUT5             EPWM_DCBHTRIPSEL_TRIPINPUT5_Msk                 
#define EPWM_DCBHTRIPSEL_TRIPINPUT6_Pos         (5U)
#define EPWM_DCBHTRIPSEL_TRIPINPUT6_Msk         (0x1UL<<EPWM_DCBHTRIPSEL_TRIPINPUT6_Pos)        /*!< 0x00000020 */
#define EPWM_DCBHTRIPSEL_TRIPINPUT6             EPWM_DCBHTRIPSEL_TRIPINPUT6_Msk                 
#define EPWM_DCBHTRIPSEL_TRIPINPUT7_Pos         (6U)
#define EPWM_DCBHTRIPSEL_TRIPINPUT7_Msk         (0x1UL<<EPWM_DCBHTRIPSEL_TRIPINPUT7_Pos)        /*!< 0x00000040 */
#define EPWM_DCBHTRIPSEL_TRIPINPUT7             EPWM_DCBHTRIPSEL_TRIPINPUT7_Msk                 
#define EPWM_DCBHTRIPSEL_TRIPINPUT8_Pos         (7U)
#define EPWM_DCBHTRIPSEL_TRIPINPUT8_Msk         (0x1UL<<EPWM_DCBHTRIPSEL_TRIPINPUT8_Pos)        /*!< 0x00000080 */
#define EPWM_DCBHTRIPSEL_TRIPINPUT8             EPWM_DCBHTRIPSEL_TRIPINPUT8_Msk                 
#define EPWM_DCBHTRIPSEL_TRIPINPUT9_Pos         (8U)
#define EPWM_DCBHTRIPSEL_TRIPINPUT9_Msk         (0x1UL<<EPWM_DCBHTRIPSEL_TRIPINPUT9_Pos)        /*!< 0x00000100 */
#define EPWM_DCBHTRIPSEL_TRIPINPUT9             EPWM_DCBHTRIPSEL_TRIPINPUT9_Msk                 
#define EPWM_DCBHTRIPSEL_TRIPINPUT10_Pos        (9U)
#define EPWM_DCBHTRIPSEL_TRIPINPUT10_Msk        (0x1UL<<EPWM_DCBHTRIPSEL_TRIPINPUT10_Pos)       /*!< 0x00000200 */
#define EPWM_DCBHTRIPSEL_TRIPINPUT10            EPWM_DCBHTRIPSEL_TRIPINPUT10_Msk                
#define EPWM_DCBHTRIPSEL_TRIPINPUT11_Pos        (10U)
#define EPWM_DCBHTRIPSEL_TRIPINPUT11_Msk        (0x1UL<<EPWM_DCBHTRIPSEL_TRIPINPUT11_Pos)       /*!< 0x00000400 */
#define EPWM_DCBHTRIPSEL_TRIPINPUT11            EPWM_DCBHTRIPSEL_TRIPINPUT11_Msk                
#define EPWM_DCBHTRIPSEL_TRIPINPUT12_Pos        (11U)
#define EPWM_DCBHTRIPSEL_TRIPINPUT12_Msk        (0x1UL<<EPWM_DCBHTRIPSEL_TRIPINPUT12_Pos)       /*!< 0x00000800 */
#define EPWM_DCBHTRIPSEL_TRIPINPUT12            EPWM_DCBHTRIPSEL_TRIPINPUT12_Msk                

/********************************* Bit definition for EPWM_DCBLTRIPSEL register ***********************************/
#define EPWM_DCBLTRIPSEL_TRIPINPUT1_Pos         (0U)
#define EPWM_DCBLTRIPSEL_TRIPINPUT1_Msk         (0x1UL<<EPWM_DCBLTRIPSEL_TRIPINPUT1_Pos)        /*!< 0x00000001 */
#define EPWM_DCBLTRIPSEL_TRIPINPUT1             EPWM_DCBLTRIPSEL_TRIPINPUT1_Msk                 
#define EPWM_DCBLTRIPSEL_TRIPINPUT2_Pos         (1U)
#define EPWM_DCBLTRIPSEL_TRIPINPUT2_Msk         (0x1UL<<EPWM_DCBLTRIPSEL_TRIPINPUT2_Pos)        /*!< 0x00000002 */
#define EPWM_DCBLTRIPSEL_TRIPINPUT2             EPWM_DCBLTRIPSEL_TRIPINPUT2_Msk                 
#define EPWM_DCBLTRIPSEL_TRIPINPUT3_Pos         (2U)
#define EPWM_DCBLTRIPSEL_TRIPINPUT3_Msk         (0x1UL<<EPWM_DCBLTRIPSEL_TRIPINPUT3_Pos)        /*!< 0x00000004 */
#define EPWM_DCBLTRIPSEL_TRIPINPUT3             EPWM_DCBLTRIPSEL_TRIPINPUT3_Msk                 
#define EPWM_DCBLTRIPSEL_TRIPINPUT4_Pos         (3U)
#define EPWM_DCBLTRIPSEL_TRIPINPUT4_Msk         (0x1UL<<EPWM_DCBLTRIPSEL_TRIPINPUT4_Pos)        /*!< 0x00000008 */
#define EPWM_DCBLTRIPSEL_TRIPINPUT4             EPWM_DCBLTRIPSEL_TRIPINPUT4_Msk                 
#define EPWM_DCBLTRIPSEL_TRIPINPUT5_Pos         (4U)
#define EPWM_DCBLTRIPSEL_TRIPINPUT5_Msk         (0x1UL<<EPWM_DCBLTRIPSEL_TRIPINPUT5_Pos)        /*!< 0x00000010 */
#define EPWM_DCBLTRIPSEL_TRIPINPUT5             EPWM_DCBLTRIPSEL_TRIPINPUT5_Msk                 
#define EPWM_DCBLTRIPSEL_TRIPINPUT6_Pos         (5U)
#define EPWM_DCBLTRIPSEL_TRIPINPUT6_Msk         (0x1UL<<EPWM_DCBLTRIPSEL_TRIPINPUT6_Pos)        /*!< 0x00000020 */
#define EPWM_DCBLTRIPSEL_TRIPINPUT6             EPWM_DCBLTRIPSEL_TRIPINPUT6_Msk                 
#define EPWM_DCBLTRIPSEL_TRIPINPUT7_Pos         (6U)
#define EPWM_DCBLTRIPSEL_TRIPINPUT7_Msk         (0x1UL<<EPWM_DCBLTRIPSEL_TRIPINPUT7_Pos)        /*!< 0x00000040 */
#define EPWM_DCBLTRIPSEL_TRIPINPUT7             EPWM_DCBLTRIPSEL_TRIPINPUT7_Msk                 
#define EPWM_DCBLTRIPSEL_TRIPINPUT8_Pos         (7U)
#define EPWM_DCBLTRIPSEL_TRIPINPUT8_Msk         (0x1UL<<EPWM_DCBLTRIPSEL_TRIPINPUT8_Pos)        /*!< 0x00000080 */
#define EPWM_DCBLTRIPSEL_TRIPINPUT8             EPWM_DCBLTRIPSEL_TRIPINPUT8_Msk                 
#define EPWM_DCBLTRIPSEL_TRIPINPUT9_Pos         (8U)
#define EPWM_DCBLTRIPSEL_TRIPINPUT9_Msk         (0x1UL<<EPWM_DCBLTRIPSEL_TRIPINPUT9_Pos)        /*!< 0x00000100 */
#define EPWM_DCBLTRIPSEL_TRIPINPUT9             EPWM_DCBLTRIPSEL_TRIPINPUT9_Msk                 
#define EPWM_DCBLTRIPSEL_TRIPINPUT10_Pos        (9U)
#define EPWM_DCBLTRIPSEL_TRIPINPUT10_Msk        (0x1UL<<EPWM_DCBLTRIPSEL_TRIPINPUT10_Pos)       /*!< 0x00000200 */
#define EPWM_DCBLTRIPSEL_TRIPINPUT10            EPWM_DCBLTRIPSEL_TRIPINPUT10_Msk                
#define EPWM_DCBLTRIPSEL_TRIPINPUT11_Pos        (10U)
#define EPWM_DCBLTRIPSEL_TRIPINPUT11_Msk        (0x1UL<<EPWM_DCBLTRIPSEL_TRIPINPUT11_Pos)       /*!< 0x00000400 */
#define EPWM_DCBLTRIPSEL_TRIPINPUT11            EPWM_DCBLTRIPSEL_TRIPINPUT11_Msk                
#define EPWM_DCBLTRIPSEL_TRIPINPUT12_Pos        (11U)
#define EPWM_DCBLTRIPSEL_TRIPINPUT12_Msk        (0x1UL<<EPWM_DCBLTRIPSEL_TRIPINPUT12_Pos)       /*!< 0x00000800 */
#define EPWM_DCBLTRIPSEL_TRIPINPUT12            EPWM_DCBLTRIPSEL_TRIPINPUT12_Msk                

/********************************* Bit definition for EPWM_EPWMLOCK register *************************************/
#define EPWM_EPWMLOCK_HRLOCK_Pos               (0U)
#define EPWM_EPWMLOCK_HRLOCK_Msk               (0x1UL<<EPWM_EPWMLOCK_HRLOCK_Pos)              /*!< 0x00000001 */
#define EPWM_EPWMLOCK_HRLOCK                   EPWM_EPWMLOCK_HRLOCK_Msk                       
#define EPWM_EPWMLOCK_GLLOCK_Pos               (1U)
#define EPWM_EPWMLOCK_GLLOCK_Msk               (0x1UL<<EPWM_EPWMLOCK_GLLOCK_Pos)              /*!< 0x00000002 */
#define EPWM_EPWMLOCK_GLLOCK                   EPWM_EPWMLOCK_GLLOCK_Msk                       
#define EPWM_EPWMLOCK_TZCFGLOCK_Pos            (2U)
#define EPWM_EPWMLOCK_TZCFGLOCK_Msk            (0x1UL<<EPWM_EPWMLOCK_TZCFGLOCK_Pos)           /*!< 0x00000004 */
#define EPWM_EPWMLOCK_TZCFGLOCK                EPWM_EPWMLOCK_TZCFGLOCK_Msk                    
#define EPWM_EPWMLOCK_TZCLRLOCK_Pos            (3U)
#define EPWM_EPWMLOCK_TZCLRLOCK_Msk            (0x1UL<<EPWM_EPWMLOCK_TZCLRLOCK_Pos)           /*!< 0x00000008 */
#define EPWM_EPWMLOCK_TZCLRLOCK                EPWM_EPWMLOCK_TZCLRLOCK_Msk                    
#define EPWM_EPWMLOCK_DCLOCK_Pos               (4U)
#define EPWM_EPWMLOCK_DCLOCK_Msk               (0x1UL<<EPWM_EPWMLOCK_DCLOCK_Pos)              /*!< 0x00000010 */
#define EPWM_EPWMLOCK_DCLOCK                   EPWM_EPWMLOCK_DCLOCK_Msk                       
#define EPWM_EPWMLOCK_KEY_Pos                  (16U)
#define EPWM_EPWMLOCK_KEY_Msk                  (0xFFFFUL<<EPWM_EPWMLOCK_KEY_Pos)              /*!< 0xFFFF0000 */
#define EPWM_EPWMLOCK_KEY                      EPWM_EPWMLOCK_KEY_Msk

/********************************* Bit definition for EPWM_HWVDELVAL register *************************************/
#define EPWM_HWVDELVAL_HWVDELVAL_Pos            (0U)
#define EPWM_HWVDELVAL_HWVDELVAL_Msk            (0xFFFFUL<<EPWM_HWVDELVAL_HWVDELVAL_Pos)        /*!< 0x0000FFFF */
#define EPWM_HWVDELVAL_HWVDELVAL                EPWM_HWVDELVAL_HWVDELVAL_Msk

/********************************* Bit definition for EPWM_VCNTVAL register ***************************************/
#define EPWM_VCNTVAL_VCNTVAL_Pos                (0U)
#define EPWM_VCNTVAL_VCNTVAL_Msk                (0xFFFFUL<<EPWM_VCNTVAL_VCNTVAL_Pos)            /*!< 0x0000FFFF */
#define EPWM_VCNTVAL_VCNTVAL                    EPWM_VCNTVAL_VCNTVAL_Msk

/********************************************************************************************************************/
/********************************* LPTIM *************************************************************************/
/********************************************************************************************************************/

/********************************* Bit definition for LPTIM_ISR register ********************************************/
#define LPTIM_ISR_CMPM_Pos                        (0U)
#define LPTIM_ISR_CMPM_Msk                        (0x1UL<<LPTIM_ISR_CMPM_Pos)                       /*!< 0x00000001 */
#define LPTIM_ISR_CMPM                            LPTIM_ISR_CMPM_Msk                                /*!< Compare match */
#define LPTIM_ISR_ARRM_Pos                        (1U)
#define LPTIM_ISR_ARRM_Msk                        (0x1UL<<LPTIM_ISR_ARRM_Pos)                       /*!< 0x00000002 */
#define LPTIM_ISR_ARRM                            LPTIM_ISR_ARRM_Msk                                /*!< Autoreload match */
#define LPTIM_ISR_EXTTRIG_Pos                     (2U)
#define LPTIM_ISR_EXTTRIG_Msk                     (0x1UL<<LPTIM_ISR_EXTTRIG_Pos)                    /*!< 0x00000004 */
#define LPTIM_ISR_EXTTRIG                         LPTIM_ISR_EXTTRIG_Msk                             /*!< External trigger edge event */
#define LPTIM_ISR_CMPOK_Pos                       (3U)
#define LPTIM_ISR_CMPOK_Msk                       (0x1UL<<LPTIM_ISR_CMPOK_Pos)                      /*!< 0x00000008 */
#define LPTIM_ISR_CMPOK                           LPTIM_ISR_CMPOK_Msk                               /*!< Compare register update OK */
#define LPTIM_ISR_ARROK_Pos                       (4U)
#define LPTIM_ISR_ARROK_Msk                       (0x1UL<<LPTIM_ISR_ARROK_Pos)                      /*!< 0x00000010 */
#define LPTIM_ISR_ARROK                           LPTIM_ISR_ARROK_Msk                               /*!< Autoreload register update OK */
#define LPTIM_ISR_UP_Pos                          (5U)
#define LPTIM_ISR_UP_Msk                          (0x1UL<<LPTIM_ISR_UP_Pos)                         /*!< 0x00000020 */
#define LPTIM_ISR_UP                              LPTIM_ISR_UP_Msk                                  /*!< Counter direction change down to up */
#define LPTIM_ISR_DOWN_Pos                        (6U)
#define LPTIM_ISR_DOWN_Msk                        (0x1UL<<LPTIM_ISR_DOWN_Pos)                       /*!< 0x00000040 */
#define LPTIM_ISR_DOWN                            LPTIM_ISR_DOWN_Msk                                /*!< Counter direction change up to down */

/********************************* Bit definition for LPTIM_ICR register ********************************************/
#define LPTIM_ICR_CMPMCF_Pos                      (0U)
#define LPTIM_ICR_CMPMCF_Msk                      (0x1UL<<LPTIM_ICR_CMPMCF_Pos)                     /*!< 0x00000001 */
#define LPTIM_ICR_CMPMCF                          LPTIM_ICR_CMPMCF_Msk                              /*!< Compare match clear flag */
#define LPTIM_ICR_ARRMCF_Pos                      (1U)
#define LPTIM_ICR_ARRMCF_Msk                      (0x1UL<<LPTIM_ICR_ARRMCF_Pos)                     /*!< 0x00000002 */
#define LPTIM_ICR_ARRMCF                          LPTIM_ICR_ARRMCF_Msk                              /*!< Autoreload match clear flag */
#define LPTIM_ICR_EXTTRIGCF_Pos                   (2U)
#define LPTIM_ICR_EXTTRIGCF_Msk                   (0x1UL<<LPTIM_ICR_EXTTRIGCF_Pos)                  /*!< 0x00000004 */
#define LPTIM_ICR_EXTTRIGCF                       LPTIM_ICR_EXTTRIGCF_Msk                           /*!< External trigger valid edge clear flag */
#define LPTIM_ICR_CMPOKCF_Pos                     (3U)
#define LPTIM_ICR_CMPOKCF_Msk                     (0x1UL<<LPTIM_ICR_CMPOKCF_Pos)                    /*!< 0x00000008 */
#define LPTIM_ICR_CMPOKCF                         LPTIM_ICR_CMPOKCF_Msk                             /*!< Compare register update OK clear flag */
#define LPTIM_ICR_ARROKCF_Pos                     (4U)
#define LPTIM_ICR_ARROKCF_Msk                     (0x1UL<<LPTIM_ICR_ARROKCF_Pos)                    /*!< 0x00000010 */
#define LPTIM_ICR_ARROKCF                         LPTIM_ICR_ARROKCF_Msk                             /*!< Autoreload register update OK clear flag */
#define LPTIM_ICR_UPCF_Pos                        (5U)
#define LPTIM_ICR_UPCF_Msk                        (0x1UL<<LPTIM_ICR_UPCF_Pos)                       /*!< 0x00000020 */
#define LPTIM_ICR_UPCF                            LPTIM_ICR_UPCF_Msk                                /*!< Direction change to UP clear flag */
#define LPTIM_ICR_DOWNCF_Pos                      (6U)
#define LPTIM_ICR_DOWNCF_Msk                      (0x1UL<<LPTIM_ICR_DOWNCF_Pos)                     /*!< 0x00000040 */
#define LPTIM_ICR_DOWNCF                          LPTIM_ICR_DOWNCF_Msk                              /*!< Direction change to down clear flag */

/********************************* Bit definition for LPTIM_IER register ********************************************/
#define LPTIM_IER_CMPMIE_Pos                      (0U)
#define LPTIM_IER_CMPMIE_Msk                      (0x1UL<<LPTIM_IER_CMPMIE_Pos)                     /*!< 0x00000001 */
#define LPTIM_IER_CMPMIE                          LPTIM_IER_CMPMIE_Msk                              /*!< Compare match Interrupt Enable */
#define LPTIM_IER_ARRMIE_Pos                      (1U)
#define LPTIM_IER_ARRMIE_Msk                      (0x1UL<<LPTIM_IER_ARRMIE_Pos)                     /*!< 0x00000002 */
#define LPTIM_IER_ARRMIE                          LPTIM_IER_ARRMIE_Msk                              /*!< Autoreload match Interrupt Enable */
#define LPTIM_IER_EXTTRIGIE_Pos                   (2U)
#define LPTIM_IER_EXTTRIGIE_Msk                   (0x1UL<<LPTIM_IER_EXTTRIGIE_Pos)                  /*!< 0x00000004 */
#define LPTIM_IER_EXTTRIGIE                       LPTIM_IER_EXTTRIGIE_Msk                           /*!< External trigger valid edge Interrupt Enable */
#define LPTIM_IER_CMPOKIE_Pos                     (3U)
#define LPTIM_IER_CMPOKIE_Msk                     (0x1UL<<LPTIM_IER_CMPOKIE_Pos)                    /*!< 0x00000008 */
#define LPTIM_IER_CMPOKIE                         LPTIM_IER_CMPOKIE_Msk                             /*!< Compare register update OK Interrupt Enable */
#define LPTIM_IER_ARROKIE_Pos                     (4U)
#define LPTIM_IER_ARROKIE_Msk                     (0x1UL<<LPTIM_IER_ARROKIE_Pos)                    /*!< 0x00000010 */
#define LPTIM_IER_ARROKIE                         LPTIM_IER_ARROKIE_Msk                             /*!< Autoreload register update OK Interrupt Enable */
#define LPTIM_IER_UPIE_Pos                        (5U)
#define LPTIM_IER_UPIE_Msk                        (0x1UL<<LPTIM_IER_UPIE_Pos)                       /*!< 0x00000020 */
#define LPTIM_IER_UPIE                            LPTIM_IER_UPIE_Msk                                /*!< Direction change to UP Interrupt Enable */
#define LPTIM_IER_DOWNIE_Pos                      (6U)
#define LPTIM_IER_DOWNIE_Msk                      (0x1UL<<LPTIM_IER_DOWNIE_Pos)                     /*!< 0x00000040 */
#define LPTIM_IER_DOWNIE                          LPTIM_IER_DOWNIE_Msk                              /*!< Direction change to down Interrupt Enable */

/********************************* Bit definition for LPTIM_CFGR register *******************************************/
#define LPTIM_CFGR_CKSEL_Pos                      (0U)
#define LPTIM_CFGR_CKSEL_Msk                      (0x1UL<<LPTIM_CFGR_CKSEL_Pos)                     /*!< 0x00000001 */
#define LPTIM_CFGR_CKSEL                          LPTIM_CFGR_CKSEL_Msk                              /*!< Clock selector */
#define LPTIM_CFGR_CKPOL_Pos                      (1U)
#define LPTIM_CFGR_CKPOL_Msk                      (0x3UL<<LPTIM_CFGR_CKPOL_Pos)                     /*!< 0x00000006 */
#define LPTIM_CFGR_CKPOL                          LPTIM_CFGR_CKPOL_Msk                              /*!< Clock Polarity */
#define LPTIM_CFGR_CKPOL_0                        (0x1UL<<LPTIM_CFGR_CKPOL_Pos)                     /*!< 0x00000002 */
#define LPTIM_CFGR_CKPOL_1                        (0x2UL<<LPTIM_CFGR_CKPOL_Pos)                     /*!< 0x00000004 */
#define LPTIM_CFGR_CKFLT_Pos                      (3U)
#define LPTIM_CFGR_CKFLT_Msk                      (0x3UL<<LPTIM_CFGR_CKFLT_Pos)                     /*!< 0x00000018 */
#define LPTIM_CFGR_CKFLT                          LPTIM_CFGR_CKFLT_Msk                              /*!< Configurable digital filter for external clock */
#define LPTIM_CFGR_CKFLT_0                        (0x1UL<<LPTIM_CFGR_CKFLT_Pos)                     /*!< 0x00000008 */
#define LPTIM_CFGR_CKFLT_1                        (0x2UL<<LPTIM_CFGR_CKFLT_Pos)                     /*!< 0x00000010 */
#define LPTIM_CFGR_TRGFLT_Pos                     (6U)
#define LPTIM_CFGR_TRGFLT_Msk                     (0x3UL<<LPTIM_CFGR_TRGFLT_Pos)                    /*!< 0x000000C0 */
#define LPTIM_CFGR_TRGFLT                         LPTIM_CFGR_TRGFLT_Msk                             /*!< Configurable digital filter for trigger */
#define LPTIM_CFGR_TRGFLT_0                       (0x1UL<<LPTIM_CFGR_TRGFLT_Pos)                    /*!< 0x00000040 */
#define LPTIM_CFGR_TRGFLT_1                       (0x2UL<<LPTIM_CFGR_TRGFLT_Pos)                    /*!< 0x00000080 */
#define LPTIM_CFGR_PRESC_Pos                      (9U)
#define LPTIM_CFGR_PRESC_Msk                      (0x7UL<<LPTIM_CFGR_PRESC_Pos)                     /*!< 0x00000E00 */
#define LPTIM_CFGR_PRESC                          LPTIM_CFGR_PRESC_Msk                              /*!< Clock prescaler */
#define LPTIM_CFGR_PRESC_0                        (0x1UL<<LPTIM_CFGR_PRESC_Pos)                     /*!< 0x00000200 */
#define LPTIM_CFGR_PRESC_1                        (0x2UL<<LPTIM_CFGR_PRESC_Pos)                     /*!< 0x00000400 */
#define LPTIM_CFGR_PRESC_2                        (0x4UL<<LPTIM_CFGR_PRESC_Pos)                     /*!< 0x00000800 */
#define LPTIM_CFGR_TRIGSEL_Pos                    (13U)
#define LPTIM_CFGR_TRIGSEL_Msk                    (0x7UL<<LPTIM_CFGR_TRIGSEL_Pos)                   /*!< 0x0000E000 */
#define LPTIM_CFGR_TRIGSEL                        LPTIM_CFGR_TRIGSEL_Msk                            /*!< Trigger selector */
#define LPTIM_CFGR_TRIGSEL_0                      (0x1UL<<LPTIM_CFGR_TRIGSEL_Pos)                   /*!< 0x00002000 */
#define LPTIM_CFGR_TRIGSEL_1                      (0x2UL<<LPTIM_CFGR_TRIGSEL_Pos)                   /*!< 0x00004000 */
#define LPTIM_CFGR_TRIGSEL_2                      (0x4UL<<LPTIM_CFGR_TRIGSEL_Pos)                   /*!< 0x00008000 */
#define LPTIM_CFGR_TRIGEN_Pos                     (17U)
#define LPTIM_CFGR_TRIGEN_Msk                     (0x3UL<<LPTIM_CFGR_TRIGEN_Pos)                    /*!< 0x00060000 */
#define LPTIM_CFGR_TRIGEN                         LPTIM_CFGR_TRIGEN_Msk                             /*!< Trigger enable and polarity */
#define LPTIM_CFGR_TRIGEN_0                       (0x1UL<<LPTIM_CFGR_TRIGEN_Pos)                    /*!< 0x00020000 */
#define LPTIM_CFGR_TRIGEN_1                       (0x2UL<<LPTIM_CFGR_TRIGEN_Pos)                    /*!< 0x00040000 */
#define LPTIM_CFGR_TIMOUT_Pos                     (19U)
#define LPTIM_CFGR_TIMOUT_Msk                     (0x1UL<<LPTIM_CFGR_TIMOUT_Pos)                    /*!< 0x00080000 */
#define LPTIM_CFGR_TIMOUT                         LPTIM_CFGR_TIMOUT_Msk                             /*!<  Timeout enable */
#define LPTIM_CFGR_WAVE_Pos                       (20U)
#define LPTIM_CFGR_WAVE_Msk                       (0x1UL<<LPTIM_CFGR_WAVE_Pos)                      /*!< 0x00100000 */
#define LPTIM_CFGR_WAVE                           LPTIM_CFGR_WAVE_Msk                               /*!< Waveform shape */
#define LPTIM_CFGR_WAVPOL_Pos                     (21U)
#define LPTIM_CFGR_WAVPOL_Msk                     (0x1UL<<LPTIM_CFGR_WAVPOL_Pos)                    /*!< 0x00200000 */
#define LPTIM_CFGR_WAVPOL                         LPTIM_CFGR_WAVPOL_Msk                             /*!< Waveform shape polarity */
#define LPTIM_CFGR_PRELOAD_Pos                    (22U)
#define LPTIM_CFGR_PRELOAD_Msk                    (0x1UL<<LPTIM_CFGR_PRELOAD_Pos)                   /*!< 0x00400000 */
#define LPTIM_CFGR_PRELOAD                        LPTIM_CFGR_PRELOAD_Msk                            /*!< Registers update mode */
#define LPTIM_CFGR_COUNTMODE_Pos                  (23U)
#define LPTIM_CFGR_COUNTMODE_Msk                  (0x1UL<<LPTIM_CFGR_COUNTMODE_Pos)                 /*!< 0x00800000 */
#define LPTIM_CFGR_COUNTMODE                      LPTIM_CFGR_COUNTMODE_Msk                          /*!< counter mode enabled */
#define LPTIM_CFGR_ENC_Pos                        (24U)
#define LPTIM_CFGR_ENC_Msk                        (0x1UL<<LPTIM_CFGR_ENC_Pos)                       /*!< 0x01000000 */
#define LPTIM_CFGR_ENC                            LPTIM_CFGR_ENC_Msk                                /*!< Encoder mode enable */

/********************************* Bit definition for LPTIM_CR register *********************************************/
#define LPTIM_CR_ENABLE_Pos                       (0U)
#define LPTIM_CR_ENABLE_Msk                       (0x1UL<<LPTIM_CR_ENABLE_Pos)                      /*!< 0x00000001 */
#define LPTIM_CR_ENABLE                           LPTIM_CR_ENABLE_Msk                               /*!< LPTIM enable */
#define LPTIM_CR_SNGSTRT_Pos                      (1U)
#define LPTIM_CR_SNGSTRT_Msk                      (0x1UL<<LPTIM_CR_SNGSTRT_Pos)                     /*!< 0x00000002 */
#define LPTIM_CR_SNGSTRT                          LPTIM_CR_SNGSTRT_Msk                              /*!< LPTIM start in Single mode */
#define LPTIM_CR_CNTSTRT_Pos                      (2U)
#define LPTIM_CR_CNTSTRT_Msk                      (0x1UL<<LPTIM_CR_CNTSTRT_Pos)                     /*!< 0x00000004 */
#define LPTIM_CR_CNTSTRT                          LPTIM_CR_CNTSTRT_Msk                              /*!< Timer start in Continuous mode */
#define LPTIM_CR_COUNTRST_Pos                     (3U)
#define LPTIM_CR_COUNTRST_Msk                     (0x1UL<<LPTIM_CR_COUNTRST_Pos)                    /*!< 0x00000008 */
#define LPTIM_CR_COUNTRST                         LPTIM_CR_COUNTRST_Msk                             /*!< Counter reset */
#define LPTIM_CR_RSTARE_Pos                       (4U)
#define LPTIM_CR_RSTARE_Msk                       (0x1UL<<LPTIM_CR_RSTARE_Pos)                      /*!< 0x00000010 */
#define LPTIM_CR_RSTARE                           LPTIM_CR_RSTARE_Msk                               /*!< Reset after read enable */

/********************************* Bit definition for LPTIM_CMP register ********************************************/
#define LPTIM_CMP_CMP_Pos                         (0U)
#define LPTIM_CMP_CMP_Msk                         (0xFFFFUL<<LPTIM_CMP_CMP_Pos)                     /*!< 0x0000FFFF */
#define LPTIM_CMP_CMP                             LPTIM_CMP_CMP_Msk                                 /*!< Compare value */

/********************************* Bit definition for LPTIM_ARR register ********************************************/
#define LPTIM_ARR_ARR_Pos                         (0U)
#define LPTIM_ARR_ARR_Msk                         (0xFFFFUL<<LPTIM_ARR_ARR_Pos)                     /*!< 0x0000FFFF */
#define LPTIM_ARR_ARR                             LPTIM_ARR_ARR_Msk                                 /*!< Auto reload value */

/********************************* Bit definition for LPTIM_CNT register ********************************************/
#define LPTIM_CNT_CNT_Pos                         (0U)
#define LPTIM_CNT_CNT_Msk                         (0xFFFFUL<<LPTIM_CNT_CNT_Pos)                     /*!< 0x0000FFFF */
#define LPTIM_CNT_CNT                             LPTIM_CNT_CNT_Msk                                 /*!< Counter value */

/********************************* Bit definition for LPTIM_OR register *********************************************/
#define LPTIM_OR_IN1_Pos                          (0U)
#define LPTIM_OR_IN1_Msk                          (0xDUL<<LPTIM_OR_IN1_Pos)                         /*!< 0x0000000D */
#define LPTIM_OR_IN1                              LPTIM_OR_IN1_Msk                                  /*!< LPTimer input 1 remap extension */
#define LPTIM_OR_IN1_0                            (0x1UL<<LPTIM_OR_IN1_Pos)                         /*!< 0x00000001 */
#define LPTIM_OR_IN1_1                            (0x4UL<<LPTIM_OR_IN1_Pos)                         /*!< 0x00000004 */
#define LPTIM_OR_IN1_2                            (0x8UL<<LPTIM_OR_IN1_Pos)                         /*!< 0x00000008 */
#define LPTIM_OR_IN2_Pos                          (1U)
#define LPTIM_OR_IN2_Msk                          (0x19UL<<LPTIM_OR_IN2_Pos)                        /*!< 0x00000032 */
#define LPTIM_OR_IN2                              LPTIM_OR_IN2_Msk                                  /*!< LPTimer input 2 remap extension */
#define LPTIM_OR_IN2_0                            (0x1UL<<LPTIM_OR_IN2_Pos)                         /*!< 0x00000002 */
#define LPTIM_OR_IN2_1                            (0x8UL<<LPTIM_OR_IN2_Pos)                         /*!< 0x00000010 */
#define LPTIM_OR_IN2_2                            (0x10UL<<LPTIM_OR_IN2_Pos)                        /*!< 0x00000020 */

/********************************************************************************************************************/
/********************************* IWDG *****************************************************************************/
/********************************************************************************************************************/

/********************************* Bit definition for IWDG_KR register **********************************************/
#define IWDG_KR_KEY_Pos                           (0U)
#define IWDG_KR_KEY_Msk                           (0xFFFFUL<<IWDG_KR_KEY_Pos)                       /*!< 0x0000FFFF */
#define IWDG_KR_KEY                               IWDG_KR_KEY_Msk                                   /*!< IWDG KEY */

/********************************* Bit definition for IWDG_PR register **********************************************/
#define IWDG_PR_PR_Pos                            (0U)
#define IWDG_PR_PR_Msk                            (0x7UL<<IWDG_PR_PR_Pos)                           /*!< 0x00000007 */
#define IWDG_PR_PR                                IWDG_PR_PR_Msk                                    /*!< IWDG preload */
#define IWDG_PR_PR_0                              (0x1UL<<IWDG_PR_PR_Pos)                           /*!< 0x00000001 */
#define IWDG_PR_PR_1                              (0x2UL<<IWDG_PR_PR_Pos)                           /*!< 0x00000002 */
#define IWDG_PR_PR_2                              (0x4UL<<IWDG_PR_PR_Pos)                           /*!< 0x00000004 */

/********************************* Bit definition for IWDG_RLR register *********************************************/
#define IWDG_RLR_RL_Pos                           (0U)
#define IWDG_RLR_RL_Msk                           (0xFFFUL<<IWDG_RLR_RL_Pos)                        /*!< 0x00000FFF */
#define IWDG_RLR_RL                               IWDG_RLR_RL_Msk                                   /*!< IWDG reload */

/********************************* Bit definition for IWDG_SR register **********************************************/
#define IWDG_SR_PVU_Pos                           (0U)
#define IWDG_SR_PVU_Msk                           (0x1UL<<IWDG_SR_PVU_Pos)                          /*!< 0x00000001 */
#define IWDG_SR_PVU                               IWDG_SR_PVU_Msk                                   /*!< Watchdog prescaler value update */
#define IWDG_SR_RVU_Pos                           (1U)
#define IWDG_SR_RVU_Msk                           (0x1UL<<IWDG_SR_RVU_Pos)                          /*!< 0x00000002 */
#define IWDG_SR_RVU                               IWDG_SR_RVU_Msk                                   /*!< Watchdog counter reload value update */

/********************************************************************************************************************/
/********************************* WWDG *****************************************************************************/
/********************************************************************************************************************/

/********************************* Bit definition for WWDG_CR register **********************************************/
#define WWDG_CR_T_Pos                             (0U)
#define WWDG_CR_T_Msk                             (0x7FUL<<WWDG_CR_T_Pos)                           /*!< 0x0000007F */
#define WWDG_CR_T                                 WWDG_CR_T_Msk                                     /*!< wwdg counter bit6 */
#define WWDG_CR_WDGA_Pos                          (7U)
#define WWDG_CR_WDGA_Msk                          (0x1UL<<WWDG_CR_WDGA_Pos)                         /*!< 0x00000080 */
#define WWDG_CR_WDGA                              WWDG_CR_WDGA_Msk                                  /*!< WWDG Activation */

/********************************* Bit definition for WWDG_CFR register *********************************************/
#define WWDG_CFR_W_Pos                            (0U)
#define WWDG_CFR_W_Msk                            (0x7FUL<<WWDG_CFR_W_Pos)                          /*!< 0x0000007F */
#define WWDG_CFR_W                                WWDG_CFR_W_Msk                                    /*!< window value bit 6 */
#define WWDG_CFR_WDGTB_Pos                        (7U)
#define WWDG_CFR_WDGTB_Msk                        (0x3UL<<WWDG_CFR_WDGTB_Pos)                       /*!< 0x00000180 */
#define WWDG_CFR_WDGTB                            WWDG_CFR_WDGTB_Msk                                /*!< time base bit 1 */
#define WWDG_CFR_WDGTB_0                          (0x1UL<<WWDG_CFR_WDGTB_Pos)                       /*!< 0x00000080 */
#define WWDG_CFR_WDGTB_1                          (0x2UL<<WWDG_CFR_WDGTB_Pos)                       /*!< 0x00000100 */
#define WWDG_CFR_EWI_Pos                          (9U)
#define WWDG_CFR_EWI_Msk                          (0x1UL<<WWDG_CFR_EWI_Pos)                         /*!< 0x00000200 */
#define WWDG_CFR_EWI                              WWDG_CFR_EWI_Msk                                  /*!< Early wakeup interrupt */

/********************************* Bit definition for WWDG_SR register **********************************************/
#define WWDG_SR_EWIF_Pos                          (0U)
#define WWDG_SR_EWIF_Msk                          (0x1UL<<WWDG_SR_EWIF_Pos)                         /*!< 0x00000001 */
#define WWDG_SR_EWIF                              WWDG_SR_EWIF_Msk                                  /*!< Early wakeup interrupt flag */

/********************************************************************************************************************/
/********************************* RTC ******************************************************************************/
/********************************************************************************************************************/

/********************************* Bit definition for RTC_CRH register **********************************************/
#define RTC_CRH_SECIE_Pos                         (0U)
#define RTC_CRH_SECIE_Msk                         (0x1UL<<RTC_CRH_SECIE_Pos)                        /*!< 0x00000001 */
#define RTC_CRH_SECIE                             RTC_CRH_SECIE_Msk                                 /*!< Second interrupt enable */
#define RTC_CRH_ALRIE_Pos                         (1U)
#define RTC_CRH_ALRIE_Msk                         (0x1UL<<RTC_CRH_ALRIE_Pos)                        /*!< 0x00000002 */
#define RTC_CRH_ALRIE                             RTC_CRH_ALRIE_Msk                                 /*!< Alarm interrupt enable */
#define RTC_CRH_OWIE_Pos                          (2U)
#define RTC_CRH_OWIE_Msk                          (0x1UL<<RTC_CRH_OWIE_Pos)                         /*!< 0x00000004 */
#define RTC_CRH_OWIE                              RTC_CRH_OWIE_Msk                                  /*!< Overflow interrupt enable */

/********************************* Bit definition for RTC_CRL register **********************************************/
#define RTC_CRL_SECF_Pos                          (0U)
#define RTC_CRL_SECF_Msk                          (0x1UL<<RTC_CRL_SECF_Pos)                         /*!< 0x00000001 */
#define RTC_CRL_SECF                              RTC_CRL_SECF_Msk                                  /*!< Second flag */
#define RTC_CRL_ALRF_Pos                          (1U)
#define RTC_CRL_ALRF_Msk                          (0x1UL<<RTC_CRL_ALRF_Pos)                         /*!< 0x00000002 */
#define RTC_CRL_ALRF                              RTC_CRL_ALRF_Msk                                  /*!< Alarm flag */
#define RTC_CRL_OWF_Pos                           (2U)
#define RTC_CRL_OWF_Msk                           (0x1UL<<RTC_CRL_OWF_Pos)                          /*!< 0x00000004 */
#define RTC_CRL_OWF                               RTC_CRL_OWF_Msk                                   /*!< Overflow flag */
#define RTC_CRL_RSF_Pos                           (3U)
#define RTC_CRL_RSF_Msk                           (0x1UL<<RTC_CRL_RSF_Pos)                          /*!< 0x00000008 */
#define RTC_CRL_RSF                               RTC_CRL_RSF_Msk                                   /*!< Registers synchronized flag */
#define RTC_CRL_CNF_Pos                           (4U)
#define RTC_CRL_CNF_Msk                           (0x1UL<<RTC_CRL_CNF_Pos)                          /*!< 0x00000010 */
#define RTC_CRL_CNF                               RTC_CRL_CNF_Msk                                   /*!< Configuration flag */
#define RTC_CRL_RTOFF_Pos                         (5U)
#define RTC_CRL_RTOFF_Msk                         (0x1UL<<RTC_CRL_RTOFF_Pos)                        /*!< 0x00000020 */
#define RTC_CRL_RTOFF                             RTC_CRL_RTOFF_Msk                                 /*!< RTC operation OFF */

/********************************* Bit definition for RTC_PRLH register *********************************************/
#define RTC_PRLH_PRL_Pos                          (0U)
#define RTC_PRLH_PRL_Msk                          (0xFUL<<RTC_PRLH_PRL_Pos)                         /*!< 0x0000000F */
#define RTC_PRLH_PRL                              RTC_PRLH_PRL_Msk                                  /*!< RTC pre-scaler reload value high part */
#define RTC_PRLH_PRL_0                            (0x1UL<<RTC_PRLH_PRL_Pos)                         /*!< 0x00000001 */
#define RTC_PRLH_PRL_1                            (0x2UL<<RTC_PRLH_PRL_Pos)                         /*!< 0x00000002 */
#define RTC_PRLH_PRL_2                            (0x4UL<<RTC_PRLH_PRL_Pos)                         /*!< 0x00000004 */
#define RTC_PRLH_PRL_3                            (0x8UL<<RTC_PRLH_PRL_Pos)                         /*!< 0x00000008 */

/********************************* Bit definition for RTC_PRLL register *********************************************/
#define RTC_PRLL_PRL_Pos                          (0U)
#define RTC_PRLL_PRL_Msk                          (0xFFFFUL<<RTC_PRLL_PRL_Pos)                      /*!< 0x0000FFFF */
#define RTC_PRLL_PRL                              RTC_PRLL_PRL_Msk                                  /*!< RTC pre-scaler reload value low part */

/********************************* Bit definition for RTC_DIVH register *********************************************/
#define RTC_DIVH_DIV_Pos                          (0U)
#define RTC_DIVH_DIV_Msk                          (0xFUL<<RTC_DIVH_DIV_Pos)                         /*!< 0x0000000F */
#define RTC_DIVH_DIV                              RTC_DIVH_DIV_Msk                                  /*!< RTC clock divider high part */
#define RTC_DIVH_DIV_0                            (0x1UL<<RTC_DIVH_DIV_Pos)                         /*!< 0x00000001 */
#define RTC_DIVH_DIV_1                            (0x2UL<<RTC_DIVH_DIV_Pos)                         /*!< 0x00000002 */
#define RTC_DIVH_DIV_2                            (0x4UL<<RTC_DIVH_DIV_Pos)                         /*!< 0x00000004 */
#define RTC_DIVH_DIV_3                            (0x8UL<<RTC_DIVH_DIV_Pos)                         /*!< 0x00000008 */

/********************************* Bit definition for RTC_DIVL register *********************************************/
#define RTC_DIVL_DIV_Pos                          (0U)
#define RTC_DIVL_DIV_Msk                          (0xFFFFUL<<RTC_DIVL_DIV_Pos)                      /*!< 0x0000FFFF */
#define RTC_DIVL_DIV                              RTC_DIVL_DIV_Msk                                  /*!< RTC clock divider low part */

/********************************* Bit definition for RTC_CNTH register *********************************************/
#define RTC_CNTH_CNT_Pos                          (0U)
#define RTC_CNTH_CNT_Msk                          (0xFFFFUL<<RTC_CNTH_CNT_Pos)                      /*!< 0x0000FFFF */
#define RTC_CNTH_CNT                              RTC_CNTH_CNT_Msk                                  /*!< RTC counter high part */

/********************************* Bit definition for RTC_CNTL register *********************************************/
#define RTC_CNTL_CNT_Pos                          (0U)
#define RTC_CNTL_CNT_Msk                          (0xFFFFUL<<RTC_CNTL_CNT_Pos)                      /*!< 0x0000FFFF */
#define RTC_CNTL_CNT                              RTC_CNTL_CNT_Msk                                  /*!< RTC counter high part */

/********************************* Bit definition for RTC_ALRH register *********************************************/
#define RTC_ALRH_ALR_Pos                          (0U)
#define RTC_ALRH_ALR_Msk                          (0xFFFFUL<<RTC_ALRH_ALR_Pos)                      /*!< 0x0000FFFF */
#define RTC_ALRH_ALR                              RTC_ALRH_ALR_Msk                                  /*!< RTC alarm high part */

/********************************* Bit definition for RTC_ALRL register *********************************************/
#define RTC_ALRL_ALR_Pos                          (0U)
#define RTC_ALRL_ALR_Msk                          (0xFFFFUL<<RTC_ALRL_ALR_Pos)                      /*!< 0x0000FFFF */
#define RTC_ALRL_ALR                              RTC_ALRL_ALR_Msk                                  /*!< RTC alarm low part */

/********************************* Bit definition for RTC_TMPCFGR register ******************************************/
#define RTC_TMPCFGR_TPE_Pos                       (0U)
#define RTC_TMPCFGR_TPE_Msk                       (0x1UL<<RTC_TMPCFGR_TPE_Pos)                      /*!< 0x00000001 */
#define RTC_TMPCFGR_TPE                           RTC_TMPCFGR_TPE_Msk                               /*!< TAMP enable */
#define RTC_TMPCFGR_TPAL_Pos                      (1U)
#define RTC_TMPCFGR_TPAL_Msk                      (0x1UL<<RTC_TMPCFGR_TPAL_Pos)                     /*!< 0x00000002 */
#define RTC_TMPCFGR_TPAL                          RTC_TMPCFGR_TPAL_Msk                              /*!< TAMPER pin interrupt enable */

/********************************* Bit definition for RTC_TMPCSR register *******************************************/
#define RTC_TMPCSR_CTE_Pos                        (0U)
#define RTC_TMPCSR_CTE_Msk                        (0x1UL<<RTC_TMPCSR_CTE_Pos)                       /*!< 0x00000001 */
#define RTC_TMPCSR_CTE                            RTC_TMPCSR_CTE_Msk                                /*!< clear TAMP event */
#define RTC_TMPCSR_CTI_Pos                        (1U)
#define RTC_TMPCSR_CTI_Msk                        (0x1UL<<RTC_TMPCSR_CTI_Pos)                       /*!< 0x00000002 */
#define RTC_TMPCSR_CTI                            RTC_TMPCSR_CTI_Msk                                /*!< clear TAMP interrupt */
#define RTC_TMPCSR_TPIE_Pos                       (2U)
#define RTC_TMPCSR_TPIE_Msk                       (0x1UL<<RTC_TMPCSR_TPIE_Pos)                      /*!< 0x00000004 */
#define RTC_TMPCSR_TPIE                           RTC_TMPCSR_TPIE_Msk                               /*!< TAMP interrupt enable */
#define RTC_TMPCSR_TEF_Pos                        (8U)
#define RTC_TMPCSR_TEF_Msk                        (0x1UL<<RTC_TMPCSR_TEF_Pos)                       /*!< 0x00000100 */
#define RTC_TMPCSR_TEF                            RTC_TMPCSR_TEF_Msk                                /*!< TAMP event flag */
#define RTC_TMPCSR_TIF_Pos                        (9U)
#define RTC_TMPCSR_TIF_Msk                        (0x1UL<<RTC_TMPCSR_TIF_Pos)                       /*!< 0x00000200 */
#define RTC_TMPCSR_TIF                            RTC_TMPCSR_TIF_Msk                                /*!< TAMP interrupt flag */

/********************************* Bit definition for RTC_CALIBR register *******************************************/
#define RTC_CALIBR_CAL_Pos                        (0U)
#define RTC_CALIBR_CAL_Msk                        (0x7FUL<<RTC_CALIBR_CAL_Pos)                      /*!< 0x0000007F */
#define RTC_CALIBR_CAL                            RTC_CALIBR_CAL_Msk                                /*!< RTC calibration value */
#define RTC_CALIBR_CCO_Pos                        (7U)
#define RTC_CALIBR_CCO_Msk                        (0x1UL<<RTC_CALIBR_CCO_Pos)                       /*!< 0x00000080 */
#define RTC_CALIBR_CCO                            RTC_CALIBR_CCO_Msk                                /*!< Calibration clock output */
#define RTC_CALIBR_ASOE_Pos                       (8U)
#define RTC_CALIBR_ASOE_Msk                       (0x1UL<<RTC_CALIBR_ASOE_Pos)                      /*!< 0x00000100 */
#define RTC_CALIBR_ASOE                           RTC_CALIBR_ASOE_Msk                               /*!< Alarm or second output enable */
#define RTC_CALIBR_ASOS_Pos                       (9U)
#define RTC_CALIBR_ASOS_Msk                       (0x1UL<<RTC_CALIBR_ASOS_Pos)                      /*!< 0x00000200 */
#define RTC_CALIBR_ASOS                           RTC_CALIBR_ASOS_Msk                               /*!< Alarm or second output selection */

/********************************* Bit definition for RTC_BKPDR0 register *******************************************/
#define RTC_BKPDR0_D_Pos                          (0U)
#define RTC_BKPDR0_D_Msk                          (0xFFFFFFFFUL<<RTC_BKPDR0_D_Pos)                  /*!< 0xFFFFFFFF */
#define RTC_BKPDR0_D                              RTC_BKPDR0_D_Msk                                  /*!< bakeup data word0 */

/********************************* Bit definition for RTC_BKPDR1 register *******************************************/
#define RTC_BKPDR1_D_Pos                          (0U)
#define RTC_BKPDR1_D_Msk                          (0xFFFFFFFFUL<<RTC_BKPDR1_D_Pos)                  /*!< 0xFFFFFFFF */
#define RTC_BKPDR1_D                              RTC_BKPDR1_D_Msk                                  /*!< bakeup data word1 */

/********************************* Bit definition for RTC_BKPDR2 register *******************************************/
#define RTC_BKPDR2_D_Pos                          (0U)
#define RTC_BKPDR2_D_Msk                          (0xFFFFFFFFUL<<RTC_BKPDR2_D_Pos)                  /*!< 0xFFFFFFFF */
#define RTC_BKPDR2_D                              RTC_BKPDR2_D_Msk                                  /*!< bakeup data word2 */

/********************************* Bit definition for RTC_BKPDR3 register *******************************************/
#define RTC_BKPDR3_D_Pos                          (0U)
#define RTC_BKPDR3_D_Msk                          (0xFFFFFFFFUL<<RTC_BKPDR3_D_Pos)                  /*!< 0xFFFFFFFF */
#define RTC_BKPDR3_D                              RTC_BKPDR3_D_Msk                                  /*!< bakeup data word3 */

/********************************* Bit definition for RTC_BKPDR4 register *******************************************/
#define RTC_BKPDR4_D_Pos                          (0U)
#define RTC_BKPDR4_D_Msk                          (0xFFFFFFFFUL<<RTC_BKPDR4_D_Pos)                  /*!< 0xFFFFFFFF */
#define RTC_BKPDR4_D                              RTC_BKPDR4_D_Msk                                  /*!< bakeup data word4 */

/********************************************************************************************************************/
/********************************* SPI ******************************************************************************/
/********************************************************************************************************************/

#define SPI_I2S_SUPPORT       /*!< I2S support */

/********************************* Bit definition for SPI_CR1 register **********************************************/
#define SPI_CR1_CPHA_Pos                          (0U)
#define SPI_CR1_CPHA_Msk                          (0x1UL<<SPI_CR1_CPHA_Pos)                         /*!< 0x00000001 */
#define SPI_CR1_CPHA                              SPI_CR1_CPHA_Msk                                  /*!< Clock Phase */
#define SPI_CR1_CPOL_Pos                          (1U)
#define SPI_CR1_CPOL_Msk                          (0x1UL<<SPI_CR1_CPOL_Pos)                         /*!< 0x00000002 */
#define SPI_CR1_CPOL                              SPI_CR1_CPOL_Msk                                  /*!< Clock Polarity  */
#define SPI_CR1_MSTR_Pos                          (2U)
#define SPI_CR1_MSTR_Msk                          (0x1UL<<SPI_CR1_MSTR_Pos)                         /*!< 0x00000004 */
#define SPI_CR1_MSTR                              SPI_CR1_MSTR_Msk                                  /*!< Master Selection */
#define SPI_CR1_BR_Pos                            (3U)
#define SPI_CR1_BR_Msk                            (0x7UL<<SPI_CR1_BR_Pos)                           /*!< 0x00000038 */
#define SPI_CR1_BR                                SPI_CR1_BR_Msk                                    /*!< Baud Rate Control */
#define SPI_CR1_BR_0                              (0x1UL<<SPI_CR1_BR_Pos)                           /*!< 0x00000008 */
#define SPI_CR1_BR_1                              (0x2UL<<SPI_CR1_BR_Pos)                           /*!< 0x00000010 */
#define SPI_CR1_BR_2                              (0x4UL<<SPI_CR1_BR_Pos)                           /*!< 0x00000020 */
#define SPI_CR1_SPE_Pos                           (6U)
#define SPI_CR1_SPE_Msk                           (0x1UL<<SPI_CR1_SPE_Pos)                          /*!< 0x00000040 */
#define SPI_CR1_SPE                               SPI_CR1_SPE_Msk                                   /*!< SPI Enable */
#define SPI_CR1_LSBFIRST_Pos                      (7U)
#define SPI_CR1_LSBFIRST_Msk                      (0x1UL<<SPI_CR1_LSBFIRST_Pos)                     /*!< 0x00000080 */
#define SPI_CR1_LSBFIRST                          SPI_CR1_LSBFIRST_Msk                              /*!<  Frame Format */
#define SPI_CR1_SSI_Pos                           (8U)
#define SPI_CR1_SSI_Msk                           (0x1UL<<SPI_CR1_SSI_Pos)                          /*!< 0x00000100 */
#define SPI_CR1_SSI                               SPI_CR1_SSI_Msk                                   /*!< Internal slave select */
#define SPI_CR1_SSM_Pos                           (9U)
#define SPI_CR1_SSM_Msk                           (0x1UL<<SPI_CR1_SSM_Pos)                          /*!< 0x00000200 */
#define SPI_CR1_SSM                               SPI_CR1_SSM_Msk                                   /*!< Software slave management  */
#define SPI_CR1_RXONLY_Pos                        (10U)
#define SPI_CR1_RXONLY_Msk                        (0x1UL<<SPI_CR1_RXONLY_Pos)                       /*!< 0x00000400 */
#define SPI_CR1_RXONLY                            SPI_CR1_RXONLY_Msk                                /*!< Receive only */
#define SPI_CR1_DFF_Pos                           (11U)
#define SPI_CR1_DFF_Msk                           (0x1UL<<SPI_CR1_DFF_Pos)                          /*!< 0x00000800 */
#define SPI_CR1_DFF                               SPI_CR1_DFF_Msk                                   /*!< Data frame format */
#define SPI_CR1_CRCNEXT_Pos                       (12U)
#define SPI_CR1_CRCNEXT_Msk                       (0x1UL<<SPI_CR1_CRCNEXT_Pos)                      /*!< 0x00001000 */
#define SPI_CR1_CRCNEXT                           SPI_CR1_CRCNEXT_Msk                               /*!< Transmit CRC next */
#define SPI_CR1_CRCEN_Pos                         (13U)
#define SPI_CR1_CRCEN_Msk                         (0x1UL<<SPI_CR1_CRCEN_Pos)                        /*!< 0x00002000 */
#define SPI_CR1_CRCEN                             SPI_CR1_CRCEN_Msk                                 /*!< Hardware CRC calculation enable */
#define SPI_CR1_BIDIOE_Pos                        (14U)
#define SPI_CR1_BIDIOE_Msk                        (0x1UL<<SPI_CR1_BIDIOE_Pos)                       /*!< 0x00004000 */
#define SPI_CR1_BIDIOE                            SPI_CR1_BIDIOE_Msk                                /*!< Output enable in bidirectional mode */
#define SPI_CR1_BIDIMODE_Pos                      (15U)
#define SPI_CR1_BIDIMODE_Msk                      (0x1UL<<SPI_CR1_BIDIMODE_Pos)                     /*!< 0x00008000 */
#define SPI_CR1_BIDIMODE                          SPI_CR1_BIDIMODE_Msk                              /*!< Bidirectional data mode enable */

/********************************* Bit definition for SPI_CR2 register **********************************************/
#define SPI_CR2_RXDMAEN_Pos                       (0U)
#define SPI_CR2_RXDMAEN_Msk                       (0x1UL<<SPI_CR2_RXDMAEN_Pos)                      /*!< 0x00000001 */
#define SPI_CR2_RXDMAEN                           SPI_CR2_RXDMAEN_Msk                               /*!< Rx buffer DMA enable */
#define SPI_CR2_TXDMAEN_Pos                       (1U)
#define SPI_CR2_TXDMAEN_Msk                       (0x1UL<<SPI_CR2_TXDMAEN_Pos)                      /*!< 0x00000002 */
#define SPI_CR2_TXDMAEN                           SPI_CR2_TXDMAEN_Msk                               /*!< Tx buffer DMA enable */
#define SPI_CR2_SSOE_Pos                          (2U)
#define SPI_CR2_SSOE_Msk                          (0x1UL<<SPI_CR2_SSOE_Pos)                         /*!< 0x00000004 */
#define SPI_CR2_SSOE                              SPI_CR2_SSOE_Msk                                  /*!< SS Output Enable  */
#define SPI_CR2_CLRTXFIFO_Pos                     (4U)
#define SPI_CR2_CLRTXFIFO_Msk                     (0x1UL<<SPI_CR2_CLRTXFIFO_Pos)                    /*!< 0x00000010 */
#define SPI_CR2_CLRTXFIFO                         SPI_CR2_CLRTXFIFO_Msk                             /*!< Clear FIFO */
#define SPI_CR2_ERRIE_Pos                         (5U)
#define SPI_CR2_ERRIE_Msk                         (0x1UL<<SPI_CR2_ERRIE_Pos)                        /*!< 0x00000020 */
#define SPI_CR2_ERRIE                             SPI_CR2_ERRIE_Msk                                 /*!< Error Interrupt Enable */
#define SPI_CR2_RXNEIE_Pos                        (6U)
#define SPI_CR2_RXNEIE_Msk                        (0x1UL<<SPI_CR2_RXNEIE_Pos)                       /*!< 0x00000040 */
#define SPI_CR2_RXNEIE                            SPI_CR2_RXNEIE_Msk                                /*!< RX buffer Not Empty Interrupt Enable */
#define SPI_CR2_TXEIE_Pos                         (7U)
#define SPI_CR2_TXEIE_Msk                         (0x1UL<<SPI_CR2_TXEIE_Pos)                        /*!< 0x00000080 */
#define SPI_CR2_TXEIE                             SPI_CR2_TXEIE_Msk                                 /*!< Tx buffer Empty Interrupt Enable */
#define SPI_CR2_SAMPLE_SELECT_Pos                 (14U)
#define SPI_CR2_SAMPLE_SELECT_Msk                 (0x1UL<<SPI_CR2_SAMPLE_SELECT_Pos)                /*!< 0x00004000 */
#define SPI_CR2_SAMPLE_SELECT                     SPI_CR2_SAMPLE_SELECT_Msk
#define SPI_CR2_FRF_Pos                           (15U)
#define SPI_CR2_FRF_Msk                           (0x1UL<<SPI_CR2_FRF_Pos)                          /*!< 0x00008000 */
#define SPI_CR2_FRF                               SPI_CR2_FRF_Msk

/********************************* Bit definition for SPI_SR register ***********************************************/
#define SPI_SR_RXNE_Pos                           (0U)
#define SPI_SR_RXNE_Msk                           (0x1UL<<SPI_SR_RXNE_Pos)                          /*!< 0x00000001 */
#define SPI_SR_RXNE                               SPI_SR_RXNE_Msk                                   /*!< Receive buffer Not Empty  */
#define SPI_SR_TXE_Pos                            (1U)
#define SPI_SR_TXE_Msk                            (0x1UL<<SPI_SR_TXE_Pos)                           /*!< 0x00000002 */
#define SPI_SR_TXE                                SPI_SR_TXE_Msk                                    /*!< Transmit buffer Empty  */
#define SPI_SR_CHSIDE_Pos                         (2U)
#define SPI_SR_CHSIDE_Msk                         (0x1UL<<SPI_SR_CHSIDE_Pos)                        /*!< 0x00000004 */
#define SPI_SR_CHSIDE                             SPI_SR_CHSIDE_Msk                                 /*!< Channel side */
#define SPI_SR_UDR_Pos                            (3U)
#define SPI_SR_UDR_Msk                            (0x1UL<<SPI_SR_UDR_Pos)                           /*!< 0x00000008 */
#define SPI_SR_UDR                                SPI_SR_UDR_Msk                                    /*!< Underrun flag */
#define SPI_SR_CRCERR_Pos                         (4U)
#define SPI_SR_CRCERR_Msk                         (0x1UL<<SPI_SR_CRCERR_Pos)                        /*!< 0x00000010 */
#define SPI_SR_CRCERR                             SPI_SR_CRCERR_Msk                                 /*!< CRC error flag */
#define SPI_SR_MODF_Pos                           (5U)
#define SPI_SR_MODF_Msk                           (0x1UL<<SPI_SR_MODF_Pos)                          /*!< 0x00000020 */
#define SPI_SR_MODF                               SPI_SR_MODF_Msk                                   /*!< Mode fault */
#define SPI_SR_OVR_Pos                            (6U)
#define SPI_SR_OVR_Msk                            (0x1UL<<SPI_SR_OVR_Pos)                           /*!< 0x00000040 */
#define SPI_SR_OVR                                SPI_SR_OVR_Msk                                    /*!<  Overrun flag */
#define SPI_SR_BSY_Pos                            (7U)
#define SPI_SR_BSY_Msk                            (0x1UL<<SPI_SR_BSY_Pos)                           /*!< 0x00000080 */
#define SPI_SR_BSY                                SPI_SR_BSY_Msk                                    /*!< Busy flag  */
#define SPI_SR_FRE_Pos                            (8U)
#define SPI_SR_FRE_Msk                            (0x1UL<<SPI_SR_FRE_Pos)                           /*!< 0x00000100 */
#define SPI_SR_FRE                                SPI_SR_FRE_Msk                                    
#define SPI_SR_FRLVL_Pos                          (9U)
#define SPI_SR_FRLVL_Msk                          (0x3UL<<SPI_SR_FRLVL_Pos)                         /*!< 0x00000600 */
#define SPI_SR_FRLVL                              SPI_SR_FRLVL_Msk                                  /*!< FIFO Reception Level */
#define SPI_SR_FRLVL_0                            (0x1UL<<SPI_SR_FRLVL_Pos)                         /*!< 0x00000200 */
#define SPI_SR_FRLVL_1                            (0x2UL<<SPI_SR_FRLVL_Pos)                         /*!< 0x00000400 */
#define SPI_SR_FTLVL_Pos                          (11U)
#define SPI_SR_FTLVL_Msk                          (0x3UL<<SPI_SR_FTLVL_Pos)                         /*!< 0x00001800 */
#define SPI_SR_FTLVL                              SPI_SR_FTLVL_Msk                                  /*!< FIFO Transmission Level */
#define SPI_SR_FTLVL_0                            (0x1UL<<SPI_SR_FTLVL_Pos)                         /*!< 0x00000800 */
#define SPI_SR_FTLVL_1                            (0x2UL<<SPI_SR_FTLVL_Pos)                         /*!< 0x00001000 */

/********************************* Bit definition for SPI_DR register ***********************************************/
#define SPI_DR_DR_Pos                             (0U)
#define SPI_DR_DR_Msk                             (0xFFFFUL<<SPI_DR_DR_Pos)                         /*!< 0x0000FFFF */
#define SPI_DR_DR                                 SPI_DR_DR_Msk                                     /*!< Data Register */

/********************************* Bit definition for SPI_CRCPR register ********************************************/
#define SPI_CRCPR_CRCPOLY_Pos                     (0U)
#define SPI_CRCPR_CRCPOLY_Msk                     (0xFFFFUL<<SPI_CRCPR_CRCPOLY_Pos)                 /*!< 0x0000FFFF */
#define SPI_CRCPR_CRCPOLY                         SPI_CRCPR_CRCPOLY_Msk                             /*!< CRC polynomial register */

/********************************* Bit definition for SPI_RXCRCR register *******************************************/
#define SPI_RXCRCR_RXCRC_Pos                      (0U)
#define SPI_RXCRCR_RXCRC_Msk                      (0xFFFFUL<<SPI_RXCRCR_RXCRC_Pos)                  /*!< 0x0000FFFF */
#define SPI_RXCRCR_RXCRC                          SPI_RXCRCR_RXCRC_Msk                              /*!< rcv crc reg */

/********************************* Bit definition for SPI_TXCRCR register *******************************************/
#define SPI_TXCRCR_TXCRC_Pos                      (0U)
#define SPI_TXCRCR_TXCRC_Msk                      (0xFFFFUL<<SPI_TXCRCR_TXCRC_Pos)                  /*!< 0x0000FFFF */
#define SPI_TXCRCR_TXCRC                          SPI_TXCRCR_TXCRC_Msk                              /*!< tx crc reg  */

/********************************* Bit definition for SPI_I2S_CFGR register *****************************************/
#define SPI_I2S_CFGR_CHLEN_Pos                    (0U)
#define SPI_I2S_CFGR_CHLEN_Msk                    (0x1UL<<SPI_I2S_CFGR_CHLEN_Pos)                   /*!< 0x00000001 */
#define SPI_I2S_CFGR_CHLEN                        SPI_I2S_CFGR_CHLEN_Msk                            /*!< Channel length (number of bits per audio channel */
#define SPI_I2S_CFGR_DATLEN_Pos                   (1U)
#define SPI_I2S_CFGR_DATLEN_Msk                   (0x3UL<<SPI_I2S_CFGR_DATLEN_Pos)                  /*!< 0x00000006 */
#define SPI_I2S_CFGR_DATLEN                       SPI_I2S_CFGR_DATLEN_Msk                           /*!< Data length to be transferred */
#define SPI_I2S_CFGR_DATLEN_0                     (0x1UL<<SPI_I2S_CFGR_DATLEN_Pos)                  /*!< 0x00000002 */
#define SPI_I2S_CFGR_DATLEN_1                     (0x2UL<<SPI_I2S_CFGR_DATLEN_Pos)                  /*!< 0x00000004 */
#define SPI_I2S_CFGR_CKPOL_Pos                    (3U)
#define SPI_I2S_CFGR_CKPOL_Msk                    (0x1UL<<SPI_I2S_CFGR_CKPOL_Pos)                   /*!< 0x00000008 */
#define SPI_I2S_CFGR_CKPOL                        SPI_I2S_CFGR_CKPOL_Msk                            /*!< Steady state clock polarity */
#define SPI_I2S_CFGR_I2SSTD_Pos                   (4U)
#define SPI_I2S_CFGR_I2SSTD_Msk                   (0x3UL<<SPI_I2S_CFGR_I2SSTD_Pos)                  /*!< 0x00000030 */
#define SPI_I2S_CFGR_I2SSTD                       SPI_I2S_CFGR_I2SSTD_Msk                           /*!< I2S standard selection */
#define SPI_I2S_CFGR_I2SSTD_0                     (0x1UL<<SPI_I2S_CFGR_I2SSTD_Pos)                  /*!< 0x00000010 */
#define SPI_I2S_CFGR_I2SSTD_1                     (0x2UL<<SPI_I2S_CFGR_I2SSTD_Pos)                  /*!< 0x00000020 */
#define SPI_I2S_CFGR_PCMSYNC_Pos                  (7U)
#define SPI_I2S_CFGR_PCMSYNC_Msk                  (0x1UL<<SPI_I2S_CFGR_PCMSYNC_Pos)                 /*!< 0x00000080 */
#define SPI_I2S_CFGR_PCMSYNC                      SPI_I2S_CFGR_PCMSYNC_Msk                          /*!< PCM frame synchronization */
#define SPI_I2S_CFGR_I2SCFG_Pos                   (8U)
#define SPI_I2S_CFGR_I2SCFG_Msk                   (0x3UL<<SPI_I2S_CFGR_I2SCFG_Pos)                  /*!< 0x00000300 */
#define SPI_I2S_CFGR_I2SCFG                       SPI_I2S_CFGR_I2SCFG_Msk                           /*!< I2S configuration mode */
#define SPI_I2S_CFGR_I2SCFG_0                     (0x1UL<<SPI_I2S_CFGR_I2SCFG_Pos)                  /*!< 0x00000100 */
#define SPI_I2S_CFGR_I2SCFG_1                     (0x2UL<<SPI_I2S_CFGR_I2SCFG_Pos)                  /*!< 0x00000200 */
#define SPI_I2S_CFGR_I2SE_Pos                     (10U)
#define SPI_I2S_CFGR_I2SE_Msk                     (0x1UL<<SPI_I2S_CFGR_I2SE_Pos)                    /*!< 0x00000400 */
#define SPI_I2S_CFGR_I2SE                         SPI_I2S_CFGR_I2SE_Msk                             /*!<  I2S enable */
#define SPI_I2S_CFGR_I2SMOD_Pos                   (11U)
#define SPI_I2S_CFGR_I2SMOD_Msk                   (0x1UL<<SPI_I2S_CFGR_I2SMOD_Pos)                  /*!< 0x00000800 */
#define SPI_I2S_CFGR_I2SMOD                       SPI_I2S_CFGR_I2SMOD_Msk                           /*!< I2S mode selection */

/********************************* Bit definition for SPI_I2SPR register ********************************************/
#define SPI_I2SPR_I2SDIV_Pos                      (0U)
#define SPI_I2SPR_I2SDIV_Msk                      (0xFFUL<<SPI_I2SPR_I2SDIV_Pos)                    /*!< 0x000000FF */
#define SPI_I2SPR_I2SDIV                          SPI_I2SPR_I2SDIV_Msk                              /*!< I2S linear prescaler */
#define SPI_I2SPR_ODD_Pos                         (8U)
#define SPI_I2SPR_ODD_Msk                         (0x1UL<<SPI_I2SPR_ODD_Pos)                        /*!< 0x00000100 */
#define SPI_I2SPR_ODD                             SPI_I2SPR_ODD_Msk                                 /*!< Odd factor for the prescaler */
#define SPI_I2SPR_MCKOE_Pos                       (9U)
#define SPI_I2SPR_MCKOE_Msk                       (0x1UL<<SPI_I2SPR_MCKOE_Pos)                      /*!< 0x00000200 */
#define SPI_I2SPR_MCKOE                           SPI_I2SPR_MCKOE_Msk                               /*!<  Master clock output enable */

/********************************************************************************************************************/
/********************************* FDCAN ****************************************************************************/
/********************************************************************************************************************/

/********************************* Bit definition for FDCAN_CREL register *******************************************/
#define FDCAN_CREL_DAY_Pos                        (0U)
#define FDCAN_CREL_DAY_Msk                        (0xFFUL<<FDCAN_CREL_DAY_Pos)                      /*!< 0x000000FF */
#define FDCAN_CREL_DAY                            FDCAN_CREL_DAY_Msk                                /*!< - */
#define FDCAN_CREL_MON_Pos                        (8U)
#define FDCAN_CREL_MON_Msk                        (0xFFUL<<FDCAN_CREL_MON_Pos)                      /*!< 0x0000FF00 */
#define FDCAN_CREL_MON                            FDCAN_CREL_MON_Msk                                /*!< - */
#define FDCAN_CREL_YEAR_Pos                       (16U)
#define FDCAN_CREL_YEAR_Msk                       (0xFUL<<FDCAN_CREL_YEAR_Pos)                      /*!< 0x000F0000 */
#define FDCAN_CREL_YEAR                           FDCAN_CREL_YEAR_Msk                               /*!< - */
#define FDCAN_CREL_YEAR_0                         (0x1UL<<FDCAN_CREL_YEAR_Pos)                      /*!< 0x00010000 */
#define FDCAN_CREL_YEAR_1                         (0x2UL<<FDCAN_CREL_YEAR_Pos)                      /*!< 0x00020000 */
#define FDCAN_CREL_YEAR_2                         (0x4UL<<FDCAN_CREL_YEAR_Pos)                      /*!< 0x00040000 */
#define FDCAN_CREL_YEAR_3                         (0x8UL<<FDCAN_CREL_YEAR_Pos)                      /*!< 0x00080000 */
#define FDCAN_CREL_SUBSTEP_Pos                    (20U)
#define FDCAN_CREL_SUBSTEP_Msk                    (0xFUL<<FDCAN_CREL_SUBSTEP_Pos)                   /*!< 0x00F00000 */
#define FDCAN_CREL_SUBSTEP                        FDCAN_CREL_SUBSTEP_Msk                            /*!< - */
#define FDCAN_CREL_SUBSTEP_0                      (0x1UL<<FDCAN_CREL_SUBSTEP_Pos)                   /*!< 0x00100000 */
#define FDCAN_CREL_SUBSTEP_1                      (0x2UL<<FDCAN_CREL_SUBSTEP_Pos)                   /*!< 0x00200000 */
#define FDCAN_CREL_SUBSTEP_2                      (0x4UL<<FDCAN_CREL_SUBSTEP_Pos)                   /*!< 0x00400000 */
#define FDCAN_CREL_SUBSTEP_3                      (0x8UL<<FDCAN_CREL_SUBSTEP_Pos)                   /*!< 0x00800000 */
#define FDCAN_CREL_STEP_Pos                       (24U)
#define FDCAN_CREL_STEP_Msk                       (0xFUL<<FDCAN_CREL_STEP_Pos)                      /*!< 0x0F000000 */
#define FDCAN_CREL_STEP                           FDCAN_CREL_STEP_Msk                               /*!< - */
#define FDCAN_CREL_STEP_0                         (0x1UL<<FDCAN_CREL_STEP_Pos)                      /*!< 0x01000000 */
#define FDCAN_CREL_STEP_1                         (0x2UL<<FDCAN_CREL_STEP_Pos)                      /*!< 0x02000000 */
#define FDCAN_CREL_STEP_2                         (0x4UL<<FDCAN_CREL_STEP_Pos)                      /*!< 0x04000000 */
#define FDCAN_CREL_STEP_3                         (0x8UL<<FDCAN_CREL_STEP_Pos)                      /*!< 0x08000000 */
#define FDCAN_CREL_REL_Pos                        (28U)
#define FDCAN_CREL_REL_Msk                        (0xFUL<<FDCAN_CREL_REL_Pos)                       /*!< 0xF0000000 */
#define FDCAN_CREL_REL                            FDCAN_CREL_REL_Msk                                /*!< - */
#define FDCAN_CREL_REL_0                          (0x1UL<<FDCAN_CREL_REL_Pos)                       /*!< 0x10000000 */
#define FDCAN_CREL_REL_1                          (0x2UL<<FDCAN_CREL_REL_Pos)                       /*!< 0x20000000 */
#define FDCAN_CREL_REL_2                          (0x4UL<<FDCAN_CREL_REL_Pos)                       /*!< 0x40000000 */
#define FDCAN_CREL_REL_3                          (0x8UL<<FDCAN_CREL_REL_Pos)                       /*!< 0x80000000 */

/********************************* Bit definition for FDCAN_ENDN register *******************************************/
#define FDCAN_ENDN_ETV_Pos                        (0U)
#define FDCAN_ENDN_ETV_Msk                        (0xFFFFFFFFUL<<FDCAN_ENDN_ETV_Pos)                /*!< 0xFFFFFFFF */
#define FDCAN_ENDN_ETV                            FDCAN_ENDN_ETV_Msk                                /*!< Endian Register */

/********************************* Bit definition for FDCAN_DBTP register *******************************************/
#define FDCAN_DBTP_DSJW_Pos                       (0U)
#define FDCAN_DBTP_DSJW_Msk                       (0xFUL<<FDCAN_DBTP_DSJW_Pos)                      /*!< 0x0000000F */
#define FDCAN_DBTP_DSJW                           FDCAN_DBTP_DSJW_Msk                               /*!< Data (Re)Synchronization Jump Width */
#define FDCAN_DBTP_DSJW_0                         (0x1UL<<FDCAN_DBTP_DSJW_Pos)                      /*!< 0x00000001 */
#define FDCAN_DBTP_DSJW_1                         (0x2UL<<FDCAN_DBTP_DSJW_Pos)                      /*!< 0x00000002 */
#define FDCAN_DBTP_DSJW_2                         (0x4UL<<FDCAN_DBTP_DSJW_Pos)                      /*!< 0x00000004 */
#define FDCAN_DBTP_DSJW_3                         (0x8UL<<FDCAN_DBTP_DSJW_Pos)                      /*!< 0x00000008 */
#define FDCAN_DBTP_DTSEG2_Pos                     (4U)
#define FDCAN_DBTP_DTSEG2_Msk                     (0xFUL<<FDCAN_DBTP_DTSEG2_Pos)                    /*!< 0x000000F0 */
#define FDCAN_DBTP_DTSEG2                         FDCAN_DBTP_DTSEG2_Msk                             /*!< Data time segment after sample point */
#define FDCAN_DBTP_DTSEG2_0                       (0x1UL<<FDCAN_DBTP_DTSEG2_Pos)                    /*!< 0x00000010 */
#define FDCAN_DBTP_DTSEG2_1                       (0x2UL<<FDCAN_DBTP_DTSEG2_Pos)                    /*!< 0x00000020 */
#define FDCAN_DBTP_DTSEG2_2                       (0x4UL<<FDCAN_DBTP_DTSEG2_Pos)                    /*!< 0x00000040 */
#define FDCAN_DBTP_DTSEG2_3                       (0x8UL<<FDCAN_DBTP_DTSEG2_Pos)                    /*!< 0x00000080 */
#define FDCAN_DBTP_DTSEG1_Pos                     (8U)
#define FDCAN_DBTP_DTSEG1_Msk                     (0x1FUL<<FDCAN_DBTP_DTSEG1_Pos)                   /*!< 0x00001F00 */
#define FDCAN_DBTP_DTSEG1                         FDCAN_DBTP_DTSEG1_Msk                             /*!< Data time segment before sample point */
#define FDCAN_DBTP_DTSEG1_0                       (0x1UL<<FDCAN_DBTP_DTSEG1_Pos)                    /*!< 0x00000100 */
#define FDCAN_DBTP_DTSEG1_1                       (0x2UL<<FDCAN_DBTP_DTSEG1_Pos)                    /*!< 0x00000200 */
#define FDCAN_DBTP_DTSEG1_2                       (0x4UL<<FDCAN_DBTP_DTSEG1_Pos)                    /*!< 0x00000400 */
#define FDCAN_DBTP_DTSEG1_3                       (0x8UL<<FDCAN_DBTP_DTSEG1_Pos)                    /*!< 0x00000800 */
#define FDCAN_DBTP_DTSEG1_4                       (0x10UL<<FDCAN_DBTP_DTSEG1_Pos)                   /*!< 0x00001000 */
#define FDCAN_DBTP_DBRP_Pos                       (16U)
#define FDCAN_DBTP_DBRP_Msk                       (0x1FUL<<FDCAN_DBTP_DBRP_Pos)                     /*!< 0x001F0000 */
#define FDCAN_DBTP_DBRP                           FDCAN_DBTP_DBRP_Msk                               /*!< Data Bit Rate Prescaler */
#define FDCAN_DBTP_DBRP_0                         (0x1UL<<FDCAN_DBTP_DBRP_Pos)                      /*!< 0x00010000 */
#define FDCAN_DBTP_DBRP_1                         (0x2UL<<FDCAN_DBTP_DBRP_Pos)                      /*!< 0x00020000 */
#define FDCAN_DBTP_DBRP_2                         (0x4UL<<FDCAN_DBTP_DBRP_Pos)                      /*!< 0x00040000 */
#define FDCAN_DBTP_DBRP_3                         (0x8UL<<FDCAN_DBTP_DBRP_Pos)                      /*!< 0x00080000 */
#define FDCAN_DBTP_DBRP_4                         (0x10UL<<FDCAN_DBTP_DBRP_Pos)                     /*!< 0x00100000 */
#define FDCAN_DBTP_TDC_Pos                        (23U)
#define FDCAN_DBTP_TDC_Msk                        (0x1UL<<FDCAN_DBTP_TDC_Pos)                       /*!< 0x00800000 */
#define FDCAN_DBTP_TDC                            FDCAN_DBTP_TDC_Msk                                /*!< Transmitter Delay Compensation */

/********************************* Bit definition for FDCAN_TEST register *******************************************/
#define FDCAN_TEST_LBCK_Pos                       (4U)
#define FDCAN_TEST_LBCK_Msk                       (0x1UL<<FDCAN_TEST_LBCK_Pos)                      /*!< 0x00000010 */
#define FDCAN_TEST_LBCK                           FDCAN_TEST_LBCK_Msk                               /*!< Loop Back Mode */
#define FDCAN_TEST_TX_Pos                         (5U)
#define FDCAN_TEST_TX_Msk                         (0x3UL<<FDCAN_TEST_TX_Pos)                        /*!< 0x00000060 */
#define FDCAN_TEST_TX                             FDCAN_TEST_TX_Msk                                 /*!< Control of Transmit Pin */
#define FDCAN_TEST_TX_0                           (0x1UL<<FDCAN_TEST_TX_Pos)                        /*!< 0x00000020 */
#define FDCAN_TEST_TX_1                           (0x2UL<<FDCAN_TEST_TX_Pos)                        /*!< 0x00000040 */
#define FDCAN_TEST_RX_Pos                         (7U)
#define FDCAN_TEST_RX_Msk                         (0x1UL<<FDCAN_TEST_RX_Pos)                        /*!< 0x00000080 */
#define FDCAN_TEST_RX                             FDCAN_TEST_RX_Msk                                 /*!< Receive Pin */
#define FDCAN_TEST_TXBNP_Pos                      (8U)
#define FDCAN_TEST_TXBNP_Msk                      (0x1FUL<<FDCAN_TEST_TXBNP_Pos)                    /*!< 0x00001F00 */
#define FDCAN_TEST_TXBNP                          FDCAN_TEST_TXBNP_Msk                              /*!< Tx Buffer Number Prepared */
#define FDCAN_TEST_TXBNP_0                        (0x1UL<<FDCAN_TEST_TXBNP_Pos)                     /*!< 0x00000100 */
#define FDCAN_TEST_TXBNP_1                        (0x2UL<<FDCAN_TEST_TXBNP_Pos)                     /*!< 0x00000200 */
#define FDCAN_TEST_TXBNP_2                        (0x4UL<<FDCAN_TEST_TXBNP_Pos)                     /*!< 0x00000400 */
#define FDCAN_TEST_TXBNP_3                        (0x8UL<<FDCAN_TEST_TXBNP_Pos)                     /*!< 0x00000800 */
#define FDCAN_TEST_TXBNP_4                        (0x10UL<<FDCAN_TEST_TXBNP_Pos)                    /*!< 0x00001000 */
#define FDCAN_TEST_PVAL_Pos                       (13U)
#define FDCAN_TEST_PVAL_Msk                       (0x1UL<<FDCAN_TEST_PVAL_Pos)                      /*!< 0x00002000 */
#define FDCAN_TEST_PVAL                           FDCAN_TEST_PVAL_Msk                               /*!< Prepared Valid */
#define FDCAN_TEST_TXBNS_Pos                      (16U)
#define FDCAN_TEST_TXBNS_Msk                      (0x1FUL<<FDCAN_TEST_TXBNS_Pos)                    /*!< 0x001F0000 */
#define FDCAN_TEST_TXBNS                          FDCAN_TEST_TXBNS_Msk                              /*!< Tx Buffer Number Started */
#define FDCAN_TEST_TXBNS_0                        (0x1UL<<FDCAN_TEST_TXBNS_Pos)                     /*!< 0x00010000 */
#define FDCAN_TEST_TXBNS_1                        (0x2UL<<FDCAN_TEST_TXBNS_Pos)                     /*!< 0x00020000 */
#define FDCAN_TEST_TXBNS_2                        (0x4UL<<FDCAN_TEST_TXBNS_Pos)                     /*!< 0x00040000 */
#define FDCAN_TEST_TXBNS_3                        (0x8UL<<FDCAN_TEST_TXBNS_Pos)                     /*!< 0x00080000 */
#define FDCAN_TEST_TXBNS_4                        (0x10UL<<FDCAN_TEST_TXBNS_Pos)                    /*!< 0x00100000 */
#define FDCAN_TEST_SVAL_Pos                       (21U)
#define FDCAN_TEST_SVAL_Msk                       (0x1UL<<FDCAN_TEST_SVAL_Pos)                      /*!< 0x00200000 */
#define FDCAN_TEST_SVAL                           FDCAN_TEST_SVAL_Msk                               /*!< Started Valid */

/********************************* Bit definition for FDCAN_RWD register ********************************************/
#define FDCAN_RWD_WDC_Pos                         (0U)
#define FDCAN_RWD_WDC_Msk                         (0xFFUL<<FDCAN_RWD_WDC_Pos)                       /*!< 0x000000FF */
#define FDCAN_RWD_WDC                             FDCAN_RWD_WDC_Msk                                 /*!< Watchdog Configuration */
#define FDCAN_RWD_WDV_Pos                         (8U)
#define FDCAN_RWD_WDV_Msk                         (0xFFUL<<FDCAN_RWD_WDV_Pos)                       /*!< 0x0000FF00 */
#define FDCAN_RWD_WDV                             FDCAN_RWD_WDV_Msk                                 /*!< Watchdog Value */

/********************************* Bit definition for FDCAN_CCCR register *******************************************/
#define FDCAN_CCCR_INIT_Pos                       (0U)
#define FDCAN_CCCR_INIT_Msk                       (0x1UL<<FDCAN_CCCR_INIT_Pos)                      /*!< 0x00000001 */
#define FDCAN_CCCR_INIT                           FDCAN_CCCR_INIT_Msk                               /*!< Initialization */
#define FDCAN_CCCR_CCE_Pos                        (1U)
#define FDCAN_CCCR_CCE_Msk                        (0x1UL<<FDCAN_CCCR_CCE_Pos)                       /*!< 0x00000002 */
#define FDCAN_CCCR_CCE                            FDCAN_CCCR_CCE_Msk                                /*!< Configuration Change Enable */
#define FDCAN_CCCR_ASM_Pos                        (2U)
#define FDCAN_CCCR_ASM_Msk                        (0x1UL<<FDCAN_CCCR_ASM_Pos)                       /*!< 0x00000004 */
#define FDCAN_CCCR_ASM                            FDCAN_CCCR_ASM_Msk                                /*!< Restricted Operation Mode */
#define FDCAN_CCCR_CSA_Pos                        (3U)
#define FDCAN_CCCR_CSA_Msk                        (0x1UL<<FDCAN_CCCR_CSA_Pos)                       /*!< 0x00000008 */
#define FDCAN_CCCR_CSA                            FDCAN_CCCR_CSA_Msk                                /*!< Clock Stop Acknowledge */
#define FDCAN_CCCR_CSR_Pos                        (4U)
#define FDCAN_CCCR_CSR_Msk                        (0x1UL<<FDCAN_CCCR_CSR_Pos)                       /*!< 0x00000010 */
#define FDCAN_CCCR_CSR                            FDCAN_CCCR_CSR_Msk                                /*!< Clock Stop Request */
#define FDCAN_CCCR_MON_Pos                        (5U)
#define FDCAN_CCCR_MON_Msk                        (0x1UL<<FDCAN_CCCR_MON_Pos)                       /*!< 0x00000020 */
#define FDCAN_CCCR_MON                            FDCAN_CCCR_MON_Msk                                /*!< Bus Monitoring Mode */
#define FDCAN_CCCR_DAR_Pos                        (6U)
#define FDCAN_CCCR_DAR_Msk                        (0x1UL<<FDCAN_CCCR_DAR_Pos)                       /*!< 0x00000040 */
#define FDCAN_CCCR_DAR                            FDCAN_CCCR_DAR_Msk                                /*!< Disable Automatic Retransmission */
#define FDCAN_CCCR_TEST_Pos                       (7U)
#define FDCAN_CCCR_TEST_Msk                       (0x1UL<<FDCAN_CCCR_TEST_Pos)                      /*!< 0x00000080 */
#define FDCAN_CCCR_TEST                           FDCAN_CCCR_TEST_Msk                               /*!< Test Mode Enable */
#define FDCAN_CCCR_FDOE_Pos                       (8U)
#define FDCAN_CCCR_FDOE_Msk                       (0x1UL<<FDCAN_CCCR_FDOE_Pos)                      /*!< 0x00000100 */
#define FDCAN_CCCR_FDOE                           FDCAN_CCCR_FDOE_Msk                               /*!< FD Operation Enable */
#define FDCAN_CCCR_BRSE_Pos                       (9U)
#define FDCAN_CCCR_BRSE_Msk                       (0x1UL<<FDCAN_CCCR_BRSE_Pos)                      /*!< 0x00000200 */
#define FDCAN_CCCR_BRSE                           FDCAN_CCCR_BRSE_Msk                               /*!< Bit Rate Switch Enable */
#define FDCAN_CCCR_WMM_Pos                        (11U)
#define FDCAN_CCCR_WMM_Msk                        (0x1UL<<FDCAN_CCCR_WMM_Pos)                       /*!< 0x00000800 */
#define FDCAN_CCCR_WMM                            FDCAN_CCCR_WMM_Msk                                /*!< Wide Message Marker */
#define FDCAN_CCCR_PXHD_Pos                       (12U)
#define FDCAN_CCCR_PXHD_Msk                       (0x1UL<<FDCAN_CCCR_PXHD_Pos)                      /*!< 0x00001000 */
#define FDCAN_CCCR_PXHD                           FDCAN_CCCR_PXHD_Msk                               /*!< Protocol Exception Handling Disable */
#define FDCAN_CCCR_EFBI_Pos                       (13U)
#define FDCAN_CCCR_EFBI_Msk                       (0x1UL<<FDCAN_CCCR_EFBI_Pos)                      /*!< 0x00002000 */
#define FDCAN_CCCR_EFBI                           FDCAN_CCCR_EFBI_Msk                               /*!< Edge Filtering during Bus Integration */
#define FDCAN_CCCR_TXP_Pos                        (14U)
#define FDCAN_CCCR_TXP_Msk                        (0x1UL<<FDCAN_CCCR_TXP_Pos)                       /*!< 0x00004000 */
#define FDCAN_CCCR_TXP                            FDCAN_CCCR_TXP_Msk                                /*!< Transmit Pause */
#define FDCAN_CCCR_NISO_Pos                       (15U)
#define FDCAN_CCCR_NISO_Msk                       (0x1UL<<FDCAN_CCCR_NISO_Pos)                      /*!< 0x00008000 */
#define FDCAN_CCCR_NISO                           FDCAN_CCCR_NISO_Msk                               /*!< Non ISO Operation */

/********************************* Bit definition for FDCAN_NBTP register *******************************************/
#define FDCAN_NBTP_NTSEG2_Pos                     (0U)
#define FDCAN_NBTP_NTSEG2_Msk                     (0x7FUL<<FDCAN_NBTP_NTSEG2_Pos)                   /*!< 0x0000007F */
#define FDCAN_NBTP_NTSEG2                         FDCAN_NBTP_NTSEG2_Msk                             /*!< Nominal Time segment after sample point */
#define FDCAN_NBTP_NTSEG1_Pos                     (8U)
#define FDCAN_NBTP_NTSEG1_Msk                     (0xFFUL<<FDCAN_NBTP_NTSEG1_Pos)                   /*!< 0x0000FF00 */
#define FDCAN_NBTP_NTSEG1                         FDCAN_NBTP_NTSEG1_Msk                             /*!< Nominal Time segment before sample point */
#define FDCAN_NBTP_NBRP_Pos                       (16U)
#define FDCAN_NBTP_NBRP_Msk                       (0x1FFUL<<FDCAN_NBTP_NBRP_Pos)                    /*!< 0x01FF0000 */
#define FDCAN_NBTP_NBRP                           FDCAN_NBTP_NBRP_Msk                               /*!< Nominal Bit Rate Prescaler */
#define FDCAN_NBTP_NSJW_Pos                       (25U)
#define FDCAN_NBTP_NSJW_Msk                       (0x7FUL<<FDCAN_NBTP_NSJW_Pos)                     /*!< 0xFE000000 */
#define FDCAN_NBTP_NSJW                           FDCAN_NBTP_NSJW_Msk                               /*!< Nominal (Re)Synchronization Jump Width */

/********************************* Bit definition for FDCAN_TSCC register *******************************************/
#define FDCAN_TSCC_TSS_Pos                        (0U)
#define FDCAN_TSCC_TSS_Msk                        (0x3UL<<FDCAN_TSCC_TSS_Pos)                       /*!< 0x00000003 */
#define FDCAN_TSCC_TSS                            FDCAN_TSCC_TSS_Msk                                /*!< Timestamp Select */
#define FDCAN_TSCC_TSS_0                          (0x1UL<<FDCAN_TSCC_TSS_Pos)                       /*!< 0x00000001 */
#define FDCAN_TSCC_TSS_1                          (0x2UL<<FDCAN_TSCC_TSS_Pos)                       /*!< 0x00000002 */
#define FDCAN_TSCC_TCP_Pos                        (16U)
#define FDCAN_TSCC_TCP_Msk                        (0xFUL<<FDCAN_TSCC_TCP_Pos)                       /*!< 0x000F0000 */
#define FDCAN_TSCC_TCP                            FDCAN_TSCC_TCP_Msk                                /*!< Timestamp Counter Prescaler */
#define FDCAN_TSCC_TCP_0                          (0x1UL<<FDCAN_TSCC_TCP_Pos)                       /*!< 0x00010000 */
#define FDCAN_TSCC_TCP_1                          (0x2UL<<FDCAN_TSCC_TCP_Pos)                       /*!< 0x00020000 */
#define FDCAN_TSCC_TCP_2                          (0x4UL<<FDCAN_TSCC_TCP_Pos)                       /*!< 0x00040000 */
#define FDCAN_TSCC_TCP_3                          (0x8UL<<FDCAN_TSCC_TCP_Pos)                       /*!< 0x00080000 */

/********************************* Bit definition for FDCAN_TSCV register *******************************************/
#define FDCAN_TSCV_TSC_Pos                        (0U)
#define FDCAN_TSCV_TSC_Msk                        (0xFFFFUL<<FDCAN_TSCV_TSC_Pos)                    /*!< 0x0000FFFF */
#define FDCAN_TSCV_TSC                            FDCAN_TSCV_TSC_Msk                                /*!< Timestamp Counter */

/********************************* Bit definition for FDCAN_TOCC register *******************************************/
#define FDCAN_TOCC_ETOC_Pos                       (0U)
#define FDCAN_TOCC_ETOC_Msk                       (0x1UL<<FDCAN_TOCC_ETOC_Pos)                      /*!< 0x00000001 */
#define FDCAN_TOCC_ETOC                           FDCAN_TOCC_ETOC_Msk                               /*!< Enable Timeout Counter */
#define FDCAN_TOCC_TOS_Pos                        (1U)
#define FDCAN_TOCC_TOS_Msk                        (0x3UL<<FDCAN_TOCC_TOS_Pos)                       /*!< 0x00000006 */
#define FDCAN_TOCC_TOS                            FDCAN_TOCC_TOS_Msk                                /*!< Timeout Select */
#define FDCAN_TOCC_TOS_0                          (0x1UL<<FDCAN_TOCC_TOS_Pos)                       /*!< 0x00000002 */
#define FDCAN_TOCC_TOS_1                          (0x2UL<<FDCAN_TOCC_TOS_Pos)                       /*!< 0x00000004 */
#define FDCAN_TOCC_TOP_Pos                        (16U)
#define FDCAN_TOCC_TOP_Msk                        (0xFFFFUL<<FDCAN_TOCC_TOP_Pos)                    /*!< 0xFFFF0000 */
#define FDCAN_TOCC_TOP                            FDCAN_TOCC_TOP_Msk                                /*!< Timeout Period */

/********************************* Bit definition for FDCAN_TOCV register *******************************************/
#define FDCAN_TOCV_TOC_Pos                        (0U)
#define FDCAN_TOCV_TOC_Msk                        (0xFFFFUL<<FDCAN_TOCV_TOC_Pos)                    /*!< 0x0000FFFF */
#define FDCAN_TOCV_TOC                            FDCAN_TOCV_TOC_Msk                                /*!< Timeout Counter */

/********************************* Bit definition for FDCAN_ECR register ********************************************/
#define FDCAN_ECR_TEC_Pos                         (0U)
#define FDCAN_ECR_TEC_Msk                         (0xFFUL<<FDCAN_ECR_TEC_Pos)                       /*!< 0x000000FF */
#define FDCAN_ECR_TEC                             FDCAN_ECR_TEC_Msk                                 /*!< Transmit Error Counter */
#define FDCAN_ECR_REC_Pos                         (8U)
#define FDCAN_ECR_REC_Msk                         (0x7FUL<<FDCAN_ECR_REC_Pos)                       /*!< 0x00007F00 */
#define FDCAN_ECR_REC                             FDCAN_ECR_REC_Msk                                 /*!< Receive Error Counter */
#define FDCAN_ECR_RP_Pos                          (15U)
#define FDCAN_ECR_RP_Msk                          (0x1UL<<FDCAN_ECR_RP_Pos)                         /*!< 0x00008000 */
#define FDCAN_ECR_RP                              FDCAN_ECR_RP_Msk                                  /*!< Receive Error Passive */
#define FDCAN_ECR_CEL_Pos                         (16U)
#define FDCAN_ECR_CEL_Msk                         (0xFFUL<<FDCAN_ECR_CEL_Pos)                       /*!< 0x00FF0000 */
#define FDCAN_ECR_CEL                             FDCAN_ECR_CEL_Msk                                 /*!< CAN Error Logging */

/********************************* Bit definition for FDCAN_PSR register ********************************************/
#define FDCAN_PSR_LEC_Pos                         (0U)
#define FDCAN_PSR_LEC_Msk                         (0x7UL<<FDCAN_PSR_LEC_Pos)                        /*!< 0x00000007 */
#define FDCAN_PSR_LEC                             FDCAN_PSR_LEC_Msk                                 /*!< Last Error Code */
#define FDCAN_PSR_LEC_0                           (0x1UL<<FDCAN_PSR_LEC_Pos)                        /*!< 0x00000001 */
#define FDCAN_PSR_LEC_1                           (0x2UL<<FDCAN_PSR_LEC_Pos)                        /*!< 0x00000002 */
#define FDCAN_PSR_LEC_2                           (0x4UL<<FDCAN_PSR_LEC_Pos)                        /*!< 0x00000004 */
#define FDCAN_PSR_ACT_Pos                         (3U)
#define FDCAN_PSR_ACT_Msk                         (0x3UL<<FDCAN_PSR_ACT_Pos)                        /*!< 0x00000018 */
#define FDCAN_PSR_ACT                             FDCAN_PSR_ACT_Msk                                 /*!< Activity */
#define FDCAN_PSR_ACT_0                           (0x1UL<<FDCAN_PSR_ACT_Pos)                        /*!< 0x00000008 */
#define FDCAN_PSR_ACT_1                           (0x2UL<<FDCAN_PSR_ACT_Pos)                        /*!< 0x00000010 */
#define FDCAN_PSR_EP_Pos                          (5U)
#define FDCAN_PSR_EP_Msk                          (0x1UL<<FDCAN_PSR_EP_Pos)                         /*!< 0x00000020 */
#define FDCAN_PSR_EP                              FDCAN_PSR_EP_Msk                                  /*!< Error Passive */
#define FDCAN_PSR_EW_Pos                          (6U)
#define FDCAN_PSR_EW_Msk                          (0x1UL<<FDCAN_PSR_EW_Pos)                         /*!< 0x00000040 */
#define FDCAN_PSR_EW                              FDCAN_PSR_EW_Msk                                  /*!< Warning Status */
#define FDCAN_PSR_BO_Pos                          (7U)
#define FDCAN_PSR_BO_Msk                          (0x1UL<<FDCAN_PSR_BO_Pos)                         /*!< 0x00000080 */
#define FDCAN_PSR_BO                              FDCAN_PSR_BO_Msk                                  /*!< Bus_Off Status */
#define FDCAN_PSR_DLEC_Pos                        (8U)
#define FDCAN_PSR_DLEC_Msk                        (0x7UL<<FDCAN_PSR_DLEC_Pos)                       /*!< 0x00000700 */
#define FDCAN_PSR_DLEC                            FDCAN_PSR_DLEC_Msk                                /*!< Data Phase Last Error Code */
#define FDCAN_PSR_DLEC_0                          (0x1UL<<FDCAN_PSR_DLEC_Pos)                       /*!< 0x00000100 */
#define FDCAN_PSR_DLEC_1                          (0x2UL<<FDCAN_PSR_DLEC_Pos)                       /*!< 0x00000200 */
#define FDCAN_PSR_DLEC_2                          (0x4UL<<FDCAN_PSR_DLEC_Pos)                       /*!< 0x00000400 */
#define FDCAN_PSR_RESI_Pos                        (11U)
#define FDCAN_PSR_RESI_Msk                        (0x1UL<<FDCAN_PSR_RESI_Pos)                       /*!< 0x00000800 */
#define FDCAN_PSR_RESI                            FDCAN_PSR_RESI_Msk                                /*!< ESI flag of last received CAN FD Message */
#define FDCAN_PSR_RBRS_Pos                        (12U)
#define FDCAN_PSR_RBRS_Msk                        (0x1UL<<FDCAN_PSR_RBRS_Pos)                       /*!< 0x00001000 */
#define FDCAN_PSR_RBRS                            FDCAN_PSR_RBRS_Msk                                /*!< BRS flag of last received CAN FD Message */
#define FDCAN_PSR_RFDF_Pos                        (13U)
#define FDCAN_PSR_RFDF_Msk                        (0x1UL<<FDCAN_PSR_RFDF_Pos)                       /*!< 0x00002000 */
#define FDCAN_PSR_RFDF                            FDCAN_PSR_RFDF_Msk                                /*!< Received a CAN FD Message */
#define FDCAN_PSR_PXE_Pos                         (14U)
#define FDCAN_PSR_PXE_Msk                         (0x1UL<<FDCAN_PSR_PXE_Pos)                        /*!< 0x00004000 */
#define FDCAN_PSR_PXE                             FDCAN_PSR_PXE_Msk                                 /*!< Protocol Exception Event */
#define FDCAN_PSR_TDCV_Pos                        (16U)
#define FDCAN_PSR_TDCV_Msk                        (0x7FUL<<FDCAN_PSR_TDCV_Pos)                      /*!< 0x007F0000 */
#define FDCAN_PSR_TDCV                            FDCAN_PSR_TDCV_Msk                                /*!< Transmitter Delay Compensation Value */

/********************************* Bit definition for FDCAN_TDCR register *******************************************/
#define FDCAN_TDCR_TDCF_Pos                       (0U)
#define FDCAN_TDCR_TDCF_Msk                       (0x7FUL<<FDCAN_TDCR_TDCF_Pos)                     /*!< 0x0000007F */
#define FDCAN_TDCR_TDCF                           FDCAN_TDCR_TDCF_Msk                               /*!< Transmitter Delay Compensation Filter Window Length */
#define FDCAN_TDCR_TDCO_Pos                       (8U)
#define FDCAN_TDCR_TDCO_Msk                       (0x7FUL<<FDCAN_TDCR_TDCO_Pos)                     /*!< 0x00007F00 */
#define FDCAN_TDCR_TDCO                           FDCAN_TDCR_TDCO_Msk                               /*!< Transmitter Delay Compensation SSP Offset */

/********************************* Bit definition for FDCAN_IR register *********************************************/
#define FDCAN_IR_RF0N_Pos                         (0U)
#define FDCAN_IR_RF0N_Msk                         (0x1UL<<FDCAN_IR_RF0N_Pos)                        /*!< 0x00000001 */
#define FDCAN_IR_RF0N                             FDCAN_IR_RF0N_Msk                                 /*!< Rx FIFO 0 New Message */
#define FDCAN_IR_RF0W_Pos                         (1U)
#define FDCAN_IR_RF0W_Msk                         (0x1UL<<FDCAN_IR_RF0W_Pos)                        /*!< 0x00000002 */
#define FDCAN_IR_RF0W                             FDCAN_IR_RF0W_Msk                                 /*!< Rx FIFO 0 Watermark Reached */
#define FDCAN_IR_RF0F_Pos                         (2U)
#define FDCAN_IR_RF0F_Msk                         (0x1UL<<FDCAN_IR_RF0F_Pos)                        /*!< 0x00000004 */
#define FDCAN_IR_RF0F                             FDCAN_IR_RF0F_Msk                                 /*!< Rx FIFO 0 Full */
#define FDCAN_IR_RF0L_Pos                         (3U)
#define FDCAN_IR_RF0L_Msk                         (0x1UL<<FDCAN_IR_RF0L_Pos)                        /*!< 0x00000008 */
#define FDCAN_IR_RF0L                             FDCAN_IR_RF0L_Msk                                 /*!< Rx FIFO 0 Message Lost */
#define FDCAN_IR_RF1N_Pos                         (4U)
#define FDCAN_IR_RF1N_Msk                         (0x1UL<<FDCAN_IR_RF1N_Pos)                        /*!< 0x00000010 */
#define FDCAN_IR_RF1N                             FDCAN_IR_RF1N_Msk                                 /*!< Rx FIFO 1 New Message */
#define FDCAN_IR_RF1W_Pos                         (5U)
#define FDCAN_IR_RF1W_Msk                         (0x1UL<<FDCAN_IR_RF1W_Pos)                        /*!< 0x00000020 */
#define FDCAN_IR_RF1W                             FDCAN_IR_RF1W_Msk                                 /*!< Rx FIFO 1 Watermark Reached */
#define FDCAN_IR_RF1F_Pos                         (6U)
#define FDCAN_IR_RF1F_Msk                         (0x1UL<<FDCAN_IR_RF1F_Pos)                        /*!< 0x00000040 */
#define FDCAN_IR_RF1F                             FDCAN_IR_RF1F_Msk                                 /*!< Rx FIFO 1 Full */
#define FDCAN_IR_RF1L_Pos                         (7U)
#define FDCAN_IR_RF1L_Msk                         (0x1UL<<FDCAN_IR_RF1L_Pos)                        /*!< 0x00000080 */
#define FDCAN_IR_RF1L                             FDCAN_IR_RF1L_Msk                                 /*!< Rx FIFO 1 Message Lost */
#define FDCAN_IR_HPM_Pos                          (8U)
#define FDCAN_IR_HPM_Msk                          (0x1UL<<FDCAN_IR_HPM_Pos)                         /*!< 0x00000100 */
#define FDCAN_IR_HPM                              FDCAN_IR_HPM_Msk                                  /*!< High Priority Message */
#define FDCAN_IR_TC_Pos                           (9U)
#define FDCAN_IR_TC_Msk                           (0x1UL<<FDCAN_IR_TC_Pos)                          /*!< 0x00000200 */
#define FDCAN_IR_TC                               FDCAN_IR_TC_Msk                                   /*!< Transmission Completed */
#define FDCAN_IR_TCF_Pos                          (10U)
#define FDCAN_IR_TCF_Msk                          (0x1UL<<FDCAN_IR_TCF_Pos)                         /*!< 0x00000400 */
#define FDCAN_IR_TCF                              FDCAN_IR_TCF_Msk                                  /*!< Transmission Cancellation Finished */
#define FDCAN_IR_TFE_Pos                          (11U)
#define FDCAN_IR_TFE_Msk                          (0x1UL<<FDCAN_IR_TFE_Pos)                         /*!< 0x00000800 */
#define FDCAN_IR_TFE                              FDCAN_IR_TFE_Msk                                  /*!< Tx FIFO Empty */
#define FDCAN_IR_TEFN_Pos                         (12U)
#define FDCAN_IR_TEFN_Msk                         (0x1UL<<FDCAN_IR_TEFN_Pos)                        /*!< 0x00001000 */
#define FDCAN_IR_TEFN                             FDCAN_IR_TEFN_Msk                                 /*!< Tx Event FIFO New Entry */
#define FDCAN_IR_TEFW_Pos                         (13U)
#define FDCAN_IR_TEFW_Msk                         (0x1UL<<FDCAN_IR_TEFW_Pos)                        /*!< 0x00002000 */
#define FDCAN_IR_TEFW                             FDCAN_IR_TEFW_Msk                                 /*!< Tx Event FIFO Watermark Reached */
#define FDCAN_IR_TEFF_Pos                         (14U)
#define FDCAN_IR_TEFF_Msk                         (0x1UL<<FDCAN_IR_TEFF_Pos)                        /*!< 0x00004000 */
#define FDCAN_IR_TEFF                             FDCAN_IR_TEFF_Msk                                 /*!< Tx Event FIFO Full */
#define FDCAN_IR_TEFL_Pos                         (15U)
#define FDCAN_IR_TEFL_Msk                         (0x1UL<<FDCAN_IR_TEFL_Pos)                        /*!< 0x00008000 */
#define FDCAN_IR_TEFL                             FDCAN_IR_TEFL_Msk                                 /*!< Tx Event FIFO Element Lost */
#define FDCAN_IR_TSW_Pos                          (16U)
#define FDCAN_IR_TSW_Msk                          (0x1UL<<FDCAN_IR_TSW_Pos)                         /*!< 0x00010000 */
#define FDCAN_IR_TSW                              FDCAN_IR_TSW_Msk                                  /*!< Timestamp Wraparound */
#define FDCAN_IR_MRAF_Pos                         (17U)
#define FDCAN_IR_MRAF_Msk                         (0x1UL<<FDCAN_IR_MRAF_Pos)                        /*!< 0x00020000 */
#define FDCAN_IR_MRAF                             FDCAN_IR_MRAF_Msk                                 /*!< Message RAM Access Failure */
#define FDCAN_IR_TOO_Pos                          (18U)
#define FDCAN_IR_TOO_Msk                          (0x1UL<<FDCAN_IR_TOO_Pos)                         /*!< 0x00040000 */
#define FDCAN_IR_TOO                              FDCAN_IR_TOO_Msk                                  /*!< Timeout Occurred */
#define FDCAN_IR_DRX_Pos                          (19U)
#define FDCAN_IR_DRX_Msk                          (0x1UL<<FDCAN_IR_DRX_Pos)                         /*!< 0x00080000 */
#define FDCAN_IR_DRX                              FDCAN_IR_DRX_Msk                                  /*!< Message stored to Dedicated Rx Buffer */
#define FDCAN_IR_BEC_Pos                          (20U)
#define FDCAN_IR_BEC_Msk                          (0x1UL<<FDCAN_IR_BEC_Pos)                         /*!< 0x00100000 */
#define FDCAN_IR_BEC                              FDCAN_IR_BEC_Msk                                  /*!< Bit Error Corrected */
#define FDCAN_IR_BEU_Pos                          (21U)
#define FDCAN_IR_BEU_Msk                          (0x1UL<<FDCAN_IR_BEU_Pos)                         /*!< 0x00200000 */
#define FDCAN_IR_BEU                              FDCAN_IR_BEU_Msk                                  /*!< Bit Error Uncorrected */
#define FDCAN_IR_ELO_Pos                          (22U)
#define FDCAN_IR_ELO_Msk                          (0x1UL<<FDCAN_IR_ELO_Pos)                         /*!< 0x00400000 */
#define FDCAN_IR_ELO                              FDCAN_IR_ELO_Msk                                  /*!< Error Logging Overflow */
#define FDCAN_IR_EP_Pos                           (23U)
#define FDCAN_IR_EP_Msk                           (0x1UL<<FDCAN_IR_EP_Pos)                          /*!< 0x00800000 */
#define FDCAN_IR_EP                               FDCAN_IR_EP_Msk                                   /*!< Error Passive */
#define FDCAN_IR_EW_Pos                           (24U)
#define FDCAN_IR_EW_Msk                           (0x1UL<<FDCAN_IR_EW_Pos)                          /*!< 0x01000000 */
#define FDCAN_IR_EW                               FDCAN_IR_EW_Msk                                   /*!< Warning Status */
#define FDCAN_IR_BO_Pos                           (25U)
#define FDCAN_IR_BO_Msk                           (0x1UL<<FDCAN_IR_BO_Pos)                          /*!< 0x02000000 */
#define FDCAN_IR_BO                               FDCAN_IR_BO_Msk                                   /*!< Bus_Off Status */
#define FDCAN_IR_WDI_Pos                          (26U)
#define FDCAN_IR_WDI_Msk                          (0x1UL<<FDCAN_IR_WDI_Pos)                         /*!< 0x04000000 */
#define FDCAN_IR_WDI                              FDCAN_IR_WDI_Msk                                  /*!< Watchdog Interrupt */
#define FDCAN_IR_PEA_Pos                          (27U)
#define FDCAN_IR_PEA_Msk                          (0x1UL<<FDCAN_IR_PEA_Pos)                         /*!< 0x08000000 */
#define FDCAN_IR_PEA                              FDCAN_IR_PEA_Msk                                  /*!< Protocol Error in Arbitration Phase  */
#define FDCAN_IR_PED_Pos                          (28U)
#define FDCAN_IR_PED_Msk                          (0x1UL<<FDCAN_IR_PED_Pos)                         /*!< 0x10000000 */
#define FDCAN_IR_PED                              FDCAN_IR_PED_Msk                                  /*!< Protocol Error in Data Phase (Data Bit Time is used) */
#define FDCAN_IR_ARA_Pos                          (29U)
#define FDCAN_IR_ARA_Msk                          (0x1UL<<FDCAN_IR_ARA_Pos)                         /*!< 0x20000000 */
#define FDCAN_IR_ARA                              FDCAN_IR_ARA_Msk                                  /*!< Access to Reserved Address */

/********************************* Bit definition for FDCAN_IE register *********************************************/
#define FDCAN_IE_RF0NE_Pos                        (0U)
#define FDCAN_IE_RF0NE_Msk                        (0x1UL<<FDCAN_IE_RF0NE_Pos)                       /*!< 0x00000001 */
#define FDCAN_IE_RF0NE                            FDCAN_IE_RF0NE_Msk                                /*!< Rx FIFO 1 New Message Interrupt Enable */
#define FDCAN_IE_RF0WE_Pos                        (1U)
#define FDCAN_IE_RF0WE_Msk                        (0x1UL<<FDCAN_IE_RF0WE_Pos)                       /*!< 0x00000002 */
#define FDCAN_IE_RF0WE                            FDCAN_IE_RF0WE_Msk                                /*!< Rx FIFO 1 Watermark Reached Interrupt Enable */
#define FDCAN_IE_RF0FE_Pos                        (2U)
#define FDCAN_IE_RF0FE_Msk                        (0x1UL<<FDCAN_IE_RF0FE_Pos)                       /*!< 0x00000004 */
#define FDCAN_IE_RF0FE                            FDCAN_IE_RF0FE_Msk                                /*!< Rx FIFO 1 Full Interrupt Enable */
#define FDCAN_IE_RF0LE_Pos                        (3U)
#define FDCAN_IE_RF0LE_Msk                        (0x1UL<<FDCAN_IE_RF0LE_Pos)                       /*!< 0x00000008 */
#define FDCAN_IE_RF0LE                            FDCAN_IE_RF0LE_Msk                                /*!< Rx FIFO 1 Message Lost Interrupt Enable */
#define FDCAN_IE_RF1NE_Pos                        (4U)
#define FDCAN_IE_RF1NE_Msk                        (0x1UL<<FDCAN_IE_RF1NE_Pos)                       /*!< 0x00000010 */
#define FDCAN_IE_RF1NE                            FDCAN_IE_RF1NE_Msk                                /*!< Rx FIFO 2 New Message Interrupt Enable */
#define FDCAN_IE_RF1WE_Pos                        (5U)
#define FDCAN_IE_RF1WE_Msk                        (0x1UL<<FDCAN_IE_RF1WE_Pos)                       /*!< 0x00000020 */
#define FDCAN_IE_RF1WE                            FDCAN_IE_RF1WE_Msk                                /*!< Rx FIFO 2 Watermark Reached Interrupt Enable */
#define FDCAN_IE_RF1FE_Pos                        (6U)
#define FDCAN_IE_RF1FE_Msk                        (0x1UL<<FDCAN_IE_RF1FE_Pos)                       /*!< 0x00000040 */
#define FDCAN_IE_RF1FE                            FDCAN_IE_RF1FE_Msk                                /*!< Rx FIFO 2 Full Interrupt Enable */
#define FDCAN_IE_RF1LE_Pos                        (7U)
#define FDCAN_IE_RF1LE_Msk                        (0x1UL<<FDCAN_IE_RF1LE_Pos)                       /*!< 0x00000080 */
#define FDCAN_IE_RF1LE                            FDCAN_IE_RF1LE_Msk                                /*!< Rx FIFO 2 Message Lost Interrupt Enable */
#define FDCAN_IE_HPME_Pos                         (8U)
#define FDCAN_IE_HPME_Msk                         (0x1UL<<FDCAN_IE_HPME_Pos)                        /*!< 0x00000100 */
#define FDCAN_IE_HPME                             FDCAN_IE_HPME_Msk                                 /*!< High Priority Message Interrupt Enable */
#define FDCAN_IE_TCE_Pos                          (9U)
#define FDCAN_IE_TCE_Msk                          (0x1UL<<FDCAN_IE_TCE_Pos)                         /*!< 0x00000200 */
#define FDCAN_IE_TCE                              FDCAN_IE_TCE_Msk                                  /*!< Transmission Completed Interrupt Enable */
#define FDCAN_IE_TCFE_Pos                         (10U)
#define FDCAN_IE_TCFE_Msk                         (0x1UL<<FDCAN_IE_TCFE_Pos)                        /*!< 0x00000400 */
#define FDCAN_IE_TCFE                             FDCAN_IE_TCFE_Msk                                 /*!< Transmission Cancellation Finished Interrupt Enable */
#define FDCAN_IE_TFEE_Pos                         (11U)
#define FDCAN_IE_TFEE_Msk                         (0x1UL<<FDCAN_IE_TFEE_Pos)                        /*!< 0x00000800 */
#define FDCAN_IE_TFEE                             FDCAN_IE_TFEE_Msk                                 /*!< Tx FIFO Empty Interrupt Enable */
#define FDCAN_IE_TEFNE_Pos                        (12U)
#define FDCAN_IE_TEFNE_Msk                        (0x1UL<<FDCAN_IE_TEFNE_Pos)                       /*!< 0x00001000 */
#define FDCAN_IE_TEFNE                            FDCAN_IE_TEFNE_Msk                                /*!< Tx Event FIFO New Entry Interrupt Enable */
#define FDCAN_IE_TEFWE_Pos                        (13U)
#define FDCAN_IE_TEFWE_Msk                        (0x1UL<<FDCAN_IE_TEFWE_Pos)                       /*!< 0x00002000 */
#define FDCAN_IE_TEFWE                            FDCAN_IE_TEFWE_Msk                                /*!< Tx Event FIFO Watermark Reached Interrupt Enable */
#define FDCAN_IE_TEFFE_Pos                        (14U)
#define FDCAN_IE_TEFFE_Msk                        (0x1UL<<FDCAN_IE_TEFFE_Pos)                       /*!< 0x00004000 */
#define FDCAN_IE_TEFFE                            FDCAN_IE_TEFFE_Msk                                /*!< Tx Event FIFO Full Interrupt Enable */
#define FDCAN_IE_TEFLE_Pos                        (15U)
#define FDCAN_IE_TEFLE_Msk                        (0x1UL<<FDCAN_IE_TEFLE_Pos)                       /*!< 0x00008000 */
#define FDCAN_IE_TEFLE                            FDCAN_IE_TEFLE_Msk                                /*!< Tx Event FIFO Event Lost Interrupt Enable */
#define FDCAN_IE_TSWE_Pos                         (16U)
#define FDCAN_IE_TSWE_Msk                         (0x1UL<<FDCAN_IE_TSWE_Pos)                        /*!< 0x00010000 */
#define FDCAN_IE_TSWE                             FDCAN_IE_TSWE_Msk                                 /*!< Timestamp Wraparound Interrupt Enable */
#define FDCAN_IE_MRAFE_Pos                        (17U)
#define FDCAN_IE_MRAFE_Msk                        (0x1UL<<FDCAN_IE_MRAFE_Pos)                       /*!< 0x00020000 */
#define FDCAN_IE_MRAFE                            FDCAN_IE_MRAFE_Msk                                /*!< Message RAM Access Failure Interrupt Enable */
#define FDCAN_IE_TOOE_Pos                         (18U)
#define FDCAN_IE_TOOE_Msk                         (0x1UL<<FDCAN_IE_TOOE_Pos)                        /*!< 0x00040000 */
#define FDCAN_IE_TOOE                             FDCAN_IE_TOOE_Msk                                 /*!< Timeout Occurred Interrupt Enable */
#define FDCAN_IE_DRXE_Pos                         (19U)
#define FDCAN_IE_DRXE_Msk                         (0x1UL<<FDCAN_IE_DRXE_Pos)                        /*!< 0x00080000 */
#define FDCAN_IE_DRXE                             FDCAN_IE_DRXE_Msk                                 /*!< Message stored to Dedicated Rx Buffer Interrupt Enable */
#define FDCAN_IE_BECE_Pos                         (20U)
#define FDCAN_IE_BECE_Msk                         (0x1UL<<FDCAN_IE_BECE_Pos)                        /*!< 0x00100000 */
#define FDCAN_IE_BECE                             FDCAN_IE_BECE_Msk                                 /*!< Bit Error Corrected Interrupt Enable */
#define FDCAN_IE_BEUE_Pos                         (21U)
#define FDCAN_IE_BEUE_Msk                         (0x1UL<<FDCAN_IE_BEUE_Pos)                        /*!< 0x00200000 */
#define FDCAN_IE_BEUE                             FDCAN_IE_BEUE_Msk                                 /*!< Bit Error Uncorrected Interrupt Enable */
#define FDCAN_IE_ELOE_Pos                         (22U)
#define FDCAN_IE_ELOE_Msk                         (0x1UL<<FDCAN_IE_ELOE_Pos)                        /*!< 0x00400000 */
#define FDCAN_IE_ELOE                             FDCAN_IE_ELOE_Msk                                 /*!< Error Logging Overflow Interrupt Enable */
#define FDCAN_IE_EPE_Pos                          (23U)
#define FDCAN_IE_EPE_Msk                          (0x1UL<<FDCAN_IE_EPE_Pos)                         /*!< 0x00800000 */
#define FDCAN_IE_EPE                              FDCAN_IE_EPE_Msk                                  /*!< Error Passive Interrupt Enable */
#define FDCAN_IE_EWE_Pos                          (24U)
#define FDCAN_IE_EWE_Msk                          (0x1UL<<FDCAN_IE_EWE_Pos)                         /*!< 0x01000000 */
#define FDCAN_IE_EWE                              FDCAN_IE_EWE_Msk                                  /*!< Warning Status Interrupt Enable */
#define FDCAN_IE_BOE_Pos                          (25U)
#define FDCAN_IE_BOE_Msk                          (0x1UL<<FDCAN_IE_BOE_Pos)                         /*!< 0x02000000 */
#define FDCAN_IE_BOE                              FDCAN_IE_BOE_Msk                                  /*!< Bus_Off Status Interrupt Enable */
#define FDCAN_IE_WDIE_Pos                         (26U)
#define FDCAN_IE_WDIE_Msk                         (0x1UL<<FDCAN_IE_WDIE_Pos)                        /*!< 0x04000000 */
#define FDCAN_IE_WDIE                             FDCAN_IE_WDIE_Msk                                 /*!< Watchdog Interrupt Enable */
#define FDCAN_IE_PEAE_Pos                         (27U)
#define FDCAN_IE_PEAE_Msk                         (0x1UL<<FDCAN_IE_PEAE_Pos)                        /*!< 0x08000000 */
#define FDCAN_IE_PEAE                             FDCAN_IE_PEAE_Msk                                 /*!< Protocol Error in Arbitration Phase Enable */
#define FDCAN_IE_PEDE_Pos                         (28U)
#define FDCAN_IE_PEDE_Msk                         (0x1UL<<FDCAN_IE_PEDE_Pos)                        /*!< 0x10000000 */
#define FDCAN_IE_PEDE                             FDCAN_IE_PEDE_Msk                                 /*!< Protocol Error in Data Phase Enable */
#define FDCAN_IE_ARAE_Pos                         (29U)
#define FDCAN_IE_ARAE_Msk                         (0x1UL<<FDCAN_IE_ARAE_Pos)                        /*!< 0x20000000 */
#define FDCAN_IE_ARAE                             FDCAN_IE_ARAE_Msk                                 /*!< Access to Reserved Address Enable */

/********************************* Bit definition for FDCAN_ILS register ********************************************/
#define FDCAN_ILS_RF0NL_Pos                       (0U)
#define FDCAN_ILS_RF0NL_Msk                       (0x1UL<<FDCAN_ILS_RF0NL_Pos)                      /*!< 0x00000001 */
#define FDCAN_ILS_RF0NL                           FDCAN_ILS_RF0NL_Msk                               /*!< Rx FIFO 1 New Message Interrupt Line */
#define FDCAN_ILS_RF0WL_Pos                       (1U)
#define FDCAN_ILS_RF0WL_Msk                       (0x1UL<<FDCAN_ILS_RF0WL_Pos)                      /*!< 0x00000002 */
#define FDCAN_ILS_RF0WL                           FDCAN_ILS_RF0WL_Msk                               /*!< Rx FIFO 1 Watermark Reached Interrupt Line */
#define FDCAN_ILS_RF0FL_Pos                       (2U)
#define FDCAN_ILS_RF0FL_Msk                       (0x1UL<<FDCAN_ILS_RF0FL_Pos)                      /*!< 0x00000004 */
#define FDCAN_ILS_RF0FL                           FDCAN_ILS_RF0FL_Msk                               /*!< Rx FIFO 1 Full Interrupt Line */
#define FDCAN_ILS_RF0LL_Pos                       (3U)
#define FDCAN_ILS_RF0LL_Msk                       (0x1UL<<FDCAN_ILS_RF0LL_Pos)                      /*!< 0x00000008 */
#define FDCAN_ILS_RF0LL                           FDCAN_ILS_RF0LL_Msk                               /*!< Rx FIFO 1 Message Lost Interrupt Line */
#define FDCAN_ILS_RF1NL_Pos                       (4U)
#define FDCAN_ILS_RF1NL_Msk                       (0x1UL<<FDCAN_ILS_RF1NL_Pos)                      /*!< 0x00000010 */
#define FDCAN_ILS_RF1NL                           FDCAN_ILS_RF1NL_Msk                               /*!< Rx FIFO 2 New Message Interrupt Line */
#define FDCAN_ILS_RF1WL_Pos                       (5U)
#define FDCAN_ILS_RF1WL_Msk                       (0x1UL<<FDCAN_ILS_RF1WL_Pos)                      /*!< 0x00000020 */
#define FDCAN_ILS_RF1WL                           FDCAN_ILS_RF1WL_Msk                               /*!< Rx FIFO 2 Watermark Reached Interrupt Line */
#define FDCAN_ILS_RF1FL_Pos                       (6U)
#define FDCAN_ILS_RF1FL_Msk                       (0x1UL<<FDCAN_ILS_RF1FL_Pos)                      /*!< 0x00000040 */
#define FDCAN_ILS_RF1FL                           FDCAN_ILS_RF1FL_Msk                               /*!< Rx FIFO 2 Full Interrupt Line */
#define FDCAN_ILS_RF1LL_Pos                       (7U)
#define FDCAN_ILS_RF1LL_Msk                       (0x1UL<<FDCAN_ILS_RF1LL_Pos)                      /*!< 0x00000080 */
#define FDCAN_ILS_RF1LL                           FDCAN_ILS_RF1LL_Msk                               /*!< Rx FIFO 2 Message Lost Interrupt Line */
#define FDCAN_ILS_HPML_Pos                        (8U)
#define FDCAN_ILS_HPML_Msk                        (0x1UL<<FDCAN_ILS_HPML_Pos)                       /*!< 0x00000100 */
#define FDCAN_ILS_HPML                            FDCAN_ILS_HPML_Msk                                /*!< High Priority Message Interrupt Line */
#define FDCAN_ILS_TCL_Pos                         (9U)
#define FDCAN_ILS_TCL_Msk                         (0x1UL<<FDCAN_ILS_TCL_Pos)                        /*!< 0x00000200 */
#define FDCAN_ILS_TCL                             FDCAN_ILS_TCL_Msk                                 /*!< Transmission Completed Interrupt Line */
#define FDCAN_ILS_TCFL_Pos                        (10U)
#define FDCAN_ILS_TCFL_Msk                        (0x1UL<<FDCAN_ILS_TCFL_Pos)                       /*!< 0x00000400 */
#define FDCAN_ILS_TCFL                            FDCAN_ILS_TCFL_Msk                                /*!< Transmission Cancellation Finished Interrupt Line */
#define FDCAN_ILS_TFEL_Pos                        (11U)
#define FDCAN_ILS_TFEL_Msk                        (0x1UL<<FDCAN_ILS_TFEL_Pos)                       /*!< 0x00000800 */
#define FDCAN_ILS_TFEL                            FDCAN_ILS_TFEL_Msk                                /*!< Tx FIFO Empty Interrupt Line */
#define FDCAN_ILS_TEFNL_Pos                       (12U)
#define FDCAN_ILS_TEFNL_Msk                       (0x1UL<<FDCAN_ILS_TEFNL_Pos)                      /*!< 0x00001000 */
#define FDCAN_ILS_TEFNL                           FDCAN_ILS_TEFNL_Msk                               /*!< Tx Event FIFO New Entry Interrupt Line */
#define FDCAN_ILS_TEFWL_Pos                       (13U)
#define FDCAN_ILS_TEFWL_Msk                       (0x1UL<<FDCAN_ILS_TEFWL_Pos)                      /*!< 0x00002000 */
#define FDCAN_ILS_TEFWL                           FDCAN_ILS_TEFWL_Msk                               /*!< Tx Event FIFO Watermark Reached Interrupt Line */
#define FDCAN_ILS_TEFFL_Pos                       (14U)
#define FDCAN_ILS_TEFFL_Msk                       (0x1UL<<FDCAN_ILS_TEFFL_Pos)                      /*!< 0x00004000 */
#define FDCAN_ILS_TEFFL                           FDCAN_ILS_TEFFL_Msk                               /*!< Tx Event FIFO Full Interrupt Line */
#define FDCAN_ILS_TEFLL_Pos                       (15U)
#define FDCAN_ILS_TEFLL_Msk                       (0x1UL<<FDCAN_ILS_TEFLL_Pos)                      /*!< 0x00008000 */
#define FDCAN_ILS_TEFLL                           FDCAN_ILS_TEFLL_Msk                               /*!< Tx Event FIFO Event Lost Interrupt Line */
#define FDCAN_ILS_TSWL_Pos                        (16U)
#define FDCAN_ILS_TSWL_Msk                        (0x1UL<<FDCAN_ILS_TSWL_Pos)                       /*!< 0x00010000 */
#define FDCAN_ILS_TSWL                            FDCAN_ILS_TSWL_Msk                                /*!< Timestamp Wraparound Interrupt Line */
#define FDCAN_ILS_MRAFL_Pos                       (17U)
#define FDCAN_ILS_MRAFL_Msk                       (0x1UL<<FDCAN_ILS_MRAFL_Pos)                      /*!< 0x00020000 */
#define FDCAN_ILS_MRAFL                           FDCAN_ILS_MRAFL_Msk                               /*!< Message RAM Access Failure Interrupt Line */
#define FDCAN_ILS_TOOL_Pos                        (18U)
#define FDCAN_ILS_TOOL_Msk                        (0x1UL<<FDCAN_ILS_TOOL_Pos)                       /*!< 0x00040000 */
#define FDCAN_ILS_TOOL                            FDCAN_ILS_TOOL_Msk                                /*!< Timeout Occurred Interrupt Line */
#define FDCAN_ILS_DRXL_Pos                        (19U)
#define FDCAN_ILS_DRXL_Msk                        (0x1UL<<FDCAN_ILS_DRXL_Pos)                       /*!< 0x00080000 */
#define FDCAN_ILS_DRXL                            FDCAN_ILS_DRXL_Msk                                /*!< Message stored to Dedicated Rx Buffer Interrupt Line */
#define FDCAN_ILS_BECL_Pos                        (20U)
#define FDCAN_ILS_BECL_Msk                        (0x1UL<<FDCAN_ILS_BECL_Pos)                       /*!< 0x00100000 */
#define FDCAN_ILS_BECL                            FDCAN_ILS_BECL_Msk                                /*!< Bit Error Corrected Interrupt Line */
#define FDCAN_ILS_BEUL_Pos                        (21U)
#define FDCAN_ILS_BEUL_Msk                        (0x1UL<<FDCAN_ILS_BEUL_Pos)                       /*!< 0x00200000 */
#define FDCAN_ILS_BEUL                            FDCAN_ILS_BEUL_Msk                                /*!< Bit Error Uncorrected Interrupt Line */
#define FDCAN_ILS_ELOL_Pos                        (22U)
#define FDCAN_ILS_ELOL_Msk                        (0x1UL<<FDCAN_ILS_ELOL_Pos)                       /*!< 0x00400000 */
#define FDCAN_ILS_ELOL                            FDCAN_ILS_ELOL_Msk                                /*!< Error Logging Overflow Interrupt Line */
#define FDCAN_ILS_EPL_Pos                         (23U)
#define FDCAN_ILS_EPL_Msk                         (0x1UL<<FDCAN_ILS_EPL_Pos)                        /*!< 0x00800000 */
#define FDCAN_ILS_EPL                             FDCAN_ILS_EPL_Msk                                 /*!< Error Passive Interrupt Line */
#define FDCAN_ILS_EWL_Pos                         (24U)
#define FDCAN_ILS_EWL_Msk                         (0x1UL<<FDCAN_ILS_EWL_Pos)                        /*!< 0x01000000 */
#define FDCAN_ILS_EWL                             FDCAN_ILS_EWL_Msk                                 /*!< Warning Status Interrupt Line */
#define FDCAN_ILS_BOL_Pos                         (25U)
#define FDCAN_ILS_BOL_Msk                         (0x1UL<<FDCAN_ILS_BOL_Pos)                        /*!< 0x02000000 */
#define FDCAN_ILS_BOL                             FDCAN_ILS_BOL_Msk                                 /*!< Bus_Off Status Interrupt Line */
#define FDCAN_ILS_WDIL_Pos                        (26U)
#define FDCAN_ILS_WDIL_Msk                        (0x1UL<<FDCAN_ILS_WDIL_Pos)                       /*!< 0x04000000 */
#define FDCAN_ILS_WDIL                            FDCAN_ILS_WDIL_Msk                                /*!< Watchdog Interrupt Line */
#define FDCAN_ILS_PEAL_Pos                        (27U)
#define FDCAN_ILS_PEAL_Msk                        (0x1UL<<FDCAN_ILS_PEAL_Pos)                       /*!< 0x08000000 */
#define FDCAN_ILS_PEAL                            FDCAN_ILS_PEAL_Msk                                /*!< Protocol Error in Arbitration Phase Line */
#define FDCAN_ILS_PEDL_Pos                        (28U)
#define FDCAN_ILS_PEDL_Msk                        (0x1UL<<FDCAN_ILS_PEDL_Pos)                       /*!< 0x10000000 */
#define FDCAN_ILS_PEDL                            FDCAN_ILS_PEDL_Msk                                /*!< Protocol Error in Data Phase Line */
#define FDCAN_ILS_ARAL_Pos                        (29U)
#define FDCAN_ILS_ARAL_Msk                        (0x1UL<<FDCAN_ILS_ARAL_Pos)                       /*!< 0x20000000 */
#define FDCAN_ILS_ARAL                            FDCAN_ILS_ARAL_Msk                                /*!< Access to Reserved Address Line */

/********************************* Bit definition for FDCAN_ILE register ********************************************/
#define FDCAN_ILE_EINT0_Pos                       (0U)
#define FDCAN_ILE_EINT0_Msk                       (0x1UL<<FDCAN_ILE_EINT0_Pos)                      /*!< 0x00000001 */
#define FDCAN_ILE_EINT0                           FDCAN_ILE_EINT0_Msk                               /*!< Enable Interrupt Line 0 */
#define FDCAN_ILE_EINT1_Pos                       (1U)
#define FDCAN_ILE_EINT1_Msk                       (0x1UL<<FDCAN_ILE_EINT1_Pos)                      /*!< 0x00000002 */
#define FDCAN_ILE_EINT1                           FDCAN_ILE_EINT1_Msk                               /*!< Enable Interrupt Line 1 */

/********************************* Bit definition for FDCAN_GFC register ********************************************/
#define FDCAN_GFC_RRFE_Pos                        (0U)
#define FDCAN_GFC_RRFE_Msk                        (0x1UL<<FDCAN_GFC_RRFE_Pos)                       /*!< 0x00000001 */
#define FDCAN_GFC_RRFE                            FDCAN_GFC_RRFE_Msk                                /*!< Reject Remote Frames Extended */
#define FDCAN_GFC_RRFS_Pos                        (1U)
#define FDCAN_GFC_RRFS_Msk                        (0x1UL<<FDCAN_GFC_RRFS_Pos)                       /*!< 0x00000002 */
#define FDCAN_GFC_RRFS                            FDCAN_GFC_RRFS_Msk                                /*!< Reject Remote Frames Standard */
#define FDCAN_GFC_ANFE_Pos                        (2U)
#define FDCAN_GFC_ANFE_Msk                        (0x3UL<<FDCAN_GFC_ANFE_Pos)                       /*!< 0x0000000C */
#define FDCAN_GFC_ANFE                            FDCAN_GFC_ANFE_Msk                                /*!< Accept Non-matching Frames Extended */
#define FDCAN_GFC_ANFE_0                          (0x1UL<<FDCAN_GFC_ANFE_Pos)                       /*!< 0x00000004 */
#define FDCAN_GFC_ANFE_1                          (0x2UL<<FDCAN_GFC_ANFE_Pos)                       /*!< 0x00000008 */
#define FDCAN_GFC_ANFS_Pos                        (4U)
#define FDCAN_GFC_ANFS_Msk                        (0x3UL<<FDCAN_GFC_ANFS_Pos)                       /*!< 0x00000030 */
#define FDCAN_GFC_ANFS                            FDCAN_GFC_ANFS_Msk                                /*!< Accept Non-matching Frames Standard */
#define FDCAN_GFC_ANFS_0                          (0x1UL<<FDCAN_GFC_ANFS_Pos)                       /*!< 0x00000010 */
#define FDCAN_GFC_ANFS_1                          (0x2UL<<FDCAN_GFC_ANFS_Pos)                       /*!< 0x00000020 */

/********************************* Bit definition for FDCAN_SIDFC register ******************************************/
#define FDCAN_SIDFC_FLSSA_Pos                     (2U)
#define FDCAN_SIDFC_FLSSA_Msk                     (0x3FFFUL<<FDCAN_SIDFC_FLSSA_Pos)                 /*!< 0x0000FFFC */
#define FDCAN_SIDFC_FLSSA                         FDCAN_SIDFC_FLSSA_Msk                             /*!< Filter List Standard Start Address */
#define FDCAN_SIDFC_LSS_Pos                       (16U)
#define FDCAN_SIDFC_LSS_Msk                       (0xFFUL<<FDCAN_SIDFC_LSS_Pos)                     /*!< 0x00FF0000 */
#define FDCAN_SIDFC_LSS                           FDCAN_SIDFC_LSS_Msk                               /*!< List Size Standard */

/********************************* Bit definition for FDCAN_XIDFC register ******************************************/
#define FDCAN_XIDFC_FLESA_Pos                     (2U)
#define FDCAN_XIDFC_FLESA_Msk                     (0x3FFFUL<<FDCAN_XIDFC_FLESA_Pos)                 /*!< 0x0000FFFC */
#define FDCAN_XIDFC_FLESA                         FDCAN_XIDFC_FLESA_Msk                             /*!< Filter List Extended Start Address */
#define FDCAN_XIDFC_LSE_Pos                       (16U)
#define FDCAN_XIDFC_LSE_Msk                       (0x7FUL<<FDCAN_XIDFC_LSE_Pos)                     /*!< 0x007F0000 */
#define FDCAN_XIDFC_LSE                           FDCAN_XIDFC_LSE_Msk                               /*!<  List Size Extended */

/********************************* Bit definition for FDCAN_XIDAM register ******************************************/
#define FDCAN_XIDAM_EIDM_Pos                      (0U)
#define FDCAN_XIDAM_EIDM_Msk                      (0x1FFFFFFFUL<<FDCAN_XIDAM_EIDM_Pos)              /*!< 0x1FFFFFFF */
#define FDCAN_XIDAM_EIDM                          FDCAN_XIDAM_EIDM_Msk                              /*!< Extended ID Mask */

/********************************* Bit definition for FDCAN_HPMS register *******************************************/
#define FDCAN_HPMS_BIDX_Pos                       (0U)
#define FDCAN_HPMS_BIDX_Msk                       (0x3FUL<<FDCAN_HPMS_BIDX_Pos)                     /*!< 0x0000003F */
#define FDCAN_HPMS_BIDX                           FDCAN_HPMS_BIDX_Msk                               /*!< Buffer Index */
#define FDCAN_HPMS_BIDX_0                         (0x1UL<<FDCAN_HPMS_BIDX_Pos)                      /*!< 0x00000001 */
#define FDCAN_HPMS_BIDX_1                         (0x2UL<<FDCAN_HPMS_BIDX_Pos)                      /*!< 0x00000002 */
#define FDCAN_HPMS_BIDX_2                         (0x4UL<<FDCAN_HPMS_BIDX_Pos)                      /*!< 0x00000004 */
#define FDCAN_HPMS_BIDX_3                         (0x8UL<<FDCAN_HPMS_BIDX_Pos)                      /*!< 0x00000008 */
#define FDCAN_HPMS_BIDX_4                         (0x10UL<<FDCAN_HPMS_BIDX_Pos)                     /*!< 0x00000010 */
#define FDCAN_HPMS_BIDX_5                         (0x20UL<<FDCAN_HPMS_BIDX_Pos)                     /*!< 0x00000020 */
#define FDCAN_HPMS_MSI_Pos                        (6U)
#define FDCAN_HPMS_MSI_Msk                        (0x3UL<<FDCAN_HPMS_MSI_Pos)                       /*!< 0x000000C0 */
#define FDCAN_HPMS_MSI                            FDCAN_HPMS_MSI_Msk                                /*!<  Message Storage Indicator */
#define FDCAN_HPMS_MSI_0                          (0x1UL<<FDCAN_HPMS_MSI_Pos)                       /*!< 0x00000040 */
#define FDCAN_HPMS_MSI_1                          (0x2UL<<FDCAN_HPMS_MSI_Pos)                       /*!< 0x00000080 */
#define FDCAN_HPMS_FIDX_Pos                       (8U)
#define FDCAN_HPMS_FIDX_Msk                       (0x7FUL<<FDCAN_HPMS_FIDX_Pos)                     /*!< 0x00007F00 */
#define FDCAN_HPMS_FIDX                           FDCAN_HPMS_FIDX_Msk                               /*!< Filter Index */
#define FDCAN_HPMS_FLST_Pos                       (15U)
#define FDCAN_HPMS_FLST_Msk                       (0x1UL<<FDCAN_HPMS_FLST_Pos)                      /*!< 0x00008000 */
#define FDCAN_HPMS_FLST                           FDCAN_HPMS_FLST_Msk                               /*!< Filter List */

/********************************* Bit definition for FDCAN_NDAT1 register ******************************************/
#define FDCAN_NDAT1_ND0_Pos                       (0U)
#define FDCAN_NDAT1_ND0_Msk                       (0x1UL<<FDCAN_NDAT1_ND0_Pos)                      /*!< 0x00000001 */
#define FDCAN_NDAT1_ND0                           FDCAN_NDAT1_ND0_Msk                               /*!< New Data0 */
#define FDCAN_NDAT1_ND1_Pos                       (1U)
#define FDCAN_NDAT1_ND1_Msk                       (0x1UL<<FDCAN_NDAT1_ND1_Pos)                      /*!< 0x00000002 */
#define FDCAN_NDAT1_ND1                           FDCAN_NDAT1_ND1_Msk                               /*!< New Data1 */
#define FDCAN_NDAT1_ND2_Pos                       (2U)
#define FDCAN_NDAT1_ND2_Msk                       (0x1UL<<FDCAN_NDAT1_ND2_Pos)                      /*!< 0x00000004 */
#define FDCAN_NDAT1_ND2                           FDCAN_NDAT1_ND2_Msk                               /*!< New Data2 */
#define FDCAN_NDAT1_ND3_Pos                       (3U)
#define FDCAN_NDAT1_ND3_Msk                       (0x1UL<<FDCAN_NDAT1_ND3_Pos)                      /*!< 0x00000008 */
#define FDCAN_NDAT1_ND3                           FDCAN_NDAT1_ND3_Msk                               /*!< New Data3 */
#define FDCAN_NDAT1_ND4_Pos                       (4U)
#define FDCAN_NDAT1_ND4_Msk                       (0x1UL<<FDCAN_NDAT1_ND4_Pos)                      /*!< 0x00000010 */
#define FDCAN_NDAT1_ND4                           FDCAN_NDAT1_ND4_Msk                               /*!< New Data4 */
#define FDCAN_NDAT1_ND5_Pos                       (5U)
#define FDCAN_NDAT1_ND5_Msk                       (0x1UL<<FDCAN_NDAT1_ND5_Pos)                      /*!< 0x00000020 */
#define FDCAN_NDAT1_ND5                           FDCAN_NDAT1_ND5_Msk                               /*!< New Data5 */
#define FDCAN_NDAT1_ND6_Pos                       (6U)
#define FDCAN_NDAT1_ND6_Msk                       (0x1UL<<FDCAN_NDAT1_ND6_Pos)                      /*!< 0x00000040 */
#define FDCAN_NDAT1_ND6                           FDCAN_NDAT1_ND6_Msk                               /*!< New Data6 */
#define FDCAN_NDAT1_ND7_Pos                       (7U)
#define FDCAN_NDAT1_ND7_Msk                       (0x1UL<<FDCAN_NDAT1_ND7_Pos)                      /*!< 0x00000080 */
#define FDCAN_NDAT1_ND7                           FDCAN_NDAT1_ND7_Msk                               /*!< New Data7 */
#define FDCAN_NDAT1_ND8_Pos                       (8U)
#define FDCAN_NDAT1_ND8_Msk                       (0x1UL<<FDCAN_NDAT1_ND8_Pos)                      /*!< 0x00000100 */
#define FDCAN_NDAT1_ND8                           FDCAN_NDAT1_ND8_Msk                               /*!< New Data8 */
#define FDCAN_NDAT1_ND9_Pos                       (9U)
#define FDCAN_NDAT1_ND9_Msk                       (0x1UL<<FDCAN_NDAT1_ND9_Pos)                      /*!< 0x00000200 */
#define FDCAN_NDAT1_ND9                           FDCAN_NDAT1_ND9_Msk                               /*!< New Data9 */
#define FDCAN_NDAT1_ND10_Pos                      (10U)
#define FDCAN_NDAT1_ND10_Msk                      (0x1UL<<FDCAN_NDAT1_ND10_Pos)                     /*!< 0x00000400 */
#define FDCAN_NDAT1_ND10                          FDCAN_NDAT1_ND10_Msk                              /*!< New Data10 */
#define FDCAN_NDAT1_ND11_Pos                      (11U)
#define FDCAN_NDAT1_ND11_Msk                      (0x1UL<<FDCAN_NDAT1_ND11_Pos)                     /*!< 0x00000800 */
#define FDCAN_NDAT1_ND11                          FDCAN_NDAT1_ND11_Msk                              /*!< New Data11 */
#define FDCAN_NDAT1_ND12_Pos                      (12U)
#define FDCAN_NDAT1_ND12_Msk                      (0x1UL<<FDCAN_NDAT1_ND12_Pos)                     /*!< 0x00001000 */
#define FDCAN_NDAT1_ND12                          FDCAN_NDAT1_ND12_Msk                              /*!< New Data12 */
#define FDCAN_NDAT1_ND13_Pos                      (13U)
#define FDCAN_NDAT1_ND13_Msk                      (0x1UL<<FDCAN_NDAT1_ND13_Pos)                     /*!< 0x00002000 */
#define FDCAN_NDAT1_ND13                          FDCAN_NDAT1_ND13_Msk                              /*!< New Data13 */
#define FDCAN_NDAT1_ND14_Pos                      (14U)
#define FDCAN_NDAT1_ND14_Msk                      (0x1UL<<FDCAN_NDAT1_ND14_Pos)                     /*!< 0x00004000 */
#define FDCAN_NDAT1_ND14                          FDCAN_NDAT1_ND14_Msk                              /*!< New Data14 */
#define FDCAN_NDAT1_ND15_Pos                      (15U)
#define FDCAN_NDAT1_ND15_Msk                      (0x1UL<<FDCAN_NDAT1_ND15_Pos)                     /*!< 0x00008000 */
#define FDCAN_NDAT1_ND15                          FDCAN_NDAT1_ND15_Msk                              /*!< New Data15 */
#define FDCAN_NDAT1_ND16_Pos                      (16U)
#define FDCAN_NDAT1_ND16_Msk                      (0x1UL<<FDCAN_NDAT1_ND16_Pos)                     /*!< 0x00010000 */
#define FDCAN_NDAT1_ND16                          FDCAN_NDAT1_ND16_Msk                              /*!< New Data16 */
#define FDCAN_NDAT1_ND17_Pos                      (17U)
#define FDCAN_NDAT1_ND17_Msk                      (0x1UL<<FDCAN_NDAT1_ND17_Pos)                     /*!< 0x00020000 */
#define FDCAN_NDAT1_ND17                          FDCAN_NDAT1_ND17_Msk                              /*!< New Data17 */
#define FDCAN_NDAT1_ND18_Pos                      (18U)
#define FDCAN_NDAT1_ND18_Msk                      (0x1UL<<FDCAN_NDAT1_ND18_Pos)                     /*!< 0x00040000 */
#define FDCAN_NDAT1_ND18                          FDCAN_NDAT1_ND18_Msk                              /*!< New Data18 */
#define FDCAN_NDAT1_ND19_Pos                      (19U)
#define FDCAN_NDAT1_ND19_Msk                      (0x1UL<<FDCAN_NDAT1_ND19_Pos)                     /*!< 0x00080000 */
#define FDCAN_NDAT1_ND19                          FDCAN_NDAT1_ND19_Msk                              /*!< New Data19 */
#define FDCAN_NDAT1_ND20_Pos                      (20U)
#define FDCAN_NDAT1_ND20_Msk                      (0x1UL<<FDCAN_NDAT1_ND20_Pos)                     /*!< 0x00100000 */
#define FDCAN_NDAT1_ND20                          FDCAN_NDAT1_ND20_Msk                              /*!< New Data20 */
#define FDCAN_NDAT1_ND21_Pos                      (21U)
#define FDCAN_NDAT1_ND21_Msk                      (0x1UL<<FDCAN_NDAT1_ND21_Pos)                     /*!< 0x00200000 */
#define FDCAN_NDAT1_ND21                          FDCAN_NDAT1_ND21_Msk                              /*!< New Data21 */
#define FDCAN_NDAT1_ND22_Pos                      (22U)
#define FDCAN_NDAT1_ND22_Msk                      (0x1UL<<FDCAN_NDAT1_ND22_Pos)                     /*!< 0x00400000 */
#define FDCAN_NDAT1_ND22                          FDCAN_NDAT1_ND22_Msk                              /*!< New Data22 */
#define FDCAN_NDAT1_ND23_Pos                      (23U)
#define FDCAN_NDAT1_ND23_Msk                      (0x1UL<<FDCAN_NDAT1_ND23_Pos)                     /*!< 0x00800000 */
#define FDCAN_NDAT1_ND23                          FDCAN_NDAT1_ND23_Msk                              /*!< New Data23 */
#define FDCAN_NDAT1_ND24_Pos                      (24U)
#define FDCAN_NDAT1_ND24_Msk                      (0x1UL<<FDCAN_NDAT1_ND24_Pos)                     /*!< 0x01000000 */
#define FDCAN_NDAT1_ND24                          FDCAN_NDAT1_ND24_Msk                              /*!< New Data24 */
#define FDCAN_NDAT1_ND25_Pos                      (25U)
#define FDCAN_NDAT1_ND25_Msk                      (0x1UL<<FDCAN_NDAT1_ND25_Pos)                     /*!< 0x02000000 */
#define FDCAN_NDAT1_ND25                          FDCAN_NDAT1_ND25_Msk                              /*!< New Data25 */
#define FDCAN_NDAT1_ND26_Pos                      (26U)
#define FDCAN_NDAT1_ND26_Msk                      (0x1UL<<FDCAN_NDAT1_ND26_Pos)                     /*!< 0x04000000 */
#define FDCAN_NDAT1_ND26                          FDCAN_NDAT1_ND26_Msk                              /*!< New Data26 */
#define FDCAN_NDAT1_ND27_Pos                      (27U)
#define FDCAN_NDAT1_ND27_Msk                      (0x1UL<<FDCAN_NDAT1_ND27_Pos)                     /*!< 0x08000000 */
#define FDCAN_NDAT1_ND27                          FDCAN_NDAT1_ND27_Msk                              /*!< New Data27 */
#define FDCAN_NDAT1_ND28_Pos                      (28U)
#define FDCAN_NDAT1_ND28_Msk                      (0x1UL<<FDCAN_NDAT1_ND28_Pos)                     /*!< 0x10000000 */
#define FDCAN_NDAT1_ND28                          FDCAN_NDAT1_ND28_Msk                              /*!< New Data28 */
#define FDCAN_NDAT1_ND29_Pos                      (29U)
#define FDCAN_NDAT1_ND29_Msk                      (0x1UL<<FDCAN_NDAT1_ND29_Pos)                     /*!< 0x20000000 */
#define FDCAN_NDAT1_ND29                          FDCAN_NDAT1_ND29_Msk                              /*!< New Data29 */
#define FDCAN_NDAT1_ND30_Pos                      (30U)
#define FDCAN_NDAT1_ND30_Msk                      (0x1UL<<FDCAN_NDAT1_ND30_Pos)                     /*!< 0x40000000 */
#define FDCAN_NDAT1_ND30                          FDCAN_NDAT1_ND30_Msk                              /*!< New Data30 */
#define FDCAN_NDAT1_ND31_Pos                      (31U)
#define FDCAN_NDAT1_ND31_Msk                      (0x1UL<<FDCAN_NDAT1_ND31_Pos)                     /*!< 0x80000000 */
#define FDCAN_NDAT1_ND31                          FDCAN_NDAT1_ND31_Msk                              /*!< New Data31 */

/********************************* Bit definition for FDCAN_NDAT2 register ******************************************/
#define FDCAN_NDAT2_ND32_Pos                      (0U)
#define FDCAN_NDAT2_ND32_Msk                      (0x1UL<<FDCAN_NDAT2_ND32_Pos)                     /*!< 0x00000001 */
#define FDCAN_NDAT2_ND32                          FDCAN_NDAT2_ND32_Msk                              /*!< New Data32 */
#define FDCAN_NDAT2_ND33_Pos                      (1U)
#define FDCAN_NDAT2_ND33_Msk                      (0x1UL<<FDCAN_NDAT2_ND33_Pos)                     /*!< 0x00000002 */
#define FDCAN_NDAT2_ND33                          FDCAN_NDAT2_ND33_Msk                              /*!< New Data33 */
#define FDCAN_NDAT2_ND34_Pos                      (2U)
#define FDCAN_NDAT2_ND34_Msk                      (0x1UL<<FDCAN_NDAT2_ND34_Pos)                     /*!< 0x00000004 */
#define FDCAN_NDAT2_ND34                          FDCAN_NDAT2_ND34_Msk                              /*!< New Data34 */
#define FDCAN_NDAT2_ND35_Pos                      (3U)
#define FDCAN_NDAT2_ND35_Msk                      (0x1UL<<FDCAN_NDAT2_ND35_Pos)                     /*!< 0x00000008 */
#define FDCAN_NDAT2_ND35                          FDCAN_NDAT2_ND35_Msk                              /*!< New Data35 */
#define FDCAN_NDAT2_ND36_Pos                      (4U)
#define FDCAN_NDAT2_ND36_Msk                      (0x1UL<<FDCAN_NDAT2_ND36_Pos)                     /*!< 0x00000010 */
#define FDCAN_NDAT2_ND36                          FDCAN_NDAT2_ND36_Msk                              /*!< New Data36 */
#define FDCAN_NDAT2_ND37_Pos                      (5U)
#define FDCAN_NDAT2_ND37_Msk                      (0x1UL<<FDCAN_NDAT2_ND37_Pos)                     /*!< 0x00000020 */
#define FDCAN_NDAT2_ND37                          FDCAN_NDAT2_ND37_Msk                              /*!< New Data37 */
#define FDCAN_NDAT2_ND38_Pos                      (6U)
#define FDCAN_NDAT2_ND38_Msk                      (0x1UL<<FDCAN_NDAT2_ND38_Pos)                     /*!< 0x00000040 */
#define FDCAN_NDAT2_ND38                          FDCAN_NDAT2_ND38_Msk                              /*!< New Data38 */
#define FDCAN_NDAT2_ND39_Pos                      (7U)
#define FDCAN_NDAT2_ND39_Msk                      (0x1UL<<FDCAN_NDAT2_ND39_Pos)                     /*!< 0x00000080 */
#define FDCAN_NDAT2_ND39                          FDCAN_NDAT2_ND39_Msk                              /*!< New Data39 */
#define FDCAN_NDAT2_ND40_Pos                      (8U)
#define FDCAN_NDAT2_ND40_Msk                      (0x1UL<<FDCAN_NDAT2_ND40_Pos)                     /*!< 0x00000100 */
#define FDCAN_NDAT2_ND40                          FDCAN_NDAT2_ND40_Msk                              /*!< New Data40 */
#define FDCAN_NDAT2_ND41_Pos                      (9U)
#define FDCAN_NDAT2_ND41_Msk                      (0x1UL<<FDCAN_NDAT2_ND41_Pos)                     /*!< 0x00000200 */
#define FDCAN_NDAT2_ND41                          FDCAN_NDAT2_ND41_Msk                              /*!< New Data41 */
#define FDCAN_NDAT2_ND42_Pos                      (10U)
#define FDCAN_NDAT2_ND42_Msk                      (0x1UL<<FDCAN_NDAT2_ND42_Pos)                     /*!< 0x00000400 */
#define FDCAN_NDAT2_ND42                          FDCAN_NDAT2_ND42_Msk                              /*!< New Data42 */
#define FDCAN_NDAT2_ND43_Pos                      (11U)
#define FDCAN_NDAT2_ND43_Msk                      (0x1UL<<FDCAN_NDAT2_ND43_Pos)                     /*!< 0x00000800 */
#define FDCAN_NDAT2_ND43                          FDCAN_NDAT2_ND43_Msk                              /*!< New Data43 */
#define FDCAN_NDAT2_ND44_Pos                      (12U)
#define FDCAN_NDAT2_ND44_Msk                      (0x1UL<<FDCAN_NDAT2_ND44_Pos)                     /*!< 0x00001000 */
#define FDCAN_NDAT2_ND44                          FDCAN_NDAT2_ND44_Msk                              /*!< New Data44 */
#define FDCAN_NDAT2_ND45_Pos                      (13U)
#define FDCAN_NDAT2_ND45_Msk                      (0x1UL<<FDCAN_NDAT2_ND45_Pos)                     /*!< 0x00002000 */
#define FDCAN_NDAT2_ND45                          FDCAN_NDAT2_ND45_Msk                              /*!< New Data45 */
#define FDCAN_NDAT2_ND46_Pos                      (14U)
#define FDCAN_NDAT2_ND46_Msk                      (0x1UL<<FDCAN_NDAT2_ND46_Pos)                     /*!< 0x00004000 */
#define FDCAN_NDAT2_ND46                          FDCAN_NDAT2_ND46_Msk                              /*!< New Data46 */
#define FDCAN_NDAT2_ND47_Pos                      (15U)
#define FDCAN_NDAT2_ND47_Msk                      (0x1UL<<FDCAN_NDAT2_ND47_Pos)                     /*!< 0x00008000 */
#define FDCAN_NDAT2_ND47                          FDCAN_NDAT2_ND47_Msk                              /*!< New Data47 */
#define FDCAN_NDAT2_ND48_Pos                      (16U)
#define FDCAN_NDAT2_ND48_Msk                      (0x1UL<<FDCAN_NDAT2_ND48_Pos)                     /*!< 0x00010000 */
#define FDCAN_NDAT2_ND48                          FDCAN_NDAT2_ND48_Msk                              /*!< New Data48 */
#define FDCAN_NDAT2_ND49_Pos                      (17U)
#define FDCAN_NDAT2_ND49_Msk                      (0x1UL<<FDCAN_NDAT2_ND49_Pos)                     /*!< 0x00020000 */
#define FDCAN_NDAT2_ND49                          FDCAN_NDAT2_ND49_Msk                              /*!< New Data49 */
#define FDCAN_NDAT2_ND50_Pos                      (18U)
#define FDCAN_NDAT2_ND50_Msk                      (0x1UL<<FDCAN_NDAT2_ND50_Pos)                     /*!< 0x00040000 */
#define FDCAN_NDAT2_ND50                          FDCAN_NDAT2_ND50_Msk                              /*!< New Data50 */
#define FDCAN_NDAT2_ND51_Pos                      (19U)
#define FDCAN_NDAT2_ND51_Msk                      (0x1UL<<FDCAN_NDAT2_ND51_Pos)                     /*!< 0x00080000 */
#define FDCAN_NDAT2_ND51                          FDCAN_NDAT2_ND51_Msk                              /*!< New Data51 */
#define FDCAN_NDAT2_ND52_Pos                      (20U)
#define FDCAN_NDAT2_ND52_Msk                      (0x1UL<<FDCAN_NDAT2_ND52_Pos)                     /*!< 0x00100000 */
#define FDCAN_NDAT2_ND52                          FDCAN_NDAT2_ND52_Msk                              /*!< New Data52 */
#define FDCAN_NDAT2_ND53_Pos                      (21U)
#define FDCAN_NDAT2_ND53_Msk                      (0x1UL<<FDCAN_NDAT2_ND53_Pos)                     /*!< 0x00200000 */
#define FDCAN_NDAT2_ND53                          FDCAN_NDAT2_ND53_Msk                              /*!< New Data53 */
#define FDCAN_NDAT2_ND54_Pos                      (22U)
#define FDCAN_NDAT2_ND54_Msk                      (0x1UL<<FDCAN_NDAT2_ND54_Pos)                     /*!< 0x00400000 */
#define FDCAN_NDAT2_ND54                          FDCAN_NDAT2_ND54_Msk                              /*!< New Data54 */
#define FDCAN_NDAT2_ND55_Pos                      (23U)
#define FDCAN_NDAT2_ND55_Msk                      (0x1UL<<FDCAN_NDAT2_ND55_Pos)                     /*!< 0x00800000 */
#define FDCAN_NDAT2_ND55                          FDCAN_NDAT2_ND55_Msk                              /*!< New Data55 */
#define FDCAN_NDAT2_ND56_Pos                      (24U)
#define FDCAN_NDAT2_ND56_Msk                      (0x1UL<<FDCAN_NDAT2_ND56_Pos)                     /*!< 0x01000000 */
#define FDCAN_NDAT2_ND56                          FDCAN_NDAT2_ND56_Msk                              /*!< New Data56 */
#define FDCAN_NDAT2_ND57_Pos                      (25U)
#define FDCAN_NDAT2_ND57_Msk                      (0x1UL<<FDCAN_NDAT2_ND57_Pos)                     /*!< 0x02000000 */
#define FDCAN_NDAT2_ND57                          FDCAN_NDAT2_ND57_Msk                              /*!< New Data57 */
#define FDCAN_NDAT2_ND58_Pos                      (26U)
#define FDCAN_NDAT2_ND58_Msk                      (0x1UL<<FDCAN_NDAT2_ND58_Pos)                     /*!< 0x04000000 */
#define FDCAN_NDAT2_ND58                          FDCAN_NDAT2_ND58_Msk                              /*!< New Data58 */
#define FDCAN_NDAT2_ND59_Pos                      (27U)
#define FDCAN_NDAT2_ND59_Msk                      (0x1UL<<FDCAN_NDAT2_ND59_Pos)                     /*!< 0x08000000 */
#define FDCAN_NDAT2_ND59                          FDCAN_NDAT2_ND59_Msk                              /*!< New Data59 */
#define FDCAN_NDAT2_ND60_Pos                      (28U)
#define FDCAN_NDAT2_ND60_Msk                      (0x1UL<<FDCAN_NDAT2_ND60_Pos)                     /*!< 0x10000000 */
#define FDCAN_NDAT2_ND60                          FDCAN_NDAT2_ND60_Msk                              /*!< New Data60 */
#define FDCAN_NDAT2_ND61_Pos                      (29U)
#define FDCAN_NDAT2_ND61_Msk                      (0x1UL<<FDCAN_NDAT2_ND61_Pos)                     /*!< 0x20000000 */
#define FDCAN_NDAT2_ND61                          FDCAN_NDAT2_ND61_Msk                              /*!< New Data61 */
#define FDCAN_NDAT2_ND62_Pos                      (30U)
#define FDCAN_NDAT2_ND62_Msk                      (0x1UL<<FDCAN_NDAT2_ND62_Pos)                     /*!< 0x40000000 */
#define FDCAN_NDAT2_ND62                          FDCAN_NDAT2_ND62_Msk                              /*!< New Data62 */
#define FDCAN_NDAT2_ND63_Pos                      (31U)
#define FDCAN_NDAT2_ND63_Msk                      (0x1UL<<FDCAN_NDAT2_ND63_Pos)                     /*!< 0x80000000 */
#define FDCAN_NDAT2_ND63                          FDCAN_NDAT2_ND63_Msk                              /*!< New Data63 */

/********************************* Bit definition for FDCAN_RXF0C register ******************************************/
#define FDCAN_RXF0C_F0SA_Pos                      (2U)
#define FDCAN_RXF0C_F0SA_Msk                      (0x3FFFUL<<FDCAN_RXF0C_F0SA_Pos)                  /*!< 0x0000FFFC */
#define FDCAN_RXF0C_F0SA                          FDCAN_RXF0C_F0SA_Msk                              /*!< Rx FIFO 0 Start Address */
#define FDCAN_RXF0C_F0S_Pos                       (16U)
#define FDCAN_RXF0C_F0S_Msk                       (0x7FUL<<FDCAN_RXF0C_F0S_Pos)                     /*!< 0x007F0000 */
#define FDCAN_RXF0C_F0S                           FDCAN_RXF0C_F0S_Msk                               /*!< Rx FIFO 0 Size */
#define FDCAN_RXF0C_F0WM_Pos                      (24U)
#define FDCAN_RXF0C_F0WM_Msk                      (0x7FUL<<FDCAN_RXF0C_F0WM_Pos)                    /*!< 0x7F000000 */
#define FDCAN_RXF0C_F0WM                          FDCAN_RXF0C_F0WM_Msk                              /*!< Rx FIFO 0 Watermark */
#define FDCAN_RXF0C_F0OM_Pos                      (31U)
#define FDCAN_RXF0C_F0OM_Msk                      (0x1UL<<FDCAN_RXF0C_F0OM_Pos)                     /*!< 0x80000000 */
#define FDCAN_RXF0C_F0OM                          FDCAN_RXF0C_F0OM_Msk                              /*!< FIFO 0 Operation Mode */

/********************************* Bit definition for FDCAN_RXF0S register ******************************************/
#define FDCAN_RXF0S_F0FL_Pos                      (0U)
#define FDCAN_RXF0S_F0FL_Msk                      (0x7FUL<<FDCAN_RXF0S_F0FL_Pos)                    /*!< 0x0000007F */
#define FDCAN_RXF0S_F0FL                          FDCAN_RXF0S_F0FL_Msk                              /*!< Rx FIFO 0 Fill Level */
#define FDCAN_RXF0S_F0GI_Pos                      (8U)
#define FDCAN_RXF0S_F0GI_Msk                      (0x3FUL<<FDCAN_RXF0S_F0GI_Pos)                    /*!< 0x00003F00 */
#define FDCAN_RXF0S_F0GI                          FDCAN_RXF0S_F0GI_Msk                              /*!< Rx FIFO 0 Get Index */
#define FDCAN_RXF0S_F0GI_0                        (0x1UL<<FDCAN_RXF0S_F0GI_Pos)                     /*!< 0x00000100 */
#define FDCAN_RXF0S_F0GI_1                        (0x2UL<<FDCAN_RXF0S_F0GI_Pos)                     /*!< 0x00000200 */
#define FDCAN_RXF0S_F0GI_2                        (0x4UL<<FDCAN_RXF0S_F0GI_Pos)                     /*!< 0x00000400 */
#define FDCAN_RXF0S_F0GI_3                        (0x8UL<<FDCAN_RXF0S_F0GI_Pos)                     /*!< 0x00000800 */
#define FDCAN_RXF0S_F0GI_4                        (0x10UL<<FDCAN_RXF0S_F0GI_Pos)                    /*!< 0x00001000 */
#define FDCAN_RXF0S_F0GI_5                        (0x20UL<<FDCAN_RXF0S_F0GI_Pos)                    /*!< 0x00002000 */
#define FDCAN_RXF0S_F0PI_Pos                      (16U)
#define FDCAN_RXF0S_F0PI_Msk                      (0x3FUL<<FDCAN_RXF0S_F0PI_Pos)                    /*!< 0x003F0000 */
#define FDCAN_RXF0S_F0PI                          FDCAN_RXF0S_F0PI_Msk                              /*!< Rx FIFO 0 Put Index */
#define FDCAN_RXF0S_F0PI_0                        (0x1UL<<FDCAN_RXF0S_F0PI_Pos)                     /*!< 0x00010000 */
#define FDCAN_RXF0S_F0PI_1                        (0x2UL<<FDCAN_RXF0S_F0PI_Pos)                     /*!< 0x00020000 */
#define FDCAN_RXF0S_F0PI_2                        (0x4UL<<FDCAN_RXF0S_F0PI_Pos)                     /*!< 0x00040000 */
#define FDCAN_RXF0S_F0PI_3                        (0x8UL<<FDCAN_RXF0S_F0PI_Pos)                     /*!< 0x00080000 */
#define FDCAN_RXF0S_F0PI_4                        (0x10UL<<FDCAN_RXF0S_F0PI_Pos)                    /*!< 0x00100000 */
#define FDCAN_RXF0S_F0PI_5                        (0x20UL<<FDCAN_RXF0S_F0PI_Pos)                    /*!< 0x00200000 */
#define FDCAN_RXF0S_F0F_Pos                       (24U)
#define FDCAN_RXF0S_F0F_Msk                       (0x1UL<<FDCAN_RXF0S_F0F_Pos)                      /*!< 0x01000000 */
#define FDCAN_RXF0S_F0F                           FDCAN_RXF0S_F0F_Msk                               /*!< Rx FIFO 0 Full */
#define FDCAN_RXF0S_RF0L_Pos                      (25U)
#define FDCAN_RXF0S_RF0L_Msk                      (0x1UL<<FDCAN_RXF0S_RF0L_Pos)                     /*!< 0x02000000 */
#define FDCAN_RXF0S_RF0L                          FDCAN_RXF0S_RF0L_Msk                              /*!< Rx FIFO 0 Message Lost */

/********************************* Bit definition for FDCAN_RXF0A register ******************************************/
#define FDCAN_RXF0A_F0AI_Pos                      (0U)
#define FDCAN_RXF0A_F0AI_Msk                      (0x3FUL<<FDCAN_RXF0A_F0AI_Pos)                    /*!< 0x0000003F */
#define FDCAN_RXF0A_F0AI                          FDCAN_RXF0A_F0AI_Msk                              /*!< Rx FIFO 0 Acknowledge Index */
#define FDCAN_RXF0A_F0AI_0                        (0x1UL<<FDCAN_RXF0A_F0AI_Pos)                     /*!< 0x00000001 */
#define FDCAN_RXF0A_F0AI_1                        (0x2UL<<FDCAN_RXF0A_F0AI_Pos)                     /*!< 0x00000002 */
#define FDCAN_RXF0A_F0AI_2                        (0x4UL<<FDCAN_RXF0A_F0AI_Pos)                     /*!< 0x00000004 */
#define FDCAN_RXF0A_F0AI_3                        (0x8UL<<FDCAN_RXF0A_F0AI_Pos)                     /*!< 0x00000008 */
#define FDCAN_RXF0A_F0AI_4                        (0x10UL<<FDCAN_RXF0A_F0AI_Pos)                    /*!< 0x00000010 */
#define FDCAN_RXF0A_F0AI_5                        (0x20UL<<FDCAN_RXF0A_F0AI_Pos)                    /*!< 0x00000020 */

/********************************* Bit definition for FDCAN_RXBC register *******************************************/
#define FDCAN_RXBC_RBSA_Pos                       (2U)
#define FDCAN_RXBC_RBSA_Msk                       (0x3FFFUL<<FDCAN_RXBC_RBSA_Pos)                   /*!< 0x0000FFFC */
#define FDCAN_RXBC_RBSA                           FDCAN_RXBC_RBSA_Msk                               /*!< Rx Buffer Start Address */

/********************************* Bit definition for FDCAN_RXF1C register ******************************************/
#define FDCAN_RXF1C_F1SA_Pos                      (2U)
#define FDCAN_RXF1C_F1SA_Msk                      (0xFUL<<FDCAN_RXF1C_F1SA_Pos)                     /*!< 0x0000003C */
#define FDCAN_RXF1C_F1SA                          FDCAN_RXF1C_F1SA_Msk                              /*!< Rx FIFO 1 Start Address */
#define FDCAN_RXF1C_F1SA_0                        (0x1UL<<FDCAN_RXF1C_F1SA_Pos)                     /*!< 0x00000004 */
#define FDCAN_RXF1C_F1SA_1                        (0x2UL<<FDCAN_RXF1C_F1SA_Pos)                     /*!< 0x00000008 */
#define FDCAN_RXF1C_F1SA_2                        (0x4UL<<FDCAN_RXF1C_F1SA_Pos)                     /*!< 0x00000010 */
#define FDCAN_RXF1C_F1SA_3                        (0x8UL<<FDCAN_RXF1C_F1SA_Pos)                     /*!< 0x00000020 */
#define FDCAN_RXF1C_F1S_Pos                       (16U)
#define FDCAN_RXF1C_F1S_Msk                       (0x7FUL<<FDCAN_RXF1C_F1S_Pos)                     /*!< 0x007F0000 */
#define FDCAN_RXF1C_F1S                           FDCAN_RXF1C_F1S_Msk                               /*!< Rx FIFO 1 Size */
#define FDCAN_RXF1C_F1WM_Pos                      (24U)
#define FDCAN_RXF1C_F1WM_Msk                      (0x7FUL<<FDCAN_RXF1C_F1WM_Pos)                    /*!< 0x7F000000 */
#define FDCAN_RXF1C_F1WM                          FDCAN_RXF1C_F1WM_Msk                              /*!< Rx FIFO 1 Watermark */
#define FDCAN_RXF1C_F1OM_Pos                      (31U)
#define FDCAN_RXF1C_F1OM_Msk                      (0x1UL<<FDCAN_RXF1C_F1OM_Pos)                     /*!< 0x80000000 */
#define FDCAN_RXF1C_F1OM                          FDCAN_RXF1C_F1OM_Msk                              /*!< FIFO 1 Operation Mode */

/********************************* Bit definition for FDCAN_RXF1S register ******************************************/
#define FDCAN_RXF1S_F1FL_Pos                      (0U)
#define FDCAN_RXF1S_F1FL_Msk                      (0x7FUL<<FDCAN_RXF1S_F1FL_Pos)                    /*!< 0x0000007F */
#define FDCAN_RXF1S_F1FL                          FDCAN_RXF1S_F1FL_Msk                              /*!< Rx FIFO 1 Fill Level */
#define FDCAN_RXF1S_F1GI_Pos                      (8U)
#define FDCAN_RXF1S_F1GI_Msk                      (0x3FUL<<FDCAN_RXF1S_F1GI_Pos)                    /*!< 0x00003F00 */
#define FDCAN_RXF1S_F1GI                          FDCAN_RXF1S_F1GI_Msk                              /*!< Rx FIFO 1 Get Index */
#define FDCAN_RXF1S_F1GI_0                        (0x1UL<<FDCAN_RXF1S_F1GI_Pos)                     /*!< 0x00000100 */
#define FDCAN_RXF1S_F1GI_1                        (0x2UL<<FDCAN_RXF1S_F1GI_Pos)                     /*!< 0x00000200 */
#define FDCAN_RXF1S_F1GI_2                        (0x4UL<<FDCAN_RXF1S_F1GI_Pos)                     /*!< 0x00000400 */
#define FDCAN_RXF1S_F1GI_3                        (0x8UL<<FDCAN_RXF1S_F1GI_Pos)                     /*!< 0x00000800 */
#define FDCAN_RXF1S_F1GI_4                        (0x10UL<<FDCAN_RXF1S_F1GI_Pos)                    /*!< 0x00001000 */
#define FDCAN_RXF1S_F1GI_5                        (0x20UL<<FDCAN_RXF1S_F1GI_Pos)                    /*!< 0x00002000 */
#define FDCAN_RXF1S_F1PI_Pos                      (16U)
#define FDCAN_RXF1S_F1PI_Msk                      (0x3FUL<<FDCAN_RXF1S_F1PI_Pos)                    /*!< 0x003F0000 */
#define FDCAN_RXF1S_F1PI                          FDCAN_RXF1S_F1PI_Msk                              /*!< Rx FIFO 1 Put Index */
#define FDCAN_RXF1S_F1PI_0                        (0x1UL<<FDCAN_RXF1S_F1PI_Pos)                     /*!< 0x00010000 */
#define FDCAN_RXF1S_F1PI_1                        (0x2UL<<FDCAN_RXF1S_F1PI_Pos)                     /*!< 0x00020000 */
#define FDCAN_RXF1S_F1PI_2                        (0x4UL<<FDCAN_RXF1S_F1PI_Pos)                     /*!< 0x00040000 */
#define FDCAN_RXF1S_F1PI_3                        (0x8UL<<FDCAN_RXF1S_F1PI_Pos)                     /*!< 0x00080000 */
#define FDCAN_RXF1S_F1PI_4                        (0x10UL<<FDCAN_RXF1S_F1PI_Pos)                    /*!< 0x00100000 */
#define FDCAN_RXF1S_F1PI_5                        (0x20UL<<FDCAN_RXF1S_F1PI_Pos)                    /*!< 0x00200000 */
#define FDCAN_RXF1S_F1F_Pos                       (24U)
#define FDCAN_RXF1S_F1F_Msk                       (0x1UL<<FDCAN_RXF1S_F1F_Pos)                      /*!< 0x01000000 */
#define FDCAN_RXF1S_F1F                           FDCAN_RXF1S_F1F_Msk                               /*!< Rx FIFO 1 Full */
#define FDCAN_RXF1S_RF1L_Pos                      (25U)
#define FDCAN_RXF1S_RF1L_Msk                      (0x1UL<<FDCAN_RXF1S_RF1L_Pos)                     /*!< 0x02000000 */
#define FDCAN_RXF1S_RF1L                          FDCAN_RXF1S_RF1L_Msk                              /*!< Rx FIFO 1 Message Lost */
#define FDCAN_RXF1S_DMS_Pos                       (30U)
#define FDCAN_RXF1S_DMS_Msk                       (0x3UL<<FDCAN_RXF1S_DMS_Pos)                      /*!< 0xC0000000 */
#define FDCAN_RXF1S_DMS                           FDCAN_RXF1S_DMS_Msk                               /*!< Debug Message Status */
#define FDCAN_RXF1S_DMS_0                         (0x1UL<<FDCAN_RXF1S_DMS_Pos)                      /*!< 0x40000000 */
#define FDCAN_RXF1S_DMS_1                         (0x2UL<<FDCAN_RXF1S_DMS_Pos)                      /*!< 0x80000000 */

/********************************* Bit definition for FDCAN_RXF1A register ******************************************/
#define FDCAN_RXF1A_F1AI_Pos                      (0U)
#define FDCAN_RXF1A_F1AI_Msk                      (0x3FUL<<FDCAN_RXF1A_F1AI_Pos)                    /*!< 0x0000003F */
#define FDCAN_RXF1A_F1AI                          FDCAN_RXF1A_F1AI_Msk                              /*!< Rx FIFO 1 Acknowledge Index */
#define FDCAN_RXF1A_F1AI_0                        (0x1UL<<FDCAN_RXF1A_F1AI_Pos)                     /*!< 0x00000001 */
#define FDCAN_RXF1A_F1AI_1                        (0x2UL<<FDCAN_RXF1A_F1AI_Pos)                     /*!< 0x00000002 */
#define FDCAN_RXF1A_F1AI_2                        (0x4UL<<FDCAN_RXF1A_F1AI_Pos)                     /*!< 0x00000004 */
#define FDCAN_RXF1A_F1AI_3                        (0x8UL<<FDCAN_RXF1A_F1AI_Pos)                     /*!< 0x00000008 */
#define FDCAN_RXF1A_F1AI_4                        (0x10UL<<FDCAN_RXF1A_F1AI_Pos)                    /*!< 0x00000010 */
#define FDCAN_RXF1A_F1AI_5                        (0x20UL<<FDCAN_RXF1A_F1AI_Pos)                    /*!< 0x00000020 */

/********************************* Bit definition for FDCAN_RXESC register ******************************************/
#define FDCAN_RXESC_F0DS_Pos                      (0U)
#define FDCAN_RXESC_F0DS_Msk                      (0x7UL<<FDCAN_RXESC_F0DS_Pos)                     /*!< 0x00000007 */
#define FDCAN_RXESC_F0DS                          FDCAN_RXESC_F0DS_Msk                              /*!< Rx FIFO 0 Data Field Size */
#define FDCAN_RXESC_F0DS_0                        (0x1UL<<FDCAN_RXESC_F0DS_Pos)                     /*!< 0x00000001 */
#define FDCAN_RXESC_F0DS_1                        (0x2UL<<FDCAN_RXESC_F0DS_Pos)                     /*!< 0x00000002 */
#define FDCAN_RXESC_F0DS_2                        (0x4UL<<FDCAN_RXESC_F0DS_Pos)                     /*!< 0x00000004 */
#define FDCAN_RXESC_F1DS_Pos                      (4U)
#define FDCAN_RXESC_F1DS_Msk                      (0x7UL<<FDCAN_RXESC_F1DS_Pos)                     /*!< 0x00000070 */
#define FDCAN_RXESC_F1DS                          FDCAN_RXESC_F1DS_Msk                              /*!< Rx FIFO 1 Data Field Size */
#define FDCAN_RXESC_F1DS_0                        (0x1UL<<FDCAN_RXESC_F1DS_Pos)                     /*!< 0x00000010 */
#define FDCAN_RXESC_F1DS_1                        (0x2UL<<FDCAN_RXESC_F1DS_Pos)                     /*!< 0x00000020 */
#define FDCAN_RXESC_F1DS_2                        (0x4UL<<FDCAN_RXESC_F1DS_Pos)                     /*!< 0x00000040 */
#define FDCAN_RXESC_RBDS_Pos                      (8U)
#define FDCAN_RXESC_RBDS_Msk                      (0x7UL<<FDCAN_RXESC_RBDS_Pos)                     /*!< 0x00000700 */
#define FDCAN_RXESC_RBDS                          FDCAN_RXESC_RBDS_Msk                              /*!< Rx Buffer Data Field Size */
#define FDCAN_RXESC_RBDS_0                        (0x1UL<<FDCAN_RXESC_RBDS_Pos)                     /*!< 0x00000100 */
#define FDCAN_RXESC_RBDS_1                        (0x2UL<<FDCAN_RXESC_RBDS_Pos)                     /*!< 0x00000200 */
#define FDCAN_RXESC_RBDS_2                        (0x4UL<<FDCAN_RXESC_RBDS_Pos)                     /*!< 0x00000400 */

/********************************* Bit definition for FDCAN_TXBC register *******************************************/
#define FDCAN_TXBC_TBSA_Pos                       (2U)
#define FDCAN_TXBC_TBSA_Msk                       (0x3FFFUL<<FDCAN_TXBC_TBSA_Pos)                   /*!< 0x0000FFFC */
#define FDCAN_TXBC_TBSA                           FDCAN_TXBC_TBSA_Msk                               /*!< Tx Buffers Start Address */
#define FDCAN_TXBC_NDTB_Pos                       (16U)
#define FDCAN_TXBC_NDTB_Msk                       (0x3FUL<<FDCAN_TXBC_NDTB_Pos)                     /*!< 0x003F0000 */
#define FDCAN_TXBC_NDTB                           FDCAN_TXBC_NDTB_Msk                               /*!< Number of Dedicated Transmit Buffers */
#define FDCAN_TXBC_NDTB_0                         (0x1UL<<FDCAN_TXBC_NDTB_Pos)                      /*!< 0x00010000 */
#define FDCAN_TXBC_NDTB_1                         (0x2UL<<FDCAN_TXBC_NDTB_Pos)                      /*!< 0x00020000 */
#define FDCAN_TXBC_NDTB_2                         (0x4UL<<FDCAN_TXBC_NDTB_Pos)                      /*!< 0x00040000 */
#define FDCAN_TXBC_NDTB_3                         (0x8UL<<FDCAN_TXBC_NDTB_Pos)                      /*!< 0x00080000 */
#define FDCAN_TXBC_NDTB_4                         (0x10UL<<FDCAN_TXBC_NDTB_Pos)                     /*!< 0x00100000 */
#define FDCAN_TXBC_NDTB_5                         (0x20UL<<FDCAN_TXBC_NDTB_Pos)                     /*!< 0x00200000 */
#define FDCAN_TXBC_TFQS_Pos                       (24U)
#define FDCAN_TXBC_TFQS_Msk                       (0x3FUL<<FDCAN_TXBC_TFQS_Pos)                     /*!< 0x3F000000 */
#define FDCAN_TXBC_TFQS                           FDCAN_TXBC_TFQS_Msk                               /*!< Transmit FIFO/Queue Size */
#define FDCAN_TXBC_TFQS_0                         (0x1UL<<FDCAN_TXBC_TFQS_Pos)                      /*!< 0x01000000 */
#define FDCAN_TXBC_TFQS_1                         (0x2UL<<FDCAN_TXBC_TFQS_Pos)                      /*!< 0x02000000 */
#define FDCAN_TXBC_TFQS_2                         (0x4UL<<FDCAN_TXBC_TFQS_Pos)                      /*!< 0x04000000 */
#define FDCAN_TXBC_TFQS_3                         (0x8UL<<FDCAN_TXBC_TFQS_Pos)                      /*!< 0x08000000 */
#define FDCAN_TXBC_TFQS_4                         (0x10UL<<FDCAN_TXBC_TFQS_Pos)                     /*!< 0x10000000 */
#define FDCAN_TXBC_TFQS_5                         (0x20UL<<FDCAN_TXBC_TFQS_Pos)                     /*!< 0x20000000 */
#define FDCAN_TXBC_TFQM_Pos                       (30U)
#define FDCAN_TXBC_TFQM_Msk                       (0x1UL<<FDCAN_TXBC_TFQM_Pos)                      /*!< 0x40000000 */
#define FDCAN_TXBC_TFQM                           FDCAN_TXBC_TFQM_Msk                               /*!< Tx FIFO/Queue Mode */

/********************************* Bit definition for FDCAN_TXFQS register ******************************************/
#define FDCAN_TXFQS_TFFL_Pos                      (0U)
#define FDCAN_TXFQS_TFFL_Msk                      (0x3FUL<<FDCAN_TXFQS_TFFL_Pos)                    /*!< 0x0000003F */
#define FDCAN_TXFQS_TFFL                          FDCAN_TXFQS_TFFL_Msk                              /*!< Tx FIFO Free Level */
#define FDCAN_TXFQS_TFFL_0                        (0x1UL<<FDCAN_TXFQS_TFFL_Pos)                     /*!< 0x00000001 */
#define FDCAN_TXFQS_TFFL_1                        (0x2UL<<FDCAN_TXFQS_TFFL_Pos)                     /*!< 0x00000002 */
#define FDCAN_TXFQS_TFFL_2                        (0x4UL<<FDCAN_TXFQS_TFFL_Pos)                     /*!< 0x00000004 */
#define FDCAN_TXFQS_TFFL_3                        (0x8UL<<FDCAN_TXFQS_TFFL_Pos)                     /*!< 0x00000008 */
#define FDCAN_TXFQS_TFFL_4                        (0x10UL<<FDCAN_TXFQS_TFFL_Pos)                    /*!< 0x00000010 */
#define FDCAN_TXFQS_TFFL_5                        (0x20UL<<FDCAN_TXFQS_TFFL_Pos)                    /*!< 0x00000020 */
#define FDCAN_TXFQS_TFGI_Pos                      (8U)
#define FDCAN_TXFQS_TFGI_Msk                      (0x1FUL<<FDCAN_TXFQS_TFGI_Pos)                    /*!< 0x00001F00 */
#define FDCAN_TXFQS_TFGI                          FDCAN_TXFQS_TFGI_Msk                              /*!< Tx FIFO Get Index */
#define FDCAN_TXFQS_TFGI_0                        (0x1UL<<FDCAN_TXFQS_TFGI_Pos)                     /*!< 0x00000100 */
#define FDCAN_TXFQS_TFGI_1                        (0x2UL<<FDCAN_TXFQS_TFGI_Pos)                     /*!< 0x00000200 */
#define FDCAN_TXFQS_TFGI_2                        (0x4UL<<FDCAN_TXFQS_TFGI_Pos)                     /*!< 0x00000400 */
#define FDCAN_TXFQS_TFGI_3                        (0x8UL<<FDCAN_TXFQS_TFGI_Pos)                     /*!< 0x00000800 */
#define FDCAN_TXFQS_TFGI_4                        (0x10UL<<FDCAN_TXFQS_TFGI_Pos)                    /*!< 0x00001000 */
#define FDCAN_TXFQS_TFQPI_Pos                     (16U)
#define FDCAN_TXFQS_TFQPI_Msk                     (0x1FUL<<FDCAN_TXFQS_TFQPI_Pos)                   /*!< 0x001F0000 */
#define FDCAN_TXFQS_TFQPI                         FDCAN_TXFQS_TFQPI_Msk                             /*!< Tx FIFO/Queue Put Index */
#define FDCAN_TXFQS_TFQPI_0                       (0x1UL<<FDCAN_TXFQS_TFQPI_Pos)                    /*!< 0x00010000 */
#define FDCAN_TXFQS_TFQPI_1                       (0x2UL<<FDCAN_TXFQS_TFQPI_Pos)                    /*!< 0x00020000 */
#define FDCAN_TXFQS_TFQPI_2                       (0x4UL<<FDCAN_TXFQS_TFQPI_Pos)                    /*!< 0x00040000 */
#define FDCAN_TXFQS_TFQPI_3                       (0x8UL<<FDCAN_TXFQS_TFQPI_Pos)                    /*!< 0x00080000 */
#define FDCAN_TXFQS_TFQPI_4                       (0x10UL<<FDCAN_TXFQS_TFQPI_Pos)                   /*!< 0x00100000 */
#define FDCAN_TXFQS_TFQF_Pos                      (21U)
#define FDCAN_TXFQS_TFQF_Msk                      (0x1UL<<FDCAN_TXFQS_TFQF_Pos)                     /*!< 0x00200000 */
#define FDCAN_TXFQS_TFQF                          FDCAN_TXFQS_TFQF_Msk                              /*!< Tx FIFO/Queue Full */

/********************************* Bit definition for FDCAN_TXESC register ******************************************/
#define FDCAN_TXESC_TBDS_Pos                      (0U)
#define FDCAN_TXESC_TBDS_Msk                      (0x7UL<<FDCAN_TXESC_TBDS_Pos)                     /*!< 0x00000007 */
#define FDCAN_TXESC_TBDS                          FDCAN_TXESC_TBDS_Msk                              /*!< Tx Buffer Data Field Size */
#define FDCAN_TXESC_TBDS_0                        (0x1UL<<FDCAN_TXESC_TBDS_Pos)                     /*!< 0x00000001 */
#define FDCAN_TXESC_TBDS_1                        (0x2UL<<FDCAN_TXESC_TBDS_Pos)                     /*!< 0x00000002 */
#define FDCAN_TXESC_TBDS_2                        (0x4UL<<FDCAN_TXESC_TBDS_Pos)                     /*!< 0x00000004 */

/********************************* Bit definition for FDCAN_TXBRP register ******************************************/
#define FDCAN_TXBRP_TRP0_Pos                      (0U)
#define FDCAN_TXBRP_TRP0_Msk                      (0x1UL<<FDCAN_TXBRP_TRP0_Pos)                     /*!< 0x00000001 */
#define FDCAN_TXBRP_TRP0                          FDCAN_TXBRP_TRP0_Msk                              /*!< Transmission Request Pending */
#define FDCAN_TXBRP_TRP1_Pos                      (1U)
#define FDCAN_TXBRP_TRP1_Msk                      (0x1UL<<FDCAN_TXBRP_TRP1_Pos)                     /*!< 0x00000002 */
#define FDCAN_TXBRP_TRP1                          FDCAN_TXBRP_TRP1_Msk                              /*!< Transmission Request Pending */
#define FDCAN_TXBRP_TRP2_Pos                      (2U)
#define FDCAN_TXBRP_TRP2_Msk                      (0x1UL<<FDCAN_TXBRP_TRP2_Pos)                     /*!< 0x00000004 */
#define FDCAN_TXBRP_TRP2                          FDCAN_TXBRP_TRP2_Msk                              /*!< Transmission Request Pending */
#define FDCAN_TXBRP_TRP3_Pos                      (3U)
#define FDCAN_TXBRP_TRP3_Msk                      (0x1UL<<FDCAN_TXBRP_TRP3_Pos)                     /*!< 0x00000008 */
#define FDCAN_TXBRP_TRP3                          FDCAN_TXBRP_TRP3_Msk                              /*!< Transmission Request Pending */
#define FDCAN_TXBRP_TRP4_Pos                      (4U)
#define FDCAN_TXBRP_TRP4_Msk                      (0x1UL<<FDCAN_TXBRP_TRP4_Pos)                     /*!< 0x00000010 */
#define FDCAN_TXBRP_TRP4                          FDCAN_TXBRP_TRP4_Msk                              /*!< Transmission Request Pending */
#define FDCAN_TXBRP_TRP5_Pos                      (5U)
#define FDCAN_TXBRP_TRP5_Msk                      (0x1UL<<FDCAN_TXBRP_TRP5_Pos)                     /*!< 0x00000020 */
#define FDCAN_TXBRP_TRP5                          FDCAN_TXBRP_TRP5_Msk                              /*!< Transmission Request Pending */
#define FDCAN_TXBRP_TRP6_Pos                      (6U)
#define FDCAN_TXBRP_TRP6_Msk                      (0x1UL<<FDCAN_TXBRP_TRP6_Pos)                     /*!< 0x00000040 */
#define FDCAN_TXBRP_TRP6                          FDCAN_TXBRP_TRP6_Msk                              /*!< Transmission Request Pending */
#define FDCAN_TXBRP_TRP7_Pos                      (7U)
#define FDCAN_TXBRP_TRP7_Msk                      (0x1UL<<FDCAN_TXBRP_TRP7_Pos)                     /*!< 0x00000080 */
#define FDCAN_TXBRP_TRP7                          FDCAN_TXBRP_TRP7_Msk                              /*!< Transmission Request Pending */
#define FDCAN_TXBRP_TRP8_Pos                      (8U)
#define FDCAN_TXBRP_TRP8_Msk                      (0x1UL<<FDCAN_TXBRP_TRP8_Pos)                     /*!< 0x00000100 */
#define FDCAN_TXBRP_TRP8                          FDCAN_TXBRP_TRP8_Msk                              /*!< Transmission Request Pending */
#define FDCAN_TXBRP_TRP9_Pos                      (9U)
#define FDCAN_TXBRP_TRP9_Msk                      (0x1UL<<FDCAN_TXBRP_TRP9_Pos)                     /*!< 0x00000200 */
#define FDCAN_TXBRP_TRP9                          FDCAN_TXBRP_TRP9_Msk                              /*!< Transmission Request Pending */
#define FDCAN_TXBRP_TRP10_Pos                     (10U)
#define FDCAN_TXBRP_TRP10_Msk                     (0x1UL<<FDCAN_TXBRP_TRP10_Pos)                    /*!< 0x00000400 */
#define FDCAN_TXBRP_TRP10                         FDCAN_TXBRP_TRP10_Msk                             /*!< Transmission Request Pending */
#define FDCAN_TXBRP_TRP11_Pos                     (11U)
#define FDCAN_TXBRP_TRP11_Msk                     (0x1UL<<FDCAN_TXBRP_TRP11_Pos)                    /*!< 0x00000800 */
#define FDCAN_TXBRP_TRP11                         FDCAN_TXBRP_TRP11_Msk                             /*!< Transmission Request Pending */
#define FDCAN_TXBRP_TRP12_Pos                     (12U)
#define FDCAN_TXBRP_TRP12_Msk                     (0x1UL<<FDCAN_TXBRP_TRP12_Pos)                    /*!< 0x00001000 */
#define FDCAN_TXBRP_TRP12                         FDCAN_TXBRP_TRP12_Msk                             /*!< Transmission Request Pending */
#define FDCAN_TXBRP_TRP13_Pos                     (13U)
#define FDCAN_TXBRP_TRP13_Msk                     (0x1UL<<FDCAN_TXBRP_TRP13_Pos)                    /*!< 0x00002000 */
#define FDCAN_TXBRP_TRP13                         FDCAN_TXBRP_TRP13_Msk                             /*!< Transmission Request Pending */
#define FDCAN_TXBRP_TRP14_Pos                     (14U)
#define FDCAN_TXBRP_TRP14_Msk                     (0x1UL<<FDCAN_TXBRP_TRP14_Pos)                    /*!< 0x00004000 */
#define FDCAN_TXBRP_TRP14                         FDCAN_TXBRP_TRP14_Msk                             /*!< Transmission Request Pending */
#define FDCAN_TXBRP_TRP15_Pos                     (15U)
#define FDCAN_TXBRP_TRP15_Msk                     (0x1UL<<FDCAN_TXBRP_TRP15_Pos)                    /*!< 0x00008000 */
#define FDCAN_TXBRP_TRP15                         FDCAN_TXBRP_TRP15_Msk                             /*!< Transmission Request Pending */
#define FDCAN_TXBRP_TRP16_Pos                     (16U)
#define FDCAN_TXBRP_TRP16_Msk                     (0x1UL<<FDCAN_TXBRP_TRP16_Pos)                    /*!< 0x00010000 */
#define FDCAN_TXBRP_TRP16                         FDCAN_TXBRP_TRP16_Msk                             /*!< Transmission Request Pending */
#define FDCAN_TXBRP_TRP17_Pos                     (17U)
#define FDCAN_TXBRP_TRP17_Msk                     (0x1UL<<FDCAN_TXBRP_TRP17_Pos)                    /*!< 0x00020000 */
#define FDCAN_TXBRP_TRP17                         FDCAN_TXBRP_TRP17_Msk                             /*!< Transmission Request Pending */
#define FDCAN_TXBRP_TRP18_Pos                     (18U)
#define FDCAN_TXBRP_TRP18_Msk                     (0x1UL<<FDCAN_TXBRP_TRP18_Pos)                    /*!< 0x00040000 */
#define FDCAN_TXBRP_TRP18                         FDCAN_TXBRP_TRP18_Msk                             /*!< Transmission Request Pending */
#define FDCAN_TXBRP_TRP19_Pos                     (19U)
#define FDCAN_TXBRP_TRP19_Msk                     (0x1UL<<FDCAN_TXBRP_TRP19_Pos)                    /*!< 0x00080000 */
#define FDCAN_TXBRP_TRP19                         FDCAN_TXBRP_TRP19_Msk                             /*!< Transmission Request Pending */
#define FDCAN_TXBRP_TRP20_Pos                     (20U)
#define FDCAN_TXBRP_TRP20_Msk                     (0x1UL<<FDCAN_TXBRP_TRP20_Pos)                    /*!< 0x00100000 */
#define FDCAN_TXBRP_TRP20                         FDCAN_TXBRP_TRP20_Msk                             /*!< Transmission Request Pending */
#define FDCAN_TXBRP_TRP21_Pos                     (21U)
#define FDCAN_TXBRP_TRP21_Msk                     (0x1UL<<FDCAN_TXBRP_TRP21_Pos)                    /*!< 0x00200000 */
#define FDCAN_TXBRP_TRP21                         FDCAN_TXBRP_TRP21_Msk                             /*!< Transmission Request Pending */
#define FDCAN_TXBRP_TRP22_Pos                     (22U)
#define FDCAN_TXBRP_TRP22_Msk                     (0x1UL<<FDCAN_TXBRP_TRP22_Pos)                    /*!< 0x00400000 */
#define FDCAN_TXBRP_TRP22                         FDCAN_TXBRP_TRP22_Msk                             /*!< Transmission Request Pending */
#define FDCAN_TXBRP_TRP23_Pos                     (23U)
#define FDCAN_TXBRP_TRP23_Msk                     (0x1UL<<FDCAN_TXBRP_TRP23_Pos)                    /*!< 0x00800000 */
#define FDCAN_TXBRP_TRP23                         FDCAN_TXBRP_TRP23_Msk                             /*!< Transmission Request Pending */
#define FDCAN_TXBRP_TRP24_Pos                     (24U)
#define FDCAN_TXBRP_TRP24_Msk                     (0x1UL<<FDCAN_TXBRP_TRP24_Pos)                    /*!< 0x01000000 */
#define FDCAN_TXBRP_TRP24                         FDCAN_TXBRP_TRP24_Msk                             /*!< Transmission Request Pending */
#define FDCAN_TXBRP_TRP25_Pos                     (25U)
#define FDCAN_TXBRP_TRP25_Msk                     (0x1UL<<FDCAN_TXBRP_TRP25_Pos)                    /*!< 0x02000000 */
#define FDCAN_TXBRP_TRP25                         FDCAN_TXBRP_TRP25_Msk                             /*!< Transmission Request Pending */
#define FDCAN_TXBRP_TRP26_Pos                     (26U)
#define FDCAN_TXBRP_TRP26_Msk                     (0x1UL<<FDCAN_TXBRP_TRP26_Pos)                    /*!< 0x04000000 */
#define FDCAN_TXBRP_TRP26                         FDCAN_TXBRP_TRP26_Msk                             /*!< Transmission Request Pending */
#define FDCAN_TXBRP_TRP27_Pos                     (27U)
#define FDCAN_TXBRP_TRP27_Msk                     (0x1UL<<FDCAN_TXBRP_TRP27_Pos)                    /*!< 0x08000000 */
#define FDCAN_TXBRP_TRP27                         FDCAN_TXBRP_TRP27_Msk                             /*!< Transmission Request Pending */
#define FDCAN_TXBRP_TRP28_Pos                     (28U)
#define FDCAN_TXBRP_TRP28_Msk                     (0x1UL<<FDCAN_TXBRP_TRP28_Pos)                    /*!< 0x10000000 */
#define FDCAN_TXBRP_TRP28                         FDCAN_TXBRP_TRP28_Msk                             /*!< Transmission Request Pending */
#define FDCAN_TXBRP_TRP29_Pos                     (29U)
#define FDCAN_TXBRP_TRP29_Msk                     (0x1UL<<FDCAN_TXBRP_TRP29_Pos)                    /*!< 0x20000000 */
#define FDCAN_TXBRP_TRP29                         FDCAN_TXBRP_TRP29_Msk                             /*!< Transmission Request Pending */
#define FDCAN_TXBRP_TRP30_Pos                     (30U)
#define FDCAN_TXBRP_TRP30_Msk                     (0x1UL<<FDCAN_TXBRP_TRP30_Pos)                    /*!< 0x40000000 */
#define FDCAN_TXBRP_TRP30                         FDCAN_TXBRP_TRP30_Msk                             /*!< Transmission Request Pending */
#define FDCAN_TXBRP_TRP31_Pos                     (31U)
#define FDCAN_TXBRP_TRP31_Msk                     (0x1UL<<FDCAN_TXBRP_TRP31_Pos)                    /*!< 0x80000000 */
#define FDCAN_TXBRP_TRP31                         FDCAN_TXBRP_TRP31_Msk                             /*!< Transmission Request Pending */

/********************************* Bit definition for FDCAN_TXBAR register ******************************************/
#define FDCAN_TXBAR_AR0_Pos                       (0U)
#define FDCAN_TXBAR_AR0_Msk                       (0x1UL<<FDCAN_TXBAR_AR0_Pos)                      /*!< 0x00000001 */
#define FDCAN_TXBAR_AR0                           FDCAN_TXBAR_AR0_Msk                               /*!< Add Request */
#define FDCAN_TXBAR_AR1_Pos                       (1U)
#define FDCAN_TXBAR_AR1_Msk                       (0x1UL<<FDCAN_TXBAR_AR1_Pos)                      /*!< 0x00000002 */
#define FDCAN_TXBAR_AR1                           FDCAN_TXBAR_AR1_Msk                               /*!< Add Request */
#define FDCAN_TXBAR_AR2_Pos                       (2U)
#define FDCAN_TXBAR_AR2_Msk                       (0x1UL<<FDCAN_TXBAR_AR2_Pos)                      /*!< 0x00000004 */
#define FDCAN_TXBAR_AR2                           FDCAN_TXBAR_AR2_Msk                               /*!< Add Request */
#define FDCAN_TXBAR_AR3_Pos                       (3U)
#define FDCAN_TXBAR_AR3_Msk                       (0x1UL<<FDCAN_TXBAR_AR3_Pos)                      /*!< 0x00000008 */
#define FDCAN_TXBAR_AR3                           FDCAN_TXBAR_AR3_Msk                               /*!< Add Request */
#define FDCAN_TXBAR_AR4_Pos                       (4U)
#define FDCAN_TXBAR_AR4_Msk                       (0x1UL<<FDCAN_TXBAR_AR4_Pos)                      /*!< 0x00000010 */
#define FDCAN_TXBAR_AR4                           FDCAN_TXBAR_AR4_Msk                               /*!< Add Request */
#define FDCAN_TXBAR_AR5_Pos                       (5U)
#define FDCAN_TXBAR_AR5_Msk                       (0x1UL<<FDCAN_TXBAR_AR5_Pos)                      /*!< 0x00000020 */
#define FDCAN_TXBAR_AR5                           FDCAN_TXBAR_AR5_Msk                               /*!< Add Request */
#define FDCAN_TXBAR_AR6_Pos                       (6U)
#define FDCAN_TXBAR_AR6_Msk                       (0x1UL<<FDCAN_TXBAR_AR6_Pos)                      /*!< 0x00000040 */
#define FDCAN_TXBAR_AR6                           FDCAN_TXBAR_AR6_Msk                               /*!< Add Request */
#define FDCAN_TXBAR_AR7_Pos                       (7U)
#define FDCAN_TXBAR_AR7_Msk                       (0x1UL<<FDCAN_TXBAR_AR7_Pos)                      /*!< 0x00000080 */
#define FDCAN_TXBAR_AR7                           FDCAN_TXBAR_AR7_Msk                               /*!< Add Request */
#define FDCAN_TXBAR_AR8_Pos                       (8U)
#define FDCAN_TXBAR_AR8_Msk                       (0x1UL<<FDCAN_TXBAR_AR8_Pos)                      /*!< 0x00000100 */
#define FDCAN_TXBAR_AR8                           FDCAN_TXBAR_AR8_Msk                               /*!< Add Request */
#define FDCAN_TXBAR_AR9_Pos                       (9U)
#define FDCAN_TXBAR_AR9_Msk                       (0x1UL<<FDCAN_TXBAR_AR9_Pos)                      /*!< 0x00000200 */
#define FDCAN_TXBAR_AR9                           FDCAN_TXBAR_AR9_Msk                               /*!< Add Request */
#define FDCAN_TXBAR_AR10_Pos                      (10U)
#define FDCAN_TXBAR_AR10_Msk                      (0x1UL<<FDCAN_TXBAR_AR10_Pos)                     /*!< 0x00000400 */
#define FDCAN_TXBAR_AR10                          FDCAN_TXBAR_AR10_Msk                              /*!< Add Request */
#define FDCAN_TXBAR_AR11_Pos                      (11U)
#define FDCAN_TXBAR_AR11_Msk                      (0x1UL<<FDCAN_TXBAR_AR11_Pos)                     /*!< 0x00000800 */
#define FDCAN_TXBAR_AR11                          FDCAN_TXBAR_AR11_Msk                              /*!< Add Request */
#define FDCAN_TXBAR_AR12_Pos                      (12U)
#define FDCAN_TXBAR_AR12_Msk                      (0x1UL<<FDCAN_TXBAR_AR12_Pos)                     /*!< 0x00001000 */
#define FDCAN_TXBAR_AR12                          FDCAN_TXBAR_AR12_Msk                              /*!< Add Request */
#define FDCAN_TXBAR_AR13_Pos                      (13U)
#define FDCAN_TXBAR_AR13_Msk                      (0x1UL<<FDCAN_TXBAR_AR13_Pos)                     /*!< 0x00002000 */
#define FDCAN_TXBAR_AR13                          FDCAN_TXBAR_AR13_Msk                              /*!< Add Request */
#define FDCAN_TXBAR_AR14_Pos                      (14U)
#define FDCAN_TXBAR_AR14_Msk                      (0x1UL<<FDCAN_TXBAR_AR14_Pos)                     /*!< 0x00004000 */
#define FDCAN_TXBAR_AR14                          FDCAN_TXBAR_AR14_Msk                              /*!< Add Request */
#define FDCAN_TXBAR_AR15_Pos                      (15U)
#define FDCAN_TXBAR_AR15_Msk                      (0x1UL<<FDCAN_TXBAR_AR15_Pos)                     /*!< 0x00008000 */
#define FDCAN_TXBAR_AR15                          FDCAN_TXBAR_AR15_Msk                              /*!< Add Request */
#define FDCAN_TXBAR_AR16_Pos                      (16U)
#define FDCAN_TXBAR_AR16_Msk                      (0x1UL<<FDCAN_TXBAR_AR16_Pos)                     /*!< 0x00010000 */
#define FDCAN_TXBAR_AR16                          FDCAN_TXBAR_AR16_Msk                              /*!< Add Request */
#define FDCAN_TXBAR_AR17_Pos                      (17U)
#define FDCAN_TXBAR_AR17_Msk                      (0x1UL<<FDCAN_TXBAR_AR17_Pos)                     /*!< 0x00020000 */
#define FDCAN_TXBAR_AR17                          FDCAN_TXBAR_AR17_Msk                              /*!< Add Request */
#define FDCAN_TXBAR_AR18_Pos                      (18U)
#define FDCAN_TXBAR_AR18_Msk                      (0x1UL<<FDCAN_TXBAR_AR18_Pos)                     /*!< 0x00040000 */
#define FDCAN_TXBAR_AR18                          FDCAN_TXBAR_AR18_Msk                              /*!< Add Request */
#define FDCAN_TXBAR_AR19_Pos                      (19U)
#define FDCAN_TXBAR_AR19_Msk                      (0x1UL<<FDCAN_TXBAR_AR19_Pos)                     /*!< 0x00080000 */
#define FDCAN_TXBAR_AR19                          FDCAN_TXBAR_AR19_Msk                              /*!< Add Request */
#define FDCAN_TXBAR_AR20_Pos                      (20U)
#define FDCAN_TXBAR_AR20_Msk                      (0x1UL<<FDCAN_TXBAR_AR20_Pos)                     /*!< 0x00100000 */
#define FDCAN_TXBAR_AR20                          FDCAN_TXBAR_AR20_Msk                              /*!< Add Request */
#define FDCAN_TXBAR_AR21_Pos                      (21U)
#define FDCAN_TXBAR_AR21_Msk                      (0x1UL<<FDCAN_TXBAR_AR21_Pos)                     /*!< 0x00200000 */
#define FDCAN_TXBAR_AR21                          FDCAN_TXBAR_AR21_Msk                              /*!< Add Request */
#define FDCAN_TXBAR_AR22_Pos                      (22U)
#define FDCAN_TXBAR_AR22_Msk                      (0x1UL<<FDCAN_TXBAR_AR22_Pos)                     /*!< 0x00400000 */
#define FDCAN_TXBAR_AR22                          FDCAN_TXBAR_AR22_Msk                              /*!< Add Request */
#define FDCAN_TXBAR_AR23_Pos                      (23U)
#define FDCAN_TXBAR_AR23_Msk                      (0x1UL<<FDCAN_TXBAR_AR23_Pos)                     /*!< 0x00800000 */
#define FDCAN_TXBAR_AR23                          FDCAN_TXBAR_AR23_Msk                              /*!< Add Request */
#define FDCAN_TXBAR_AR24_Pos                      (24U)
#define FDCAN_TXBAR_AR24_Msk                      (0x1UL<<FDCAN_TXBAR_AR24_Pos)                     /*!< 0x01000000 */
#define FDCAN_TXBAR_AR24                          FDCAN_TXBAR_AR24_Msk                              /*!< Add Request */
#define FDCAN_TXBAR_AR25_Pos                      (25U)
#define FDCAN_TXBAR_AR25_Msk                      (0x1UL<<FDCAN_TXBAR_AR25_Pos)                     /*!< 0x02000000 */
#define FDCAN_TXBAR_AR25                          FDCAN_TXBAR_AR25_Msk                              /*!< Add Request */
#define FDCAN_TXBAR_AR26_Pos                      (26U)
#define FDCAN_TXBAR_AR26_Msk                      (0x1UL<<FDCAN_TXBAR_AR26_Pos)                     /*!< 0x04000000 */
#define FDCAN_TXBAR_AR26                          FDCAN_TXBAR_AR26_Msk                              /*!< Add Request */
#define FDCAN_TXBAR_AR27_Pos                      (27U)
#define FDCAN_TXBAR_AR27_Msk                      (0x1UL<<FDCAN_TXBAR_AR27_Pos)                     /*!< 0x08000000 */
#define FDCAN_TXBAR_AR27                          FDCAN_TXBAR_AR27_Msk                              /*!< Add Request */
#define FDCAN_TXBAR_AR28_Pos                      (28U)
#define FDCAN_TXBAR_AR28_Msk                      (0x1UL<<FDCAN_TXBAR_AR28_Pos)                     /*!< 0x10000000 */
#define FDCAN_TXBAR_AR28                          FDCAN_TXBAR_AR28_Msk                              /*!< Add Request */
#define FDCAN_TXBAR_AR29_Pos                      (29U)
#define FDCAN_TXBAR_AR29_Msk                      (0x1UL<<FDCAN_TXBAR_AR29_Pos)                     /*!< 0x20000000 */
#define FDCAN_TXBAR_AR29                          FDCAN_TXBAR_AR29_Msk                              /*!< Add Request */
#define FDCAN_TXBAR_AR30_Pos                      (30U)
#define FDCAN_TXBAR_AR30_Msk                      (0x1UL<<FDCAN_TXBAR_AR30_Pos)                     /*!< 0x40000000 */
#define FDCAN_TXBAR_AR30                          FDCAN_TXBAR_AR30_Msk                              /*!< Add Request */
#define FDCAN_TXBAR_AR31_Pos                      (31U)
#define FDCAN_TXBAR_AR31_Msk                      (0x1UL<<FDCAN_TXBAR_AR31_Pos)                     /*!< 0x80000000 */
#define FDCAN_TXBAR_AR31                          FDCAN_TXBAR_AR31_Msk                              /*!< Add Request */

/********************************* Bit definition for FDCAN_TXBCR register ******************************************/
#define FDCAN_TXBCR_CR0_Pos                       (0U)
#define FDCAN_TXBCR_CR0_Msk                       (0x1UL<<FDCAN_TXBCR_CR0_Pos)                      /*!< 0x00000001 */
#define FDCAN_TXBCR_CR0                           FDCAN_TXBCR_CR0_Msk                               /*!< Cancellation Request */
#define FDCAN_TXBCR_CR1_Pos                       (1U)
#define FDCAN_TXBCR_CR1_Msk                       (0x1UL<<FDCAN_TXBCR_CR1_Pos)                      /*!< 0x00000002 */
#define FDCAN_TXBCR_CR1                           FDCAN_TXBCR_CR1_Msk                               /*!< Cancellation Request */
#define FDCAN_TXBCR_CR2_Pos                       (2U)
#define FDCAN_TXBCR_CR2_Msk                       (0x1UL<<FDCAN_TXBCR_CR2_Pos)                      /*!< 0x00000004 */
#define FDCAN_TXBCR_CR2                           FDCAN_TXBCR_CR2_Msk                               /*!< Cancellation Request */
#define FDCAN_TXBCR_CR3_Pos                       (3U)
#define FDCAN_TXBCR_CR3_Msk                       (0x1UL<<FDCAN_TXBCR_CR3_Pos)                      /*!< 0x00000008 */
#define FDCAN_TXBCR_CR3                           FDCAN_TXBCR_CR3_Msk                               /*!< Cancellation Request */
#define FDCAN_TXBCR_CR4_Pos                       (4U)
#define FDCAN_TXBCR_CR4_Msk                       (0x1UL<<FDCAN_TXBCR_CR4_Pos)                      /*!< 0x00000010 */
#define FDCAN_TXBCR_CR4                           FDCAN_TXBCR_CR4_Msk                               /*!< Cancellation Request */
#define FDCAN_TXBCR_CR5_Pos                       (5U)
#define FDCAN_TXBCR_CR5_Msk                       (0x1UL<<FDCAN_TXBCR_CR5_Pos)                      /*!< 0x00000020 */
#define FDCAN_TXBCR_CR5                           FDCAN_TXBCR_CR5_Msk                               /*!< Cancellation Request */
#define FDCAN_TXBCR_CR6_Pos                       (6U)
#define FDCAN_TXBCR_CR6_Msk                       (0x1UL<<FDCAN_TXBCR_CR6_Pos)                      /*!< 0x00000040 */
#define FDCAN_TXBCR_CR6                           FDCAN_TXBCR_CR6_Msk                               /*!< Cancellation Request */
#define FDCAN_TXBCR_CR7_Pos                       (7U)
#define FDCAN_TXBCR_CR7_Msk                       (0x1UL<<FDCAN_TXBCR_CR7_Pos)                      /*!< 0x00000080 */
#define FDCAN_TXBCR_CR7                           FDCAN_TXBCR_CR7_Msk                               /*!< Cancellation Request */
#define FDCAN_TXBCR_CR8_Pos                       (8U)
#define FDCAN_TXBCR_CR8_Msk                       (0x1UL<<FDCAN_TXBCR_CR8_Pos)                      /*!< 0x00000100 */
#define FDCAN_TXBCR_CR8                           FDCAN_TXBCR_CR8_Msk                               /*!< Cancellation Request */
#define FDCAN_TXBCR_CR9_Pos                       (9U)
#define FDCAN_TXBCR_CR9_Msk                       (0x1UL<<FDCAN_TXBCR_CR9_Pos)                      /*!< 0x00000200 */
#define FDCAN_TXBCR_CR9                           FDCAN_TXBCR_CR9_Msk                               /*!< Cancellation Request */
#define FDCAN_TXBCR_CR10_Pos                      (10U)
#define FDCAN_TXBCR_CR10_Msk                      (0x1UL<<FDCAN_TXBCR_CR10_Pos)                     /*!< 0x00000400 */
#define FDCAN_TXBCR_CR10                          FDCAN_TXBCR_CR10_Msk                              /*!< Cancellation Request */
#define FDCAN_TXBCR_CR11_Pos                      (11U)
#define FDCAN_TXBCR_CR11_Msk                      (0x1UL<<FDCAN_TXBCR_CR11_Pos)                     /*!< 0x00000800 */
#define FDCAN_TXBCR_CR11                          FDCAN_TXBCR_CR11_Msk                              /*!< Cancellation Request */
#define FDCAN_TXBCR_CR12_Pos                      (12U)
#define FDCAN_TXBCR_CR12_Msk                      (0x1UL<<FDCAN_TXBCR_CR12_Pos)                     /*!< 0x00001000 */
#define FDCAN_TXBCR_CR12                          FDCAN_TXBCR_CR12_Msk                              /*!< Cancellation Request */
#define FDCAN_TXBCR_CR13_Pos                      (13U)
#define FDCAN_TXBCR_CR13_Msk                      (0x1UL<<FDCAN_TXBCR_CR13_Pos)                     /*!< 0x00002000 */
#define FDCAN_TXBCR_CR13                          FDCAN_TXBCR_CR13_Msk                              /*!< Cancellation Request */
#define FDCAN_TXBCR_CR14_Pos                      (14U)
#define FDCAN_TXBCR_CR14_Msk                      (0x1UL<<FDCAN_TXBCR_CR14_Pos)                     /*!< 0x00004000 */
#define FDCAN_TXBCR_CR14                          FDCAN_TXBCR_CR14_Msk                              /*!< Cancellation Request */
#define FDCAN_TXBCR_CR15_Pos                      (15U)
#define FDCAN_TXBCR_CR15_Msk                      (0x1UL<<FDCAN_TXBCR_CR15_Pos)                     /*!< 0x00008000 */
#define FDCAN_TXBCR_CR15                          FDCAN_TXBCR_CR15_Msk                              /*!< Cancellation Request */
#define FDCAN_TXBCR_CR16_Pos                      (16U)
#define FDCAN_TXBCR_CR16_Msk                      (0x1UL<<FDCAN_TXBCR_CR16_Pos)                     /*!< 0x00010000 */
#define FDCAN_TXBCR_CR16                          FDCAN_TXBCR_CR16_Msk                              /*!< Cancellation Request */
#define FDCAN_TXBCR_CR17_Pos                      (17U)
#define FDCAN_TXBCR_CR17_Msk                      (0x1UL<<FDCAN_TXBCR_CR17_Pos)                     /*!< 0x00020000 */
#define FDCAN_TXBCR_CR17                          FDCAN_TXBCR_CR17_Msk                              /*!< Cancellation Request */
#define FDCAN_TXBCR_CR18_Pos                      (18U)
#define FDCAN_TXBCR_CR18_Msk                      (0x1UL<<FDCAN_TXBCR_CR18_Pos)                     /*!< 0x00040000 */
#define FDCAN_TXBCR_CR18                          FDCAN_TXBCR_CR18_Msk                              /*!< Cancellation Request */
#define FDCAN_TXBCR_CR19_Pos                      (19U)
#define FDCAN_TXBCR_CR19_Msk                      (0x1UL<<FDCAN_TXBCR_CR19_Pos)                     /*!< 0x00080000 */
#define FDCAN_TXBCR_CR19                          FDCAN_TXBCR_CR19_Msk                              /*!< Cancellation Request */
#define FDCAN_TXBCR_CR20_Pos                      (20U)
#define FDCAN_TXBCR_CR20_Msk                      (0x1UL<<FDCAN_TXBCR_CR20_Pos)                     /*!< 0x00100000 */
#define FDCAN_TXBCR_CR20                          FDCAN_TXBCR_CR20_Msk                              /*!< Cancellation Request */
#define FDCAN_TXBCR_CR21_Pos                      (21U)
#define FDCAN_TXBCR_CR21_Msk                      (0x1UL<<FDCAN_TXBCR_CR21_Pos)                     /*!< 0x00200000 */
#define FDCAN_TXBCR_CR21                          FDCAN_TXBCR_CR21_Msk                              /*!< Cancellation Request */
#define FDCAN_TXBCR_CR22_Pos                      (22U)
#define FDCAN_TXBCR_CR22_Msk                      (0x1UL<<FDCAN_TXBCR_CR22_Pos)                     /*!< 0x00400000 */
#define FDCAN_TXBCR_CR22                          FDCAN_TXBCR_CR22_Msk                              /*!< Cancellation Request */
#define FDCAN_TXBCR_CR23_Pos                      (23U)
#define FDCAN_TXBCR_CR23_Msk                      (0x1UL<<FDCAN_TXBCR_CR23_Pos)                     /*!< 0x00800000 */
#define FDCAN_TXBCR_CR23                          FDCAN_TXBCR_CR23_Msk                              /*!< Cancellation Request */
#define FDCAN_TXBCR_CR24_Pos                      (24U)
#define FDCAN_TXBCR_CR24_Msk                      (0x1UL<<FDCAN_TXBCR_CR24_Pos)                     /*!< 0x01000000 */
#define FDCAN_TXBCR_CR24                          FDCAN_TXBCR_CR24_Msk                              /*!< Cancellation Request */
#define FDCAN_TXBCR_CR25_Pos                      (25U)
#define FDCAN_TXBCR_CR25_Msk                      (0x1UL<<FDCAN_TXBCR_CR25_Pos)                     /*!< 0x02000000 */
#define FDCAN_TXBCR_CR25                          FDCAN_TXBCR_CR25_Msk                              /*!< Cancellation Request */
#define FDCAN_TXBCR_CR26_Pos                      (26U)
#define FDCAN_TXBCR_CR26_Msk                      (0x1UL<<FDCAN_TXBCR_CR26_Pos)                     /*!< 0x04000000 */
#define FDCAN_TXBCR_CR26                          FDCAN_TXBCR_CR26_Msk                              /*!< Cancellation Request */
#define FDCAN_TXBCR_CR27_Pos                      (27U)
#define FDCAN_TXBCR_CR27_Msk                      (0x1UL<<FDCAN_TXBCR_CR27_Pos)                     /*!< 0x08000000 */
#define FDCAN_TXBCR_CR27                          FDCAN_TXBCR_CR27_Msk                              /*!< Cancellation Request */
#define FDCAN_TXBCR_CR28_Pos                      (28U)
#define FDCAN_TXBCR_CR28_Msk                      (0x1UL<<FDCAN_TXBCR_CR28_Pos)                     /*!< 0x10000000 */
#define FDCAN_TXBCR_CR28                          FDCAN_TXBCR_CR28_Msk                              /*!< Cancellation Request */
#define FDCAN_TXBCR_CR29_Pos                      (29U)
#define FDCAN_TXBCR_CR29_Msk                      (0x1UL<<FDCAN_TXBCR_CR29_Pos)                     /*!< 0x20000000 */
#define FDCAN_TXBCR_CR29                          FDCAN_TXBCR_CR29_Msk                              /*!< Cancellation Request */
#define FDCAN_TXBCR_CR30_Pos                      (30U)
#define FDCAN_TXBCR_CR30_Msk                      (0x1UL<<FDCAN_TXBCR_CR30_Pos)                     /*!< 0x40000000 */
#define FDCAN_TXBCR_CR30                          FDCAN_TXBCR_CR30_Msk                              /*!< Cancellation Request */
#define FDCAN_TXBCR_CR31_Pos                      (31U)
#define FDCAN_TXBCR_CR31_Msk                      (0x1UL<<FDCAN_TXBCR_CR31_Pos)                     /*!< 0x80000000 */
#define FDCAN_TXBCR_CR31                          FDCAN_TXBCR_CR31_Msk                              /*!< Cancellation Request */

/********************************* Bit definition for FDCAN_TXBTO register ******************************************/
#define FDCAN_TXBTO_TO0_Pos                       (0U)
#define FDCAN_TXBTO_TO0_Msk                       (0x1UL<<FDCAN_TXBTO_TO0_Pos)                      /*!< 0x00000001 */
#define FDCAN_TXBTO_TO0                           FDCAN_TXBTO_TO0_Msk                               /*!< Transmission Occurred */
#define FDCAN_TXBTO_TO1_Pos                       (1U)
#define FDCAN_TXBTO_TO1_Msk                       (0x1UL<<FDCAN_TXBTO_TO1_Pos)                      /*!< 0x00000002 */
#define FDCAN_TXBTO_TO1                           FDCAN_TXBTO_TO1_Msk                               /*!< Transmission Occurred */
#define FDCAN_TXBTO_TO2_Pos                       (2U)
#define FDCAN_TXBTO_TO2_Msk                       (0x1UL<<FDCAN_TXBTO_TO2_Pos)                      /*!< 0x00000004 */
#define FDCAN_TXBTO_TO2                           FDCAN_TXBTO_TO2_Msk                               /*!< Transmission Occurred */
#define FDCAN_TXBTO_TO3_Pos                       (3U)
#define FDCAN_TXBTO_TO3_Msk                       (0x1UL<<FDCAN_TXBTO_TO3_Pos)                      /*!< 0x00000008 */
#define FDCAN_TXBTO_TO3                           FDCAN_TXBTO_TO3_Msk                               /*!< Transmission Occurred */
#define FDCAN_TXBTO_TO4_Pos                       (4U)
#define FDCAN_TXBTO_TO4_Msk                       (0x1UL<<FDCAN_TXBTO_TO4_Pos)                      /*!< 0x00000010 */
#define FDCAN_TXBTO_TO4                           FDCAN_TXBTO_TO4_Msk                               /*!< Transmission Occurred */
#define FDCAN_TXBTO_TO5_Pos                       (5U)
#define FDCAN_TXBTO_TO5_Msk                       (0x1UL<<FDCAN_TXBTO_TO5_Pos)                      /*!< 0x00000020 */
#define FDCAN_TXBTO_TO5                           FDCAN_TXBTO_TO5_Msk                               /*!< Transmission Occurred */
#define FDCAN_TXBTO_TO6_Pos                       (6U)
#define FDCAN_TXBTO_TO6_Msk                       (0x1UL<<FDCAN_TXBTO_TO6_Pos)                      /*!< 0x00000040 */
#define FDCAN_TXBTO_TO6                           FDCAN_TXBTO_TO6_Msk                               /*!< Transmission Occurred */
#define FDCAN_TXBTO_TO7_Pos                       (7U)
#define FDCAN_TXBTO_TO7_Msk                       (0x1UL<<FDCAN_TXBTO_TO7_Pos)                      /*!< 0x00000080 */
#define FDCAN_TXBTO_TO7                           FDCAN_TXBTO_TO7_Msk                               /*!< Transmission Occurred */
#define FDCAN_TXBTO_TO8_Pos                       (8U)
#define FDCAN_TXBTO_TO8_Msk                       (0x1UL<<FDCAN_TXBTO_TO8_Pos)                      /*!< 0x00000100 */
#define FDCAN_TXBTO_TO8                           FDCAN_TXBTO_TO8_Msk                               /*!< Transmission Occurred */
#define FDCAN_TXBTO_TO9_Pos                       (9U)
#define FDCAN_TXBTO_TO9_Msk                       (0x1UL<<FDCAN_TXBTO_TO9_Pos)                      /*!< 0x00000200 */
#define FDCAN_TXBTO_TO9                           FDCAN_TXBTO_TO9_Msk                               /*!< Transmission Occurred */
#define FDCAN_TXBTO_TO10_Pos                      (10U)
#define FDCAN_TXBTO_TO10_Msk                      (0x1UL<<FDCAN_TXBTO_TO10_Pos)                     /*!< 0x00000400 */
#define FDCAN_TXBTO_TO10                          FDCAN_TXBTO_TO10_Msk                              /*!< Transmission Occurred */
#define FDCAN_TXBTO_TO11_Pos                      (11U)
#define FDCAN_TXBTO_TO11_Msk                      (0x1UL<<FDCAN_TXBTO_TO11_Pos)                     /*!< 0x00000800 */
#define FDCAN_TXBTO_TO11                          FDCAN_TXBTO_TO11_Msk                              /*!< Transmission Occurred */
#define FDCAN_TXBTO_TO12_Pos                      (12U)
#define FDCAN_TXBTO_TO12_Msk                      (0x1UL<<FDCAN_TXBTO_TO12_Pos)                     /*!< 0x00001000 */
#define FDCAN_TXBTO_TO12                          FDCAN_TXBTO_TO12_Msk                              /*!< Transmission Occurred */
#define FDCAN_TXBTO_TO13_Pos                      (13U)
#define FDCAN_TXBTO_TO13_Msk                      (0x1UL<<FDCAN_TXBTO_TO13_Pos)                     /*!< 0x00002000 */
#define FDCAN_TXBTO_TO13                          FDCAN_TXBTO_TO13_Msk                              /*!< Transmission Occurred */
#define FDCAN_TXBTO_TO14_Pos                      (14U)
#define FDCAN_TXBTO_TO14_Msk                      (0x1UL<<FDCAN_TXBTO_TO14_Pos)                     /*!< 0x00004000 */
#define FDCAN_TXBTO_TO14                          FDCAN_TXBTO_TO14_Msk                              /*!< Transmission Occurred */
#define FDCAN_TXBTO_TO15_Pos                      (15U)
#define FDCAN_TXBTO_TO15_Msk                      (0x1UL<<FDCAN_TXBTO_TO15_Pos)                     /*!< 0x00008000 */
#define FDCAN_TXBTO_TO15                          FDCAN_TXBTO_TO15_Msk                              /*!< Transmission Occurred */
#define FDCAN_TXBTO_TO16_Pos                      (16U)
#define FDCAN_TXBTO_TO16_Msk                      (0x1UL<<FDCAN_TXBTO_TO16_Pos)                     /*!< 0x00010000 */
#define FDCAN_TXBTO_TO16                          FDCAN_TXBTO_TO16_Msk                              /*!< Transmission Occurred */
#define FDCAN_TXBTO_TO17_Pos                      (17U)
#define FDCAN_TXBTO_TO17_Msk                      (0x1UL<<FDCAN_TXBTO_TO17_Pos)                     /*!< 0x00020000 */
#define FDCAN_TXBTO_TO17                          FDCAN_TXBTO_TO17_Msk                              /*!< Transmission Occurred */
#define FDCAN_TXBTO_TO18_Pos                      (18U)
#define FDCAN_TXBTO_TO18_Msk                      (0x1UL<<FDCAN_TXBTO_TO18_Pos)                     /*!< 0x00040000 */
#define FDCAN_TXBTO_TO18                          FDCAN_TXBTO_TO18_Msk                              /*!< Transmission Occurred */
#define FDCAN_TXBTO_TO19_Pos                      (19U)
#define FDCAN_TXBTO_TO19_Msk                      (0x1UL<<FDCAN_TXBTO_TO19_Pos)                     /*!< 0x00080000 */
#define FDCAN_TXBTO_TO19                          FDCAN_TXBTO_TO19_Msk                              /*!< Transmission Occurred */
#define FDCAN_TXBTO_TO20_Pos                      (20U)
#define FDCAN_TXBTO_TO20_Msk                      (0x1UL<<FDCAN_TXBTO_TO20_Pos)                     /*!< 0x00100000 */
#define FDCAN_TXBTO_TO20                          FDCAN_TXBTO_TO20_Msk                              /*!< Transmission Occurred */
#define FDCAN_TXBTO_TO21_Pos                      (21U)
#define FDCAN_TXBTO_TO21_Msk                      (0x1UL<<FDCAN_TXBTO_TO21_Pos)                     /*!< 0x00200000 */
#define FDCAN_TXBTO_TO21                          FDCAN_TXBTO_TO21_Msk                              /*!< Transmission Occurred */
#define FDCAN_TXBTO_TO22_Pos                      (22U)
#define FDCAN_TXBTO_TO22_Msk                      (0x1UL<<FDCAN_TXBTO_TO22_Pos)                     /*!< 0x00400000 */
#define FDCAN_TXBTO_TO22                          FDCAN_TXBTO_TO22_Msk                              /*!< Transmission Occurred */
#define FDCAN_TXBTO_TO23_Pos                      (23U)
#define FDCAN_TXBTO_TO23_Msk                      (0x1UL<<FDCAN_TXBTO_TO23_Pos)                     /*!< 0x00800000 */
#define FDCAN_TXBTO_TO23                          FDCAN_TXBTO_TO23_Msk                              /*!< Transmission Occurred */
#define FDCAN_TXBTO_TO24_Pos                      (24U)
#define FDCAN_TXBTO_TO24_Msk                      (0x1UL<<FDCAN_TXBTO_TO24_Pos)                     /*!< 0x01000000 */
#define FDCAN_TXBTO_TO24                          FDCAN_TXBTO_TO24_Msk                              /*!< Transmission Occurred */
#define FDCAN_TXBTO_TO25_Pos                      (25U)
#define FDCAN_TXBTO_TO25_Msk                      (0x1UL<<FDCAN_TXBTO_TO25_Pos)                     /*!< 0x02000000 */
#define FDCAN_TXBTO_TO25                          FDCAN_TXBTO_TO25_Msk                              /*!< Transmission Occurred */
#define FDCAN_TXBTO_TO26_Pos                      (26U)
#define FDCAN_TXBTO_TO26_Msk                      (0x1UL<<FDCAN_TXBTO_TO26_Pos)                     /*!< 0x04000000 */
#define FDCAN_TXBTO_TO26                          FDCAN_TXBTO_TO26_Msk                              /*!< Transmission Occurred */
#define FDCAN_TXBTO_TO27_Pos                      (27U)
#define FDCAN_TXBTO_TO27_Msk                      (0x1UL<<FDCAN_TXBTO_TO27_Pos)                     /*!< 0x08000000 */
#define FDCAN_TXBTO_TO27                          FDCAN_TXBTO_TO27_Msk                              /*!< Transmission Occurred */
#define FDCAN_TXBTO_TO28_Pos                      (28U)
#define FDCAN_TXBTO_TO28_Msk                      (0x1UL<<FDCAN_TXBTO_TO28_Pos)                     /*!< 0x10000000 */
#define FDCAN_TXBTO_TO28                          FDCAN_TXBTO_TO28_Msk                              /*!< Transmission Occurred */
#define FDCAN_TXBTO_TO29_Pos                      (29U)
#define FDCAN_TXBTO_TO29_Msk                      (0x1UL<<FDCAN_TXBTO_TO29_Pos)                     /*!< 0x20000000 */
#define FDCAN_TXBTO_TO29                          FDCAN_TXBTO_TO29_Msk                              /*!< Transmission Occurred */
#define FDCAN_TXBTO_TO30_Pos                      (30U)
#define FDCAN_TXBTO_TO30_Msk                      (0x1UL<<FDCAN_TXBTO_TO30_Pos)                     /*!< 0x40000000 */
#define FDCAN_TXBTO_TO30                          FDCAN_TXBTO_TO30_Msk                              /*!< Transmission Occurred */
#define FDCAN_TXBTO_TO31_Pos                      (31U)
#define FDCAN_TXBTO_TO31_Msk                      (0x1UL<<FDCAN_TXBTO_TO31_Pos)                     /*!< 0x80000000 */
#define FDCAN_TXBTO_TO31                          FDCAN_TXBTO_TO31_Msk                              /*!< Transmission Occurred */

/********************************* Bit definition for FDCAN_TXBCF register ******************************************/
#define FDCAN_TXBCF_CF0_Pos                       (0U)
#define FDCAN_TXBCF_CF0_Msk                       (0x1UL<<FDCAN_TXBCF_CF0_Pos)                      /*!< 0x00000001 */
#define FDCAN_TXBCF_CF0                           FDCAN_TXBCF_CF0_Msk                               /*!< Cancellation Finished */
#define FDCAN_TXBCF_CF1_Pos                       (1U)
#define FDCAN_TXBCF_CF1_Msk                       (0x1UL<<FDCAN_TXBCF_CF1_Pos)                      /*!< 0x00000002 */
#define FDCAN_TXBCF_CF1                           FDCAN_TXBCF_CF1_Msk                               /*!< Cancellation Finished */
#define FDCAN_TXBCF_CF2_Pos                       (2U)
#define FDCAN_TXBCF_CF2_Msk                       (0x1UL<<FDCAN_TXBCF_CF2_Pos)                      /*!< 0x00000004 */
#define FDCAN_TXBCF_CF2                           FDCAN_TXBCF_CF2_Msk                               /*!< Cancellation Finished */
#define FDCAN_TXBCF_CF3_Pos                       (3U)
#define FDCAN_TXBCF_CF3_Msk                       (0x1UL<<FDCAN_TXBCF_CF3_Pos)                      /*!< 0x00000008 */
#define FDCAN_TXBCF_CF3                           FDCAN_TXBCF_CF3_Msk                               /*!< Cancellation Finished */
#define FDCAN_TXBCF_CF4_Pos                       (4U)
#define FDCAN_TXBCF_CF4_Msk                       (0x1UL<<FDCAN_TXBCF_CF4_Pos)                      /*!< 0x00000010 */
#define FDCAN_TXBCF_CF4                           FDCAN_TXBCF_CF4_Msk                               /*!< Cancellation Finished */
#define FDCAN_TXBCF_CF5_Pos                       (5U)
#define FDCAN_TXBCF_CF5_Msk                       (0x1UL<<FDCAN_TXBCF_CF5_Pos)                      /*!< 0x00000020 */
#define FDCAN_TXBCF_CF5                           FDCAN_TXBCF_CF5_Msk                               /*!< Cancellation Finished */
#define FDCAN_TXBCF_CF6_Pos                       (6U)
#define FDCAN_TXBCF_CF6_Msk                       (0x1UL<<FDCAN_TXBCF_CF6_Pos)                      /*!< 0x00000040 */
#define FDCAN_TXBCF_CF6                           FDCAN_TXBCF_CF6_Msk                               /*!< Cancellation Finished */
#define FDCAN_TXBCF_CF7_Pos                       (7U)
#define FDCAN_TXBCF_CF7_Msk                       (0x1UL<<FDCAN_TXBCF_CF7_Pos)                      /*!< 0x00000080 */
#define FDCAN_TXBCF_CF7                           FDCAN_TXBCF_CF7_Msk                               /*!< Cancellation Finished */
#define FDCAN_TXBCF_CF8_Pos                       (8U)
#define FDCAN_TXBCF_CF8_Msk                       (0x1UL<<FDCAN_TXBCF_CF8_Pos)                      /*!< 0x00000100 */
#define FDCAN_TXBCF_CF8                           FDCAN_TXBCF_CF8_Msk                               /*!< Cancellation Finished */
#define FDCAN_TXBCF_CF9_Pos                       (9U)
#define FDCAN_TXBCF_CF9_Msk                       (0x1UL<<FDCAN_TXBCF_CF9_Pos)                      /*!< 0x00000200 */
#define FDCAN_TXBCF_CF9                           FDCAN_TXBCF_CF9_Msk                               /*!< Cancellation Finished */
#define FDCAN_TXBCF_CF10_Pos                      (10U)
#define FDCAN_TXBCF_CF10_Msk                      (0x1UL<<FDCAN_TXBCF_CF10_Pos)                     /*!< 0x00000400 */
#define FDCAN_TXBCF_CF10                          FDCAN_TXBCF_CF10_Msk                              /*!< Cancellation Finished */
#define FDCAN_TXBCF_CF11_Pos                      (11U)
#define FDCAN_TXBCF_CF11_Msk                      (0x1UL<<FDCAN_TXBCF_CF11_Pos)                     /*!< 0x00000800 */
#define FDCAN_TXBCF_CF11                          FDCAN_TXBCF_CF11_Msk                              /*!< Cancellation Finished */
#define FDCAN_TXBCF_CF12_Pos                      (12U)
#define FDCAN_TXBCF_CF12_Msk                      (0x1UL<<FDCAN_TXBCF_CF12_Pos)                     /*!< 0x00001000 */
#define FDCAN_TXBCF_CF12                          FDCAN_TXBCF_CF12_Msk                              /*!< Cancellation Finished */
#define FDCAN_TXBCF_CF13_Pos                      (13U)
#define FDCAN_TXBCF_CF13_Msk                      (0x1UL<<FDCAN_TXBCF_CF13_Pos)                     /*!< 0x00002000 */
#define FDCAN_TXBCF_CF13                          FDCAN_TXBCF_CF13_Msk                              /*!< Cancellation Finished */
#define FDCAN_TXBCF_CF14_Pos                      (14U)
#define FDCAN_TXBCF_CF14_Msk                      (0x1UL<<FDCAN_TXBCF_CF14_Pos)                     /*!< 0x00004000 */
#define FDCAN_TXBCF_CF14                          FDCAN_TXBCF_CF14_Msk                              /*!< Cancellation Finished */
#define FDCAN_TXBCF_CF15_Pos                      (15U)
#define FDCAN_TXBCF_CF15_Msk                      (0x1UL<<FDCAN_TXBCF_CF15_Pos)                     /*!< 0x00008000 */
#define FDCAN_TXBCF_CF15                          FDCAN_TXBCF_CF15_Msk                              /*!< Cancellation Finished */
#define FDCAN_TXBCF_CF16_Pos                      (16U)
#define FDCAN_TXBCF_CF16_Msk                      (0x1UL<<FDCAN_TXBCF_CF16_Pos)                     /*!< 0x00010000 */
#define FDCAN_TXBCF_CF16                          FDCAN_TXBCF_CF16_Msk                              /*!< Cancellation Finished */
#define FDCAN_TXBCF_CF17_Pos                      (17U)
#define FDCAN_TXBCF_CF17_Msk                      (0x1UL<<FDCAN_TXBCF_CF17_Pos)                     /*!< 0x00020000 */
#define FDCAN_TXBCF_CF17                          FDCAN_TXBCF_CF17_Msk                              /*!< Cancellation Finished */
#define FDCAN_TXBCF_CF18_Pos                      (18U)
#define FDCAN_TXBCF_CF18_Msk                      (0x1UL<<FDCAN_TXBCF_CF18_Pos)                     /*!< 0x00040000 */
#define FDCAN_TXBCF_CF18                          FDCAN_TXBCF_CF18_Msk                              /*!< Cancellation Finished */
#define FDCAN_TXBCF_CF19_Pos                      (19U)
#define FDCAN_TXBCF_CF19_Msk                      (0x1UL<<FDCAN_TXBCF_CF19_Pos)                     /*!< 0x00080000 */
#define FDCAN_TXBCF_CF19                          FDCAN_TXBCF_CF19_Msk                              /*!< Cancellation Finished */
#define FDCAN_TXBCF_CF20_Pos                      (20U)
#define FDCAN_TXBCF_CF20_Msk                      (0x1UL<<FDCAN_TXBCF_CF20_Pos)                     /*!< 0x00100000 */
#define FDCAN_TXBCF_CF20                          FDCAN_TXBCF_CF20_Msk                              /*!< Cancellation Finished */
#define FDCAN_TXBCF_CF21_Pos                      (21U)
#define FDCAN_TXBCF_CF21_Msk                      (0x1UL<<FDCAN_TXBCF_CF21_Pos)                     /*!< 0x00200000 */
#define FDCAN_TXBCF_CF21                          FDCAN_TXBCF_CF21_Msk                              /*!< Cancellation Finished */
#define FDCAN_TXBCF_CF22_Pos                      (22U)
#define FDCAN_TXBCF_CF22_Msk                      (0x1UL<<FDCAN_TXBCF_CF22_Pos)                     /*!< 0x00400000 */
#define FDCAN_TXBCF_CF22                          FDCAN_TXBCF_CF22_Msk                              /*!< Cancellation Finished */
#define FDCAN_TXBCF_CF23_Pos                      (23U)
#define FDCAN_TXBCF_CF23_Msk                      (0x1UL<<FDCAN_TXBCF_CF23_Pos)                     /*!< 0x00800000 */
#define FDCAN_TXBCF_CF23                          FDCAN_TXBCF_CF23_Msk                              /*!< Cancellation Finished */
#define FDCAN_TXBCF_CF24_Pos                      (24U)
#define FDCAN_TXBCF_CF24_Msk                      (0x1UL<<FDCAN_TXBCF_CF24_Pos)                     /*!< 0x01000000 */
#define FDCAN_TXBCF_CF24                          FDCAN_TXBCF_CF24_Msk                              /*!< Cancellation Finished */
#define FDCAN_TXBCF_CF25_Pos                      (25U)
#define FDCAN_TXBCF_CF25_Msk                      (0x1UL<<FDCAN_TXBCF_CF25_Pos)                     /*!< 0x02000000 */
#define FDCAN_TXBCF_CF25                          FDCAN_TXBCF_CF25_Msk                              /*!< Cancellation Finished */
#define FDCAN_TXBCF_CF26_Pos                      (26U)
#define FDCAN_TXBCF_CF26_Msk                      (0x1UL<<FDCAN_TXBCF_CF26_Pos)                     /*!< 0x04000000 */
#define FDCAN_TXBCF_CF26                          FDCAN_TXBCF_CF26_Msk                              /*!< Cancellation Finished */
#define FDCAN_TXBCF_CF27_Pos                      (27U)
#define FDCAN_TXBCF_CF27_Msk                      (0x1UL<<FDCAN_TXBCF_CF27_Pos)                     /*!< 0x08000000 */
#define FDCAN_TXBCF_CF27                          FDCAN_TXBCF_CF27_Msk                              /*!< Cancellation Finished */
#define FDCAN_TXBCF_CF28_Pos                      (28U)
#define FDCAN_TXBCF_CF28_Msk                      (0x1UL<<FDCAN_TXBCF_CF28_Pos)                     /*!< 0x10000000 */
#define FDCAN_TXBCF_CF28                          FDCAN_TXBCF_CF28_Msk                              /*!< Cancellation Finished */
#define FDCAN_TXBCF_CF29_Pos                      (29U)
#define FDCAN_TXBCF_CF29_Msk                      (0x1UL<<FDCAN_TXBCF_CF29_Pos)                     /*!< 0x20000000 */
#define FDCAN_TXBCF_CF29                          FDCAN_TXBCF_CF29_Msk                              /*!< Cancellation Finished */
#define FDCAN_TXBCF_CF30_Pos                      (30U)
#define FDCAN_TXBCF_CF30_Msk                      (0x1UL<<FDCAN_TXBCF_CF30_Pos)                     /*!< 0x40000000 */
#define FDCAN_TXBCF_CF30                          FDCAN_TXBCF_CF30_Msk                              /*!< Cancellation Finished */
#define FDCAN_TXBCF_CF31_Pos                      (31U)
#define FDCAN_TXBCF_CF31_Msk                      (0x1UL<<FDCAN_TXBCF_CF31_Pos)                     /*!< 0x80000000 */
#define FDCAN_TXBCF_CF31                          FDCAN_TXBCF_CF31_Msk                              /*!< Cancellation Finished */

/********************************* Bit definition for FDCAN_TXBTIE register *****************************************/
#define FDCAN_TXBTIE_TIE0_Pos                     (0U)
#define FDCAN_TXBTIE_TIE0_Msk                     (0x1UL<<FDCAN_TXBTIE_TIE0_Pos)                    /*!< 0x00000001 */
#define FDCAN_TXBTIE_TIE0                         FDCAN_TXBTIE_TIE0_Msk                             /*!< Transmission Interrupt Enable */
#define FDCAN_TXBTIE_TIE1_Pos                     (1U)
#define FDCAN_TXBTIE_TIE1_Msk                     (0x1UL<<FDCAN_TXBTIE_TIE1_Pos)                    /*!< 0x00000002 */
#define FDCAN_TXBTIE_TIE1                         FDCAN_TXBTIE_TIE1_Msk                             /*!< Transmission Interrupt Enable */
#define FDCAN_TXBTIE_TIE2_Pos                     (2U)
#define FDCAN_TXBTIE_TIE2_Msk                     (0x1UL<<FDCAN_TXBTIE_TIE2_Pos)                    /*!< 0x00000004 */
#define FDCAN_TXBTIE_TIE2                         FDCAN_TXBTIE_TIE2_Msk                             /*!< Transmission Interrupt Enable */
#define FDCAN_TXBTIE_TIE3_Pos                     (3U)
#define FDCAN_TXBTIE_TIE3_Msk                     (0x1UL<<FDCAN_TXBTIE_TIE3_Pos)                    /*!< 0x00000008 */
#define FDCAN_TXBTIE_TIE3                         FDCAN_TXBTIE_TIE3_Msk                             /*!< Transmission Interrupt Enable */
#define FDCAN_TXBTIE_TIE4_Pos                     (4U)
#define FDCAN_TXBTIE_TIE4_Msk                     (0x1UL<<FDCAN_TXBTIE_TIE4_Pos)                    /*!< 0x00000010 */
#define FDCAN_TXBTIE_TIE4                         FDCAN_TXBTIE_TIE4_Msk                             /*!< Transmission Interrupt Enable */
#define FDCAN_TXBTIE_TIE5_Pos                     (5U)
#define FDCAN_TXBTIE_TIE5_Msk                     (0x1UL<<FDCAN_TXBTIE_TIE5_Pos)                    /*!< 0x00000020 */
#define FDCAN_TXBTIE_TIE5                         FDCAN_TXBTIE_TIE5_Msk                             /*!< Transmission Interrupt Enable */
#define FDCAN_TXBTIE_TIE6_Pos                     (6U)
#define FDCAN_TXBTIE_TIE6_Msk                     (0x1UL<<FDCAN_TXBTIE_TIE6_Pos)                    /*!< 0x00000040 */
#define FDCAN_TXBTIE_TIE6                         FDCAN_TXBTIE_TIE6_Msk                             /*!< Transmission Interrupt Enable */
#define FDCAN_TXBTIE_TIE7_Pos                     (7U)
#define FDCAN_TXBTIE_TIE7_Msk                     (0x1UL<<FDCAN_TXBTIE_TIE7_Pos)                    /*!< 0x00000080 */
#define FDCAN_TXBTIE_TIE7                         FDCAN_TXBTIE_TIE7_Msk                             /*!< Transmission Interrupt Enable */
#define FDCAN_TXBTIE_TIE8_Pos                     (8U)
#define FDCAN_TXBTIE_TIE8_Msk                     (0x1UL<<FDCAN_TXBTIE_TIE8_Pos)                    /*!< 0x00000100 */
#define FDCAN_TXBTIE_TIE8                         FDCAN_TXBTIE_TIE8_Msk                             /*!< Transmission Interrupt Enable */
#define FDCAN_TXBTIE_TIE9_Pos                     (9U)
#define FDCAN_TXBTIE_TIE9_Msk                     (0x1UL<<FDCAN_TXBTIE_TIE9_Pos)                    /*!< 0x00000200 */
#define FDCAN_TXBTIE_TIE9                         FDCAN_TXBTIE_TIE9_Msk                             /*!< Transmission Interrupt Enable */
#define FDCAN_TXBTIE_TIE10_Pos                    (10U)
#define FDCAN_TXBTIE_TIE10_Msk                    (0x1UL<<FDCAN_TXBTIE_TIE10_Pos)                   /*!< 0x00000400 */
#define FDCAN_TXBTIE_TIE10                        FDCAN_TXBTIE_TIE10_Msk                            /*!< Transmission Interrupt Enable */
#define FDCAN_TXBTIE_TIE11_Pos                    (11U)
#define FDCAN_TXBTIE_TIE11_Msk                    (0x1UL<<FDCAN_TXBTIE_TIE11_Pos)                   /*!< 0x00000800 */
#define FDCAN_TXBTIE_TIE11                        FDCAN_TXBTIE_TIE11_Msk                            /*!< Transmission Interrupt Enable */
#define FDCAN_TXBTIE_TIE12_Pos                    (12U)
#define FDCAN_TXBTIE_TIE12_Msk                    (0x1UL<<FDCAN_TXBTIE_TIE12_Pos)                   /*!< 0x00001000 */
#define FDCAN_TXBTIE_TIE12                        FDCAN_TXBTIE_TIE12_Msk                            /*!< Transmission Interrupt Enable */
#define FDCAN_TXBTIE_TIE13_Pos                    (13U)
#define FDCAN_TXBTIE_TIE13_Msk                    (0x1UL<<FDCAN_TXBTIE_TIE13_Pos)                   /*!< 0x00002000 */
#define FDCAN_TXBTIE_TIE13                        FDCAN_TXBTIE_TIE13_Msk                            /*!< Transmission Interrupt Enable */
#define FDCAN_TXBTIE_TIE14_Pos                    (14U)
#define FDCAN_TXBTIE_TIE14_Msk                    (0x1UL<<FDCAN_TXBTIE_TIE14_Pos)                   /*!< 0x00004000 */
#define FDCAN_TXBTIE_TIE14                        FDCAN_TXBTIE_TIE14_Msk                            /*!< Transmission Interrupt Enable */
#define FDCAN_TXBTIE_TIE15_Pos                    (15U)
#define FDCAN_TXBTIE_TIE15_Msk                    (0x1UL<<FDCAN_TXBTIE_TIE15_Pos)                   /*!< 0x00008000 */
#define FDCAN_TXBTIE_TIE15                        FDCAN_TXBTIE_TIE15_Msk                            /*!< Transmission Interrupt Enable */
#define FDCAN_TXBTIE_TIE16_Pos                    (16U)
#define FDCAN_TXBTIE_TIE16_Msk                    (0x1UL<<FDCAN_TXBTIE_TIE16_Pos)                   /*!< 0x00010000 */
#define FDCAN_TXBTIE_TIE16                        FDCAN_TXBTIE_TIE16_Msk                            /*!< Transmission Interrupt Enable */
#define FDCAN_TXBTIE_TIE17_Pos                    (17U)
#define FDCAN_TXBTIE_TIE17_Msk                    (0x1UL<<FDCAN_TXBTIE_TIE17_Pos)                   /*!< 0x00020000 */
#define FDCAN_TXBTIE_TIE17                        FDCAN_TXBTIE_TIE17_Msk                            /*!< Transmission Interrupt Enable */
#define FDCAN_TXBTIE_TIE18_Pos                    (18U)
#define FDCAN_TXBTIE_TIE18_Msk                    (0x1UL<<FDCAN_TXBTIE_TIE18_Pos)                   /*!< 0x00040000 */
#define FDCAN_TXBTIE_TIE18                        FDCAN_TXBTIE_TIE18_Msk                            /*!< Transmission Interrupt Enable */
#define FDCAN_TXBTIE_TIE19_Pos                    (19U)
#define FDCAN_TXBTIE_TIE19_Msk                    (0x1UL<<FDCAN_TXBTIE_TIE19_Pos)                   /*!< 0x00080000 */
#define FDCAN_TXBTIE_TIE19                        FDCAN_TXBTIE_TIE19_Msk                            /*!< Transmission Interrupt Enable */
#define FDCAN_TXBTIE_TIE20_Pos                    (20U)
#define FDCAN_TXBTIE_TIE20_Msk                    (0x1UL<<FDCAN_TXBTIE_TIE20_Pos)                   /*!< 0x00100000 */
#define FDCAN_TXBTIE_TIE20                        FDCAN_TXBTIE_TIE20_Msk                            /*!< Transmission Interrupt Enable */
#define FDCAN_TXBTIE_TIE21_Pos                    (21U)
#define FDCAN_TXBTIE_TIE21_Msk                    (0x1UL<<FDCAN_TXBTIE_TIE21_Pos)                   /*!< 0x00200000 */
#define FDCAN_TXBTIE_TIE21                        FDCAN_TXBTIE_TIE21_Msk                            /*!< Transmission Interrupt Enable */
#define FDCAN_TXBTIE_TIE22_Pos                    (22U)
#define FDCAN_TXBTIE_TIE22_Msk                    (0x1UL<<FDCAN_TXBTIE_TIE22_Pos)                   /*!< 0x00400000 */
#define FDCAN_TXBTIE_TIE22                        FDCAN_TXBTIE_TIE22_Msk                            /*!< Transmission Interrupt Enable */
#define FDCAN_TXBTIE_TIE23_Pos                    (23U)
#define FDCAN_TXBTIE_TIE23_Msk                    (0x1UL<<FDCAN_TXBTIE_TIE23_Pos)                   /*!< 0x00800000 */
#define FDCAN_TXBTIE_TIE23                        FDCAN_TXBTIE_TIE23_Msk                            /*!< Transmission Interrupt Enable */
#define FDCAN_TXBTIE_TIE24_Pos                    (24U)
#define FDCAN_TXBTIE_TIE24_Msk                    (0x1UL<<FDCAN_TXBTIE_TIE24_Pos)                   /*!< 0x01000000 */
#define FDCAN_TXBTIE_TIE24                        FDCAN_TXBTIE_TIE24_Msk                            /*!< Transmission Interrupt Enable */
#define FDCAN_TXBTIE_TIE25_Pos                    (25U)
#define FDCAN_TXBTIE_TIE25_Msk                    (0x1UL<<FDCAN_TXBTIE_TIE25_Pos)                   /*!< 0x02000000 */
#define FDCAN_TXBTIE_TIE25                        FDCAN_TXBTIE_TIE25_Msk                            /*!< Transmission Interrupt Enable */
#define FDCAN_TXBTIE_TIE26_Pos                    (26U)
#define FDCAN_TXBTIE_TIE26_Msk                    (0x1UL<<FDCAN_TXBTIE_TIE26_Pos)                   /*!< 0x04000000 */
#define FDCAN_TXBTIE_TIE26                        FDCAN_TXBTIE_TIE26_Msk                            /*!< Transmission Interrupt Enable */
#define FDCAN_TXBTIE_TIE27_Pos                    (27U)
#define FDCAN_TXBTIE_TIE27_Msk                    (0x1UL<<FDCAN_TXBTIE_TIE27_Pos)                   /*!< 0x08000000 */
#define FDCAN_TXBTIE_TIE27                        FDCAN_TXBTIE_TIE27_Msk                            /*!< Transmission Interrupt Enable */
#define FDCAN_TXBTIE_TIE28_Pos                    (28U)
#define FDCAN_TXBTIE_TIE28_Msk                    (0x1UL<<FDCAN_TXBTIE_TIE28_Pos)                   /*!< 0x10000000 */
#define FDCAN_TXBTIE_TIE28                        FDCAN_TXBTIE_TIE28_Msk                            /*!< Transmission Interrupt Enable */
#define FDCAN_TXBTIE_TIE29_Pos                    (29U)
#define FDCAN_TXBTIE_TIE29_Msk                    (0x1UL<<FDCAN_TXBTIE_TIE29_Pos)                   /*!< 0x20000000 */
#define FDCAN_TXBTIE_TIE29                        FDCAN_TXBTIE_TIE29_Msk                            /*!< Transmission Interrupt Enable */
#define FDCAN_TXBTIE_TIE30_Pos                    (30U)
#define FDCAN_TXBTIE_TIE30_Msk                    (0x1UL<<FDCAN_TXBTIE_TIE30_Pos)                   /*!< 0x40000000 */
#define FDCAN_TXBTIE_TIE30                        FDCAN_TXBTIE_TIE30_Msk                            /*!< Transmission Interrupt Enable */
#define FDCAN_TXBTIE_TIE31_Pos                    (31U)
#define FDCAN_TXBTIE_TIE31_Msk                    (0x1UL<<FDCAN_TXBTIE_TIE31_Pos)                   /*!< 0x80000000 */
#define FDCAN_TXBTIE_TIE31                        FDCAN_TXBTIE_TIE31_Msk                            /*!< Transmission Interrupt Enable */

/********************************* Bit definition for FDCAN_TXBCIE register *****************************************/
#define FDCAN_TXBCIE_CFIE0_Pos                    (0U)
#define FDCAN_TXBCIE_CFIE0_Msk                    (0x1UL<<FDCAN_TXBCIE_CFIE0_Pos)                   /*!< 0x00000001 */
#define FDCAN_TXBCIE_CFIE0                        FDCAN_TXBCIE_CFIE0_Msk                            /*!< Cancellation Finished Interrupt Enable */
#define FDCAN_TXBCIE_CFIE1_Pos                    (1U)
#define FDCAN_TXBCIE_CFIE1_Msk                    (0x1UL<<FDCAN_TXBCIE_CFIE1_Pos)                   /*!< 0x00000002 */
#define FDCAN_TXBCIE_CFIE1                        FDCAN_TXBCIE_CFIE1_Msk                            /*!< Cancellation Finished Interrupt Enable */
#define FDCAN_TXBCIE_CFIE2_Pos                    (2U)
#define FDCAN_TXBCIE_CFIE2_Msk                    (0x1UL<<FDCAN_TXBCIE_CFIE2_Pos)                   /*!< 0x00000004 */
#define FDCAN_TXBCIE_CFIE2                        FDCAN_TXBCIE_CFIE2_Msk                            /*!< Cancellation Finished Interrupt Enable */
#define FDCAN_TXBCIE_CFIE3_Pos                    (3U)
#define FDCAN_TXBCIE_CFIE3_Msk                    (0x1UL<<FDCAN_TXBCIE_CFIE3_Pos)                   /*!< 0x00000008 */
#define FDCAN_TXBCIE_CFIE3                        FDCAN_TXBCIE_CFIE3_Msk                            /*!< Cancellation Finished Interrupt Enable */
#define FDCAN_TXBCIE_CFIE4_Pos                    (4U)
#define FDCAN_TXBCIE_CFIE4_Msk                    (0x1UL<<FDCAN_TXBCIE_CFIE4_Pos)                   /*!< 0x00000010 */
#define FDCAN_TXBCIE_CFIE4                        FDCAN_TXBCIE_CFIE4_Msk                            /*!< Cancellation Finished Interrupt Enable */
#define FDCAN_TXBCIE_CFIE5_Pos                    (5U)
#define FDCAN_TXBCIE_CFIE5_Msk                    (0x1UL<<FDCAN_TXBCIE_CFIE5_Pos)                   /*!< 0x00000020 */
#define FDCAN_TXBCIE_CFIE5                        FDCAN_TXBCIE_CFIE5_Msk                            /*!< Cancellation Finished Interrupt Enable */
#define FDCAN_TXBCIE_CFIE6_Pos                    (6U)
#define FDCAN_TXBCIE_CFIE6_Msk                    (0x1UL<<FDCAN_TXBCIE_CFIE6_Pos)                   /*!< 0x00000040 */
#define FDCAN_TXBCIE_CFIE6                        FDCAN_TXBCIE_CFIE6_Msk                            /*!< Cancellation Finished Interrupt Enable */
#define FDCAN_TXBCIE_CFIE7_Pos                    (7U)
#define FDCAN_TXBCIE_CFIE7_Msk                    (0x1UL<<FDCAN_TXBCIE_CFIE7_Pos)                   /*!< 0x00000080 */
#define FDCAN_TXBCIE_CFIE7                        FDCAN_TXBCIE_CFIE7_Msk                            /*!< Cancellation Finished Interrupt Enable */
#define FDCAN_TXBCIE_CFIE8_Pos                    (8U)
#define FDCAN_TXBCIE_CFIE8_Msk                    (0x1UL<<FDCAN_TXBCIE_CFIE8_Pos)                   /*!< 0x00000100 */
#define FDCAN_TXBCIE_CFIE8                        FDCAN_TXBCIE_CFIE8_Msk                            /*!< Cancellation Finished Interrupt Enable */
#define FDCAN_TXBCIE_CFIE9_Pos                    (9U)
#define FDCAN_TXBCIE_CFIE9_Msk                    (0x1UL<<FDCAN_TXBCIE_CFIE9_Pos)                   /*!< 0x00000200 */
#define FDCAN_TXBCIE_CFIE9                        FDCAN_TXBCIE_CFIE9_Msk                            /*!< Cancellation Finished Interrupt Enable */
#define FDCAN_TXBCIE_CFIE10_Pos                   (10U)
#define FDCAN_TXBCIE_CFIE10_Msk                   (0x1UL<<FDCAN_TXBCIE_CFIE10_Pos)                  /*!< 0x00000400 */
#define FDCAN_TXBCIE_CFIE10                       FDCAN_TXBCIE_CFIE10_Msk                           /*!< Cancellation Finished Interrupt Enable */
#define FDCAN_TXBCIE_CFIE11_Pos                   (11U)
#define FDCAN_TXBCIE_CFIE11_Msk                   (0x1UL<<FDCAN_TXBCIE_CFIE11_Pos)                  /*!< 0x00000800 */
#define FDCAN_TXBCIE_CFIE11                       FDCAN_TXBCIE_CFIE11_Msk                           /*!< Cancellation Finished Interrupt Enable */
#define FDCAN_TXBCIE_CFIE12_Pos                   (12U)
#define FDCAN_TXBCIE_CFIE12_Msk                   (0x1UL<<FDCAN_TXBCIE_CFIE12_Pos)                  /*!< 0x00001000 */
#define FDCAN_TXBCIE_CFIE12                       FDCAN_TXBCIE_CFIE12_Msk                           /*!< Cancellation Finished Interrupt Enable */
#define FDCAN_TXBCIE_CFIE13_Pos                   (13U)
#define FDCAN_TXBCIE_CFIE13_Msk                   (0x1UL<<FDCAN_TXBCIE_CFIE13_Pos)                  /*!< 0x00002000 */
#define FDCAN_TXBCIE_CFIE13                       FDCAN_TXBCIE_CFIE13_Msk                           /*!< Cancellation Finished Interrupt Enable */
#define FDCAN_TXBCIE_CFIE14_Pos                   (14U)
#define FDCAN_TXBCIE_CFIE14_Msk                   (0x1UL<<FDCAN_TXBCIE_CFIE14_Pos)                  /*!< 0x00004000 */
#define FDCAN_TXBCIE_CFIE14                       FDCAN_TXBCIE_CFIE14_Msk                           /*!< Cancellation Finished Interrupt Enable */
#define FDCAN_TXBCIE_CFIE15_Pos                   (15U)
#define FDCAN_TXBCIE_CFIE15_Msk                   (0x1UL<<FDCAN_TXBCIE_CFIE15_Pos)                  /*!< 0x00008000 */
#define FDCAN_TXBCIE_CFIE15                       FDCAN_TXBCIE_CFIE15_Msk                           /*!< Cancellation Finished Interrupt Enable */
#define FDCAN_TXBCIE_CFIE16_Pos                   (16U)
#define FDCAN_TXBCIE_CFIE16_Msk                   (0x1UL<<FDCAN_TXBCIE_CFIE16_Pos)                  /*!< 0x00010000 */
#define FDCAN_TXBCIE_CFIE16                       FDCAN_TXBCIE_CFIE16_Msk                           /*!< Cancellation Finished Interrupt Enable */
#define FDCAN_TXBCIE_CFIE17_Pos                   (17U)
#define FDCAN_TXBCIE_CFIE17_Msk                   (0x1UL<<FDCAN_TXBCIE_CFIE17_Pos)                  /*!< 0x00020000 */
#define FDCAN_TXBCIE_CFIE17                       FDCAN_TXBCIE_CFIE17_Msk                           /*!< Cancellation Finished Interrupt Enable */
#define FDCAN_TXBCIE_CFIE18_Pos                   (18U)
#define FDCAN_TXBCIE_CFIE18_Msk                   (0x1UL<<FDCAN_TXBCIE_CFIE18_Pos)                  /*!< 0x00040000 */
#define FDCAN_TXBCIE_CFIE18                       FDCAN_TXBCIE_CFIE18_Msk                           /*!< Cancellation Finished Interrupt Enable */
#define FDCAN_TXBCIE_CFIE19_Pos                   (19U)
#define FDCAN_TXBCIE_CFIE19_Msk                   (0x1UL<<FDCAN_TXBCIE_CFIE19_Pos)                  /*!< 0x00080000 */
#define FDCAN_TXBCIE_CFIE19                       FDCAN_TXBCIE_CFIE19_Msk                           /*!< Cancellation Finished Interrupt Enable */
#define FDCAN_TXBCIE_CFIE20_Pos                   (20U)
#define FDCAN_TXBCIE_CFIE20_Msk                   (0x1UL<<FDCAN_TXBCIE_CFIE20_Pos)                  /*!< 0x00100000 */
#define FDCAN_TXBCIE_CFIE20                       FDCAN_TXBCIE_CFIE20_Msk                           /*!< Cancellation Finished Interrupt Enable */
#define FDCAN_TXBCIE_CFIE21_Pos                   (21U)
#define FDCAN_TXBCIE_CFIE21_Msk                   (0x1UL<<FDCAN_TXBCIE_CFIE21_Pos)                  /*!< 0x00200000 */
#define FDCAN_TXBCIE_CFIE21                       FDCAN_TXBCIE_CFIE21_Msk                           /*!< Cancellation Finished Interrupt Enable */
#define FDCAN_TXBCIE_CFIE22_Pos                   (22U)
#define FDCAN_TXBCIE_CFIE22_Msk                   (0x1UL<<FDCAN_TXBCIE_CFIE22_Pos)                  /*!< 0x00400000 */
#define FDCAN_TXBCIE_CFIE22                       FDCAN_TXBCIE_CFIE22_Msk                           /*!< Cancellation Finished Interrupt Enable */
#define FDCAN_TXBCIE_CFIE23_Pos                   (23U)
#define FDCAN_TXBCIE_CFIE23_Msk                   (0x1UL<<FDCAN_TXBCIE_CFIE23_Pos)                  /*!< 0x00800000 */
#define FDCAN_TXBCIE_CFIE23                       FDCAN_TXBCIE_CFIE23_Msk                           /*!< Cancellation Finished Interrupt Enable */
#define FDCAN_TXBCIE_CFIE24_Pos                   (24U)
#define FDCAN_TXBCIE_CFIE24_Msk                   (0x1UL<<FDCAN_TXBCIE_CFIE24_Pos)                  /*!< 0x01000000 */
#define FDCAN_TXBCIE_CFIE24                       FDCAN_TXBCIE_CFIE24_Msk                           /*!< Cancellation Finished Interrupt Enable */
#define FDCAN_TXBCIE_CFIE25_Pos                   (25U)
#define FDCAN_TXBCIE_CFIE25_Msk                   (0x1UL<<FDCAN_TXBCIE_CFIE25_Pos)                  /*!< 0x02000000 */
#define FDCAN_TXBCIE_CFIE25                       FDCAN_TXBCIE_CFIE25_Msk                           /*!< Cancellation Finished Interrupt Enable */
#define FDCAN_TXBCIE_CFIE26_Pos                   (26U)
#define FDCAN_TXBCIE_CFIE26_Msk                   (0x1UL<<FDCAN_TXBCIE_CFIE26_Pos)                  /*!< 0x04000000 */
#define FDCAN_TXBCIE_CFIE26                       FDCAN_TXBCIE_CFIE26_Msk                           /*!< Cancellation Finished Interrupt Enable */
#define FDCAN_TXBCIE_CFIE27_Pos                   (27U)
#define FDCAN_TXBCIE_CFIE27_Msk                   (0x1UL<<FDCAN_TXBCIE_CFIE27_Pos)                  /*!< 0x08000000 */
#define FDCAN_TXBCIE_CFIE27                       FDCAN_TXBCIE_CFIE27_Msk                           /*!< Cancellation Finished Interrupt Enable */
#define FDCAN_TXBCIE_CFIE28_Pos                   (28U)
#define FDCAN_TXBCIE_CFIE28_Msk                   (0x1UL<<FDCAN_TXBCIE_CFIE28_Pos)                  /*!< 0x10000000 */
#define FDCAN_TXBCIE_CFIE28                       FDCAN_TXBCIE_CFIE28_Msk                           /*!< Cancellation Finished Interrupt Enable */
#define FDCAN_TXBCIE_CFIE29_Pos                   (29U)
#define FDCAN_TXBCIE_CFIE29_Msk                   (0x1UL<<FDCAN_TXBCIE_CFIE29_Pos)                  /*!< 0x20000000 */
#define FDCAN_TXBCIE_CFIE29                       FDCAN_TXBCIE_CFIE29_Msk                           /*!< Cancellation Finished Interrupt Enable */
#define FDCAN_TXBCIE_CFIE30_Pos                   (30U)
#define FDCAN_TXBCIE_CFIE30_Msk                   (0x1UL<<FDCAN_TXBCIE_CFIE30_Pos)                  /*!< 0x40000000 */
#define FDCAN_TXBCIE_CFIE30                       FDCAN_TXBCIE_CFIE30_Msk                           /*!< Cancellation Finished Interrupt Enable */
#define FDCAN_TXBCIE_CFIE31_Pos                   (31U)
#define FDCAN_TXBCIE_CFIE31_Msk                   (0x1UL<<FDCAN_TXBCIE_CFIE31_Pos)                  /*!< 0x80000000 */
#define FDCAN_TXBCIE_CFIE31                       FDCAN_TXBCIE_CFIE31_Msk                           /*!< Cancellation Finished Interrupt Enable */

/********************************* Bit definition for FDCAN_TXEFC register ******************************************/
#define FDCAN_TXEFC_EFSA_Pos                      (2U)
#define FDCAN_TXEFC_EFSA_Msk                      (0x3FFFUL<<FDCAN_TXEFC_EFSA_Pos)                  /*!< 0x0000FFFC */
#define FDCAN_TXEFC_EFSA                          FDCAN_TXEFC_EFSA_Msk                              /*!< Event FIFO Start Address */
#define FDCAN_TXEFC_EFS_Pos                       (16U)
#define FDCAN_TXEFC_EFS_Msk                       (0x3FUL<<FDCAN_TXEFC_EFS_Pos)                     /*!< 0x003F0000 */
#define FDCAN_TXEFC_EFS                           FDCAN_TXEFC_EFS_Msk                               /*!< Event FIFO Size */
#define FDCAN_TXEFC_EFS_0                         (0x1UL<<FDCAN_TXEFC_EFS_Pos)                      /*!< 0x00010000 */
#define FDCAN_TXEFC_EFS_1                         (0x2UL<<FDCAN_TXEFC_EFS_Pos)                      /*!< 0x00020000 */
#define FDCAN_TXEFC_EFS_2                         (0x4UL<<FDCAN_TXEFC_EFS_Pos)                      /*!< 0x00040000 */
#define FDCAN_TXEFC_EFS_3                         (0x8UL<<FDCAN_TXEFC_EFS_Pos)                      /*!< 0x00080000 */
#define FDCAN_TXEFC_EFS_4                         (0x10UL<<FDCAN_TXEFC_EFS_Pos)                     /*!< 0x00100000 */
#define FDCAN_TXEFC_EFS_5                         (0x20UL<<FDCAN_TXEFC_EFS_Pos)                     /*!< 0x00200000 */
#define FDCAN_TXEFC_EFWM_Pos                      (24U)
#define FDCAN_TXEFC_EFWM_Msk                      (0x3FUL<<FDCAN_TXEFC_EFWM_Pos)                    /*!< 0x3F000000 */
#define FDCAN_TXEFC_EFWM                          FDCAN_TXEFC_EFWM_Msk                              /*!< Event FIFO Watermark */
#define FDCAN_TXEFC_EFWM_0                        (0x1UL<<FDCAN_TXEFC_EFWM_Pos)                     /*!< 0x01000000 */
#define FDCAN_TXEFC_EFWM_1                        (0x2UL<<FDCAN_TXEFC_EFWM_Pos)                     /*!< 0x02000000 */
#define FDCAN_TXEFC_EFWM_2                        (0x4UL<<FDCAN_TXEFC_EFWM_Pos)                     /*!< 0x04000000 */
#define FDCAN_TXEFC_EFWM_3                        (0x8UL<<FDCAN_TXEFC_EFWM_Pos)                     /*!< 0x08000000 */
#define FDCAN_TXEFC_EFWM_4                        (0x10UL<<FDCAN_TXEFC_EFWM_Pos)                    /*!< 0x10000000 */
#define FDCAN_TXEFC_EFWM_5                        (0x20UL<<FDCAN_TXEFC_EFWM_Pos)                    /*!< 0x20000000 */

/********************************* Bit definition for FDCAN_TXEFS register ******************************************/
#define FDCAN_TXEFS_EFFL_Pos                      (0U)
#define FDCAN_TXEFS_EFFL_Msk                      (0x3FUL<<FDCAN_TXEFS_EFFL_Pos)                    /*!< 0x0000003F */
#define FDCAN_TXEFS_EFFL                          FDCAN_TXEFS_EFFL_Msk                              /*!< Event FIFO Fill Level */
#define FDCAN_TXEFS_EFFL_0                        (0x1UL<<FDCAN_TXEFS_EFFL_Pos)                     /*!< 0x00000001 */
#define FDCAN_TXEFS_EFFL_1                        (0x2UL<<FDCAN_TXEFS_EFFL_Pos)                     /*!< 0x00000002 */
#define FDCAN_TXEFS_EFFL_2                        (0x4UL<<FDCAN_TXEFS_EFFL_Pos)                     /*!< 0x00000004 */
#define FDCAN_TXEFS_EFFL_3                        (0x8UL<<FDCAN_TXEFS_EFFL_Pos)                     /*!< 0x00000008 */
#define FDCAN_TXEFS_EFFL_4                        (0x10UL<<FDCAN_TXEFS_EFFL_Pos)                    /*!< 0x00000010 */
#define FDCAN_TXEFS_EFFL_5                        (0x20UL<<FDCAN_TXEFS_EFFL_Pos)                    /*!< 0x00000020 */
#define FDCAN_TXEFS_EFGI_Pos                      (8U)
#define FDCAN_TXEFS_EFGI_Msk                      (0x1FUL<<FDCAN_TXEFS_EFGI_Pos)                    /*!< 0x00001F00 */
#define FDCAN_TXEFS_EFGI                          FDCAN_TXEFS_EFGI_Msk                              /*!< Event FIFO Get Index */
#define FDCAN_TXEFS_EFGI_0                        (0x1UL<<FDCAN_TXEFS_EFGI_Pos)                     /*!< 0x00000100 */
#define FDCAN_TXEFS_EFGI_1                        (0x2UL<<FDCAN_TXEFS_EFGI_Pos)                     /*!< 0x00000200 */
#define FDCAN_TXEFS_EFGI_2                        (0x4UL<<FDCAN_TXEFS_EFGI_Pos)                     /*!< 0x00000400 */
#define FDCAN_TXEFS_EFGI_3                        (0x8UL<<FDCAN_TXEFS_EFGI_Pos)                     /*!< 0x00000800 */
#define FDCAN_TXEFS_EFGI_4                        (0x10UL<<FDCAN_TXEFS_EFGI_Pos)                    /*!< 0x00001000 */
#define FDCAN_TXEFS_EFPI_Pos                      (16U)
#define FDCAN_TXEFS_EFPI_Msk                      (0x1FUL<<FDCAN_TXEFS_EFPI_Pos)                    /*!< 0x001F0000 */
#define FDCAN_TXEFS_EFPI                          FDCAN_TXEFS_EFPI_Msk                              /*!< Event FIFO Put Index */
#define FDCAN_TXEFS_EFPI_0                        (0x1UL<<FDCAN_TXEFS_EFPI_Pos)                     /*!< 0x00010000 */
#define FDCAN_TXEFS_EFPI_1                        (0x2UL<<FDCAN_TXEFS_EFPI_Pos)                     /*!< 0x00020000 */
#define FDCAN_TXEFS_EFPI_2                        (0x4UL<<FDCAN_TXEFS_EFPI_Pos)                     /*!< 0x00040000 */
#define FDCAN_TXEFS_EFPI_3                        (0x8UL<<FDCAN_TXEFS_EFPI_Pos)                     /*!< 0x00080000 */
#define FDCAN_TXEFS_EFPI_4                        (0x10UL<<FDCAN_TXEFS_EFPI_Pos)                    /*!< 0x00100000 */
#define FDCAN_TXEFS_EFF_Pos                       (24U)
#define FDCAN_TXEFS_EFF_Msk                       (0x1UL<<FDCAN_TXEFS_EFF_Pos)                      /*!< 0x01000000 */
#define FDCAN_TXEFS_EFF                           FDCAN_TXEFS_EFF_Msk                               /*!< Event FIFO Full */
#define FDCAN_TXEFS_TEFL_Pos                      (25U)
#define FDCAN_TXEFS_TEFL_Msk                      (0x1UL<<FDCAN_TXEFS_TEFL_Pos)                     /*!< 0x02000000 */
#define FDCAN_TXEFS_TEFL                          FDCAN_TXEFS_TEFL_Msk                              /*!< Tx Event FIFO Element Lost */

/********************************* Bit definition for FDCAN_TXEFA register ******************************************/
#define FDCAN_TXEFA_EFAI_Pos                      (0U)
#define FDCAN_TXEFA_EFAI_Msk                      (0x1FUL<<FDCAN_TXEFA_EFAI_Pos)                    /*!< 0x0000001F */
#define FDCAN_TXEFA_EFAI                          FDCAN_TXEFA_EFAI_Msk                              /*!< Event FIFO Acknowledge Index */
#define FDCAN_TXEFA_EFAI_0                        (0x1UL<<FDCAN_TXEFA_EFAI_Pos)                     /*!< 0x00000001 */
#define FDCAN_TXEFA_EFAI_1                        (0x2UL<<FDCAN_TXEFA_EFAI_Pos)                     /*!< 0x00000002 */
#define FDCAN_TXEFA_EFAI_2                        (0x4UL<<FDCAN_TXEFA_EFAI_Pos)                     /*!< 0x00000004 */
#define FDCAN_TXEFA_EFAI_3                        (0x8UL<<FDCAN_TXEFA_EFAI_Pos)                     /*!< 0x00000008 */
#define FDCAN_TXEFA_EFAI_4                        (0x10UL<<FDCAN_TXEFA_EFAI_Pos)                    /*!< 0x00000010 */

/********************************************************************************************************************/
/********************************* I2C ******************************************************************************/
/********************************************************************************************************************/

/********************************* Bit definition for I2C_CR1 register **********************************************/
#define I2C_CR1_PE_Pos                            (0U)
#define I2C_CR1_PE_Msk                            (0x1UL<<I2C_CR1_PE_Pos)                           /*!< 0x00000001 */
#define I2C_CR1_PE                                I2C_CR1_PE_Msk                                    /*!< Peripheral enable */
#define I2C_CR1_SMBUS_Pos                         (1U)
#define I2C_CR1_SMBUS_Msk                         (0x1UL<<I2C_CR1_SMBUS_Pos)                        /*!< 0x00000002 */
#define I2C_CR1_SMBUS                             I2C_CR1_SMBUS_Msk                                 /*!< SMBus mode */
#define I2C_CR1_WUPEN_Pos                         (2U)
#define I2C_CR1_WUPEN_Msk                         (0x1UL<<I2C_CR1_WUPEN_Pos)                        /*!< 0x00000004 */
#define I2C_CR1_WUPEN                             I2C_CR1_WUPEN_Msk                                 /*!< Wakeup from Stop mode enable */
#define I2C_CR1_SMBTYPE_Pos                       (3U)
#define I2C_CR1_SMBTYPE_Msk                       (0x1UL<<I2C_CR1_SMBTYPE_Pos)                      /*!< 0x00000008 */
#define I2C_CR1_SMBTYPE                           I2C_CR1_SMBTYPE_Msk                               /*!< SMBus type */
#define I2C_CR1_ENARP_Pos                         (4U)
#define I2C_CR1_ENARP_Msk                         (0x1UL<<I2C_CR1_ENARP_Pos)                        /*!< 0x00000010 */
#define I2C_CR1_ENARP                             I2C_CR1_ENARP_Msk                                 /*!< ARP enable */
#define I2C_CR1_ENPEC_Pos                         (5U)
#define I2C_CR1_ENPEC_Msk                         (0x1UL<<I2C_CR1_ENPEC_Pos)                        /*!< 0x00000020 */
#define I2C_CR1_ENPEC                             I2C_CR1_ENPEC_Msk                                 /*!< PEC enable */
#define I2C_CR1_ENGC_Pos                          (6U)
#define I2C_CR1_ENGC_Msk                          (0x1UL<<I2C_CR1_ENGC_Pos)                         /*!< 0x00000040 */
#define I2C_CR1_ENGC                              I2C_CR1_ENGC_Msk                                  /*!< General call enable */
#define I2C_CR1_NOSTRETCH_Pos                     (7U)
#define I2C_CR1_NOSTRETCH_Msk                     (0x1UL<<I2C_CR1_NOSTRETCH_Pos)                    /*!< 0x00000080 */
#define I2C_CR1_NOSTRETCH                         I2C_CR1_NOSTRETCH_Msk                             /*!< Clock stretching disable (Slave mode) */
#define I2C_CR1_START_Pos                         (8U)
#define I2C_CR1_START_Msk                         (0x1UL<<I2C_CR1_START_Pos)                        /*!< 0x00000100 */
#define I2C_CR1_START                             I2C_CR1_START_Msk                                 /*!< Start generation */
#define I2C_CR1_STOP_Pos                          (9U)
#define I2C_CR1_STOP_Msk                          (0x1UL<<I2C_CR1_STOP_Pos)                         /*!< 0x00000200 */
#define I2C_CR1_STOP                              I2C_CR1_STOP_Msk                                  /*!< Stop generation */
#define I2C_CR1_ACK_Pos                           (10U)
#define I2C_CR1_ACK_Msk                           (0x1UL<<I2C_CR1_ACK_Pos)                          /*!< 0x00000400 */
#define I2C_CR1_ACK                               I2C_CR1_ACK_Msk                                   /*!< Acknowledge enable */
#define I2C_CR1_POS_Pos                           (11U)
#define I2C_CR1_POS_Msk                           (0x1UL<<I2C_CR1_POS_Pos)                          /*!< 0x00000800 */
#define I2C_CR1_POS                               I2C_CR1_POS_Msk                                   /*!< Acknowledge(for data reception) */
#define I2C_CR1_PEC_Pos                           (12U)
#define I2C_CR1_PEC_Msk                           (0x1UL<<I2C_CR1_PEC_Pos)                          /*!< 0x00001000 */
#define I2C_CR1_PEC                               I2C_CR1_PEC_Msk                                   /*!< Packet error checking */
#define I2C_CR1_ALERT_Pos                         (13U)
#define I2C_CR1_ALERT_Msk                         (0x1UL<<I2C_CR1_ALERT_Pos)                        /*!< 0x00002000 */
#define I2C_CR1_ALERT                             I2C_CR1_ALERT_Msk                                 /*!< SMBus alert */
#define I2C_CR1_SWRST_Pos                         (15U)
#define I2C_CR1_SWRST_Msk                         (0x1UL<<I2C_CR1_SWRST_Pos)                        /*!< 0x00008000 */
#define I2C_CR1_SWRST                             I2C_CR1_SWRST_Msk                                 /*!< Software reset */
#define I2C_CR1_WKUP_DIV_Pos                      (16U)
#define I2C_CR1_WKUP_DIV_Msk                      (0x3UL<<I2C_CR1_WKUP_DIV_Pos)                     /*!< 0x00030000 */
#define I2C_CR1_WKUP_DIV                          I2C_CR1_WKUP_DIV_Msk                              /*!< PCLK division */
#define I2C_CR1_WKUP_DIV_0                        (0x1UL<<I2C_CR1_WKUP_DIV_Pos)                     /*!< 0x00010000 */
#define I2C_CR1_WKUP_DIV_1                        (0x2UL<<I2C_CR1_WKUP_DIV_Pos)                     /*!< 0x00020000 */
#define I2C_CR1_WKUP_CNT_Pos                      (18U)
#define I2C_CR1_WKUP_CNT_Msk                      (0x3UL<<I2C_CR1_WKUP_CNT_Pos)                     /*!< 0x000C0000 */
#define I2C_CR1_WKUP_CNT                          I2C_CR1_WKUP_CNT_Msk                              /*!< Timeout count number */
#define I2C_CR1_WKUP_CNT_0                        (0x1UL<<I2C_CR1_WKUP_CNT_Pos)                     /*!< 0x00040000 */
#define I2C_CR1_WKUP_CNT_1                        (0x2UL<<I2C_CR1_WKUP_CNT_Pos)                     /*!< 0x00080000 */

/********************************* Bit definition for I2C_CR2 register **********************************************/
#define I2C_CR2_FREQ_Pos                          (0U)
#define I2C_CR2_FREQ_Msk                          (0xFFUL<<I2C_CR2_FREQ_Pos)                        /*!< 0x000000FF */
#define I2C_CR2_FREQ                              I2C_CR2_FREQ_Msk                                  /*!< Peripheral clock frequency */
#define I2C_CR2_ITERREN_Pos                       (8U)
#define I2C_CR2_ITERREN_Msk                       (0x1UL<<I2C_CR2_ITERREN_Pos)                      /*!< 0x00000100 */
#define I2C_CR2_ITERREN                           I2C_CR2_ITERREN_Msk                               /*!< Error interrupt enable */
#define I2C_CR2_DMAEN_Pos                         (11U)
#define I2C_CR2_DMAEN_Msk                         (0x1UL<<I2C_CR2_DMAEN_Pos)                        /*!< 0x00000800 */
#define I2C_CR2_DMAEN                             I2C_CR2_DMAEN_Msk                                 /*!< DMA requests enable */
#define I2C_CR2_LAST_Pos                          (12U)
#define I2C_CR2_LAST_Msk                          (0x1UL<<I2C_CR2_LAST_Pos)                         /*!< 0x00001000 */
#define I2C_CR2_LAST                              I2C_CR2_LAST_Msk                                  /*!< DMA last transfer */
#define I2C_CR2_SBIE_Pos                          (16U)
#define I2C_CR2_SBIE_Msk                          (0x1UL<<I2C_CR2_SBIE_Pos)                         /*!< 0x00010000 */
#define I2C_CR2_SBIE                              I2C_CR2_SBIE_Msk                                  /*!< Start bit (Master mode) interrupt enable */
#define I2C_CR2_ADDRIE_Pos                        (17U)
#define I2C_CR2_ADDRIE_Msk                        (0x1UL<<I2C_CR2_ADDRIE_Pos)                       /*!< 0x00020000 */
#define I2C_CR2_ADDRIE                            I2C_CR2_ADDRIE_Msk                                /*!< Address sent (master mode)/matched (slave mode)  interrupt enable */
#define I2C_CR2_BTFIE_Pos                         (18U)
#define I2C_CR2_BTFIE_Msk                         (0x1UL<<I2C_CR2_BTFIE_Pos)                        /*!< 0x00040000 */
#define I2C_CR2_BTFIE                             I2C_CR2_BTFIE_Msk                                 /*!< Byte transfer finished  interrupt enable */
#define I2C_CR2_ADD10IE_Pos                       (19U)
#define I2C_CR2_ADD10IE_Msk                       (0x1UL<<I2C_CR2_ADD10IE_Pos)                      /*!< 0x00080000 */
#define I2C_CR2_ADD10IE                           I2C_CR2_ADD10IE_Msk                               /*!< 10-bit header sent (Master mode)  interrupt enable */
#define I2C_CR2_STOPIE_Pos                        (20U)
#define I2C_CR2_STOPIE_Msk                        (0x1UL<<I2C_CR2_STOPIE_Pos)                       /*!< 0x00100000 */
#define I2C_CR2_STOPIE                            I2C_CR2_STOPIE_Msk                                /*!< Stop detection (slave mode)  interrupt enable */
#define I2C_CR2_RXIE_Pos                          (22U)
#define I2C_CR2_RXIE_Msk                          (0x1UL<<I2C_CR2_RXIE_Pos)                         /*!< 0x00400000 */
#define I2C_CR2_RXIE                              I2C_CR2_RXIE_Msk                                  /*!< Data register not empty (receivers)  interrupt enable */
#define I2C_CR2_TXIE_Pos                          (23U)
#define I2C_CR2_TXIE_Msk                          (0x1UL<<I2C_CR2_TXIE_Pos)                         /*!< 0x00800000 */
#define I2C_CR2_TXIE                              I2C_CR2_TXIE_Msk                                  /*!< Data register empty (transmitters)  interrupt enable */

/********************************* Bit definition for I2C_OAR1 register *********************************************/
#define I2C_OAR1_ADD_Pos                          (0U)
#define I2C_OAR1_ADD_Msk                          (0x3FFUL<<I2C_OAR1_ADD_Pos)                       /*!< 0x000003FF */
#define I2C_OAR1_ADD                              I2C_OAR1_ADD_Msk                                  /*!< Interface address */
#define I2C_OAR1_ADD0_Pos                         (0U)
#define I2C_OAR1_ADD0_Msk                         (0x1UL << I2C_OAR1_ADD0_Pos)                      /*!< 0x00000001 */
#define I2C_OAR1_ADD0                             I2C_OAR1_ADD0_Msk                                 /*!< desc ADD0 */
#define I2C_OAR1_ADD1_7                           0x000000FEU                                       /*!< Interface Address */
#define I2C_OAR1_ADD8_9                           0x00000300U                                       /*!< Interface Address */

#define I2C_OAR1_ADDMODE_Pos                      (15U)
#define I2C_OAR1_ADDMODE_Msk                      (0x1UL<<I2C_OAR1_ADDMODE_Pos)                     /*!< 0x00008000 */
#define I2C_OAR1_ADDMODE                          I2C_OAR1_ADDMODE_Msk                              /*!< Addressing mode (slave mode) */

/********************************* Bit definition for I2C_OAR2 register *********************************************/
#define I2C_OAR2_ENDUAL_Pos                       (0U)
#define I2C_OAR2_ENDUAL_Msk                       (0x1UL<<I2C_OAR2_ENDUAL_Pos)                      /*!< 0x00000001 */
#define I2C_OAR2_ENDUAL                           I2C_OAR2_ENDUAL_Msk                               /*!< Dual addressing mode enable */
#define I2C_OAR2_ADD2_Pos                         (1U)
#define I2C_OAR2_ADD2_Msk                         (0x7FUL<<I2C_OAR2_ADD2_Pos)                       /*!< 0x000000FE */
#define I2C_OAR2_ADD2                             I2C_OAR2_ADD2_Msk                                 /*!< Interface address */
#define I2C_OAR2_OA2MSK_Pos                       (8U)
#define I2C_OAR2_OA2MSK_Msk                       (0x7UL<<I2C_OAR2_OA2MSK_Pos)                      /*!< 0x00000700 */
#define I2C_OAR2_OA2MSK                           I2C_OAR2_OA2MSK_Msk                               /*!< Own Address 2 masks */
#define I2C_OAR2_OA2MSK_0                         (0x1UL<<I2C_OAR2_OA2MSK_Pos)                      /*!< 0x00000100 */
#define I2C_OAR2_OA2MSK_1                         (0x2UL<<I2C_OAR2_OA2MSK_Pos)                      /*!< 0x00000200 */
#define I2C_OAR2_OA2MSK_2                         (0x4UL<<I2C_OAR2_OA2MSK_Pos)                      /*!< 0x00000400 */

/********************************* Bit definition for I2C_DR register ***********************************************/
#define I2C_DR_DR_Pos                             (0U)
#define I2C_DR_DR_Msk                             (0xFFUL<<I2C_DR_DR_Pos)                           /*!< 0x000000FF */
#define I2C_DR_DR                                 I2C_DR_DR_Msk                                     /*!< 8-bit data register */

/********************************* Bit definition for I2C_SR1 register **********************************************/
#define I2C_SR1_SB_Pos                            (0U)
#define I2C_SR1_SB_Msk                            (0x1UL<<I2C_SR1_SB_Pos)                           /*!< 0x00000001 */
#define I2C_SR1_SB                                I2C_SR1_SB_Msk                                    /*!< Start bit (Master mode) */
#define I2C_SR1_ADDR_Pos                          (1U)
#define I2C_SR1_ADDR_Msk                          (0x1UL<<I2C_SR1_ADDR_Pos)                         /*!< 0x00000002 */
#define I2C_SR1_ADDR                              I2C_SR1_ADDR_Msk                                  /*!< Address sent (master mode)/matched (slave mode) */
#define I2C_SR1_BTF_Pos                           (2U)
#define I2C_SR1_BTF_Msk                           (0x1UL<<I2C_SR1_BTF_Pos)                          /*!< 0x00000004 */
#define I2C_SR1_BTF                               I2C_SR1_BTF_Msk                                   /*!< Byte transfer finished */
#define I2C_SR1_ADD10_Pos                         (3U)
#define I2C_SR1_ADD10_Msk                         (0x1UL<<I2C_SR1_ADD10_Pos)                        /*!< 0x00000008 */
#define I2C_SR1_ADD10                             I2C_SR1_ADD10_Msk                                 /*!< 10-bit header sent (Master mode) */
#define I2C_SR1_STOPF_Pos                         (4U)
#define I2C_SR1_STOPF_Msk                         (0x1UL<<I2C_SR1_STOPF_Pos)                        /*!< 0x00000010 */
#define I2C_SR1_STOPF                             I2C_SR1_STOPF_Msk                                 /*!< Stop detection (slave mode) */
#define I2C_SR1_RXNE_Pos                          (6U)
#define I2C_SR1_RXNE_Msk                          (0x1UL<<I2C_SR1_RXNE_Pos)                         /*!< 0x00000040 */
#define I2C_SR1_RXNE                              I2C_SR1_RXNE_Msk                                  /*!< Data register not empty (receivers) */
#define I2C_SR1_TXE_Pos                           (7U)
#define I2C_SR1_TXE_Msk                           (0x1UL<<I2C_SR1_TXE_Pos)                          /*!< 0x00000080 */
#define I2C_SR1_TXE                               I2C_SR1_TXE_Msk                                   /*!< Data register empty (transmitters) */
#define I2C_SR1_BERR_Pos                          (8U)
#define I2C_SR1_BERR_Msk                          (0x1UL<<I2C_SR1_BERR_Pos)                         /*!< 0x00000100 */
#define I2C_SR1_BERR                              I2C_SR1_BERR_Msk                                  /*!< Bus error */
#define I2C_SR1_ARLO_Pos                          (9U)
#define I2C_SR1_ARLO_Msk                          (0x1UL<<I2C_SR1_ARLO_Pos)                         /*!< 0x00000200 */
#define I2C_SR1_ARLO                              I2C_SR1_ARLO_Msk                                  /*!< Arbitration lost (master mode) */
#define I2C_SR1_AF_Pos                            (10U)
#define I2C_SR1_AF_Msk                            (0x1UL<<I2C_SR1_AF_Pos)                           /*!< 0x00000400 */
#define I2C_SR1_AF                                I2C_SR1_AF_Msk                                    /*!< Acknowledge failure */
#define I2C_SR1_OVR_Pos                           (11U)
#define I2C_SR1_OVR_Msk                           (0x1UL<<I2C_SR1_OVR_Pos)                          /*!< 0x00000800 */
#define I2C_SR1_OVR                               I2C_SR1_OVR_Msk                                   /*!< Overrun/Underrun */
#define I2C_SR1_PECERR_Pos                        (12U)
#define I2C_SR1_PECERR_Msk                        (0x1UL<<I2C_SR1_PECERR_Pos)                       /*!< 0x00001000 */
#define I2C_SR1_PECERR                            I2C_SR1_PECERR_Msk                                /*!< PEC Error in reception */
#define I2C_SR1_TIMEOUT_Pos                       (14U)
#define I2C_SR1_TIMEOUT_Msk                       (0x1UL<<I2C_SR1_TIMEOUT_Pos)                      /*!< 0x00004000 */
#define I2C_SR1_TIMEOUT                           I2C_SR1_TIMEOUT_Msk                               /*!< Timeout or Tlow error */
#define I2C_SR1_SMBALERT_Pos                      (15U)
#define I2C_SR1_SMBALERT_Msk                      (0x1UL<<I2C_SR1_SMBALERT_Pos)                     /*!< 0x00008000 */
#define I2C_SR1_SMBALERT                          I2C_SR1_SMBALERT_Msk                              /*!< SMBus alert */

/********************************* Bit definition for I2C_SR2 register **********************************************/
#define I2C_SR2_MSL_Pos                           (0U)
#define I2C_SR2_MSL_Msk                           (0x1UL<<I2C_SR2_MSL_Pos)                          /*!< 0x00000001 */
#define I2C_SR2_MSL                               I2C_SR2_MSL_Msk                                   /*!< Master/slave */
#define I2C_SR2_BUSY_Pos                          (1U)
#define I2C_SR2_BUSY_Msk                          (0x1UL<<I2C_SR2_BUSY_Pos)                         /*!< 0x00000002 */
#define I2C_SR2_BUSY                              I2C_SR2_BUSY_Msk                                  /*!< Bus busy */
#define I2C_SR2_TRA_Pos                           (2U)
#define I2C_SR2_TRA_Msk                           (0x1UL<<I2C_SR2_TRA_Pos)                          /*!< 0x00000004 */
#define I2C_SR2_TRA                               I2C_SR2_TRA_Msk                                   /*!< Transmitter/receiver */
#define I2C_SR2_GENCALL_Pos                       (4U)
#define I2C_SR2_GENCALL_Msk                       (0x1UL<<I2C_SR2_GENCALL_Pos)                      /*!< 0x00000010 */
#define I2C_SR2_GENCALL                           I2C_SR2_GENCALL_Msk                               /*!< General call address (Slave mode) */
#define I2C_SR2_SMBDEFAULT_Pos                    (5U)
#define I2C_SR2_SMBDEFAULT_Msk                    (0x1UL<<I2C_SR2_SMBDEFAULT_Pos)                   /*!< 0x00000020 */
#define I2C_SR2_SMBDEFAULT                        I2C_SR2_SMBDEFAULT_Msk                            /*!< SMBus device default address (Slave mode) */
#define I2C_SR2_SMBHOST_Pos                       (6U)
#define I2C_SR2_SMBHOST_Msk                       (0x1UL<<I2C_SR2_SMBHOST_Pos)                      /*!< 0x00000040 */
#define I2C_SR2_SMBHOST                           I2C_SR2_SMBHOST_Msk                               /*!< SMBus host header (Slave mode) */
#define I2C_SR2_DUALF_Pos                         (7U)
#define I2C_SR2_DUALF_Msk                         (0x1UL<<I2C_SR2_DUALF_Pos)                        /*!< 0x00000080 */
#define I2C_SR2_DUALF                             I2C_SR2_DUALF_Msk                                 /*!< Dual flag (Slave mode) */
#define I2C_SR2_PEC_Pos                           (8U)
#define I2C_SR2_PEC_Msk                           (0xFFUL<<I2C_SR2_PEC_Pos)                         /*!< 0x0000FF00 */
#define I2C_SR2_PEC                               I2C_SR2_PEC_Msk                                   /*!< Packet error checking register */
#define I2C_SR2_SBUSY_Pos                         (16U)
#define I2C_SR2_SBUSY_Msk                         (0x1UL<<I2C_SR2_SBUSY_Pos)                        /*!< 0x00010000 */
#define I2C_SR2_SBUSY                             I2C_SR2_SBUSY_Msk                                 /*!< Slave busy */

/********************************* Bit definition for I2C_CCR register **********************************************/
#define I2C_CCR_CCR_Pos                           (0U)
#define I2C_CCR_CCR_Msk                           (0xFFFUL<<I2C_CCR_CCR_Pos)                        /*!< 0x00000FFF */
#define I2C_CCR_CCR                               I2C_CCR_CCR_Msk                                   /*!< Clock control register in Fm/Sm mode (Master mode) */
#define I2C_CCR_FP_Pos                            (13U)
#define I2C_CCR_FP_Msk                            (0x1UL<<I2C_CCR_FP_Pos)                           /*!< 0x00002000 */
#define I2C_CCR_FP                                I2C_CCR_FP_Msk                                    /*!< I2C master mode selection */
#define I2C_CCR_DUTY_Pos                          (14U)
#define I2C_CCR_DUTY_Msk                          (0x1UL<<I2C_CCR_DUTY_Pos)                         /*!< 0x00004000 */
#define I2C_CCR_DUTY                              I2C_CCR_DUTY_Msk                                  /*!< Fm mode duty cycle */
#define I2C_CCR_FS_Pos                            (15U)
#define I2C_CCR_FS_Msk                            (0x1UL<<I2C_CCR_FS_Pos)                           /*!< 0x00008000 */
#define I2C_CCR_FS                                I2C_CCR_FS_Msk                                    /*!< I2C master mode selection */

/********************************* Bit definition for I2C_TRISE register ********************************************/
#define I2C_TRISE_TRISE_Pos                       (0U)
#define I2C_TRISE_TRISE_Msk                       (0xFFUL<<I2C_TRISE_TRISE_Pos)                     /*!< 0x000000FF */
#define I2C_TRISE_TRISE                           I2C_TRISE_TRISE_Msk                               /*!< Maximum rise time in Fm+/Fm/Sm mode (Master mode) */
#define I2C_TRISE_THOLDDATA_Pos                   (8U)
#define I2C_TRISE_THOLDDATA_Msk                   (0x3FUL<<I2C_TRISE_THOLDDATA_Pos)                 /*!< 0x00003F00 */
#define I2C_TRISE_THOLDDATA                       I2C_TRISE_THOLDDATA_Msk                           /*!< Data hold time */
#define I2C_TRISE_THOLDDATA_0                     (0x1UL<<I2C_TRISE_THOLDDATA_Pos)                  /*!< 0x00000100 */
#define I2C_TRISE_THOLDDATA_1                     (0x2UL<<I2C_TRISE_THOLDDATA_Pos)                  /*!< 0x00000200 */
#define I2C_TRISE_THOLDDATA_2                     (0x4UL<<I2C_TRISE_THOLDDATA_Pos)                  /*!< 0x00000400 */
#define I2C_TRISE_THOLDDATA_3                     (0x8UL<<I2C_TRISE_THOLDDATA_Pos)                  /*!< 0x00000800 */
#define I2C_TRISE_THOLDDATA_4                     (0x10UL<<I2C_TRISE_THOLDDATA_Pos)                 /*!< 0x00001000 */
#define I2C_TRISE_THOLDDATA_5                     (0x20UL<<I2C_TRISE_THOLDDATA_Pos)                 /*!< 0x00002000 */
#define I2C_TRISE_THOLDDATA_SEL_Pos               (14U)
#define I2C_TRISE_THOLDDATA_SEL_Msk               (0x1UL<<I2C_TRISE_THOLDDATA_SEL_Pos)              /*!< 0x00004000 */
#define I2C_TRISE_THOLDDATA_SEL                   I2C_TRISE_THOLDDATA_SEL_Msk                       /*!< Data hold time select */

/********************************* Bit definition for I2C_TIMEOUTR register *****************************************/
#define I2C_TIMEOUTR_TIMEOUTA_Pos                 (0U)
#define I2C_TIMEOUTR_TIMEOUTA_Msk                 (0xFFFUL<<I2C_TIMEOUTR_TIMEOUTA_Pos)              /*!< 0x00000FFF */
#define I2C_TIMEOUTR_TIMEOUTA                     I2C_TIMEOUTR_TIMEOUTA_Msk                         /*!< Bus Timeout A */
#define I2C_TIMEOUTR_TIDLE_Pos                    (12U)
#define I2C_TIMEOUTR_TIDLE_Msk                    (0x1UL<<I2C_TIMEOUTR_TIDLE_Pos)                   /*!< 0x00001000 */
#define I2C_TIMEOUTR_TIDLE                        I2C_TIMEOUTR_TIDLE_Msk                            /*!< Idle clock timeout detection */
#define I2C_TIMEOUTR_TIMEOUTEN_Pos                (15U)
#define I2C_TIMEOUTR_TIMEOUTEN_Msk                (0x1UL<<I2C_TIMEOUTR_TIMEOUTEN_Pos)               /*!< 0x00008000 */
#define I2C_TIMEOUTR_TIMEOUTEN                    I2C_TIMEOUTR_TIMEOUTEN_Msk                        /*!< Clock timeout enable */
#define I2C_TIMEOUTR_TIMEOUTB_Pos                 (16U)
#define I2C_TIMEOUTR_TIMEOUTB_Msk                 (0xFFFUL<<I2C_TIMEOUTR_TIMEOUTB_Pos)              /*!< 0x0FFF0000 */
#define I2C_TIMEOUTR_TIMEOUTB                     I2C_TIMEOUTR_TIMEOUTB_Msk                         /*!< Bus timeout B */
#define I2C_TIMEOUTR_TEXTEN_Pos                   (31U)
#define I2C_TIMEOUTR_TEXTEN_Msk                   (0x1UL<<I2C_TIMEOUTR_TEXTEN_Pos)                  /*!< 0x80000000 */
#define I2C_TIMEOUTR_TEXTEN                       I2C_TIMEOUTR_TEXTEN_Msk                           /*!< Extended clock timeout enable */

/********************************* Bit definition for I2C_OAR3 register *********************************************/
#define I2C_OAR3_ENTRIPLE_Pos                     (0U)
#define I2C_OAR3_ENTRIPLE_Msk                     (0x1UL<<I2C_OAR3_ENTRIPLE_Pos)                    /*!< 0x00000001 */
#define I2C_OAR3_ENTRIPLE                         I2C_OAR3_ENTRIPLE_Msk                             /*!< Triple addressing mode enable */
#define I2C_OAR3_ADD3_Pos                         (1U)
#define I2C_OAR3_ADD3_Msk                         (0x7FUL<<I2C_OAR3_ADD3_Pos)                       /*!< 0x000000FE */
#define I2C_OAR3_ADD3                             I2C_OAR3_ADD3_Msk                                 /*!< Interface address */

/********************************************************************************************************************/
/********************************* USART ****************************************************************************/
/********************************************************************************************************************/

/********************************* Bit definition for USART_SR register *********************************************/
#define USART_SR_PE_Pos                           (0U)
#define USART_SR_PE_Msk                           (0x1UL<<USART_SR_PE_Pos)                          /*!< 0x00000001 */
#define USART_SR_PE                               USART_SR_PE_Msk                                   
#define USART_SR_FE_Pos                           (1U)
#define USART_SR_FE_Msk                           (0x1UL<<USART_SR_FE_Pos)                          /*!< 0x00000002 */
#define USART_SR_FE                               USART_SR_FE_Msk                                   
#define USART_SR_NE_Pos                           (2U)
#define USART_SR_NE_Msk                           (0x1UL<<USART_SR_NE_Pos)                          /*!< 0x00000004 */
#define USART_SR_NE                               USART_SR_NE_Msk                                   
#define USART_SR_ORE_Pos                          (3U)
#define USART_SR_ORE_Msk                          (0x1UL<<USART_SR_ORE_Pos)                         /*!< 0x00000008 */
#define USART_SR_ORE                              USART_SR_ORE_Msk                                  
#define USART_SR_IDLE_Pos                         (4U)
#define USART_SR_IDLE_Msk                         (0x1UL<<USART_SR_IDLE_Pos)                        /*!< 0x00000010 */
#define USART_SR_IDLE                             USART_SR_IDLE_Msk                                 
#define USART_SR_RXNE_Pos                         (5U)
#define USART_SR_RXNE_Msk                         (0x1UL<<USART_SR_RXNE_Pos)                        /*!< 0x00000020 */
#define USART_SR_RXNE                             USART_SR_RXNE_Msk                                 
#define USART_SR_TC_Pos                           (6U)
#define USART_SR_TC_Msk                           (0x1UL<<USART_SR_TC_Pos)                          /*!< 0x00000040 */
#define USART_SR_TC                               USART_SR_TC_Msk                                   
#define USART_SR_TXE_Pos                          (7U)
#define USART_SR_TXE_Msk                          (0x1UL<<USART_SR_TXE_Pos)                         /*!< 0x00000080 */
#define USART_SR_TXE                              USART_SR_TXE_Msk                                  
#define USART_SR_LBD_Pos                          (8U)
#define USART_SR_LBD_Msk                          (0x1UL<<USART_SR_LBD_Pos)                         /*!< 0x00000100 */
#define USART_SR_LBD                              USART_SR_LBD_Msk                                  
#define USART_SR_CTS_Pos                          (9U)
#define USART_SR_CTS_Msk                          (0x1UL<<USART_SR_CTS_Pos)                         /*!< 0x00000200 */
#define USART_SR_CTS                              USART_SR_CTS_Msk                                  
#define USART_SR_ABRF_Pos                         (10U)
#define USART_SR_ABRF_Msk                         (0x1UL<<USART_SR_ABRF_Pos)                        /*!< 0x00000400 */
#define USART_SR_ABRF                             USART_SR_ABRF_Msk                                 
#define USART_SR_ABRE_Pos                         (11U)
#define USART_SR_ABRE_Msk                         (0x1UL<<USART_SR_ABRE_Pos)                        /*!< 0x00000800 */
#define USART_SR_ABRE                             USART_SR_ABRE_Msk                                 
#define USART_SR_ABRRQ_Pos                        (12U)
#define USART_SR_ABRRQ_Msk                        (0x1UL<<USART_SR_ABRRQ_Pos)                       /*!< 0x00001000 */
#define USART_SR_ABRRQ                            USART_SR_ABRRQ_Msk                                
#define USART_SR_TXFT_Pos                         (13U)
#define USART_SR_TXFT_Msk                         (0x1UL<<USART_SR_TXFT_Pos)                        /*!< 0x00002000 */
#define USART_SR_TXFT                             USART_SR_TXFT_Msk                                 
#define USART_SR_RXFT_Pos                         (14U)
#define USART_SR_RXFT_Msk                         (0x1UL<<USART_SR_RXFT_Pos)                        /*!< 0x00004000 */
#define USART_SR_RXFT                             USART_SR_RXFT_Msk                                 
#define USART_SR_RXFF_Pos                         (15U)
#define USART_SR_RXFF_Msk                         (0x1UL<<USART_SR_RXFF_Pos)                        /*!< 0x00008000 */
#define USART_SR_RXFF                             USART_SR_RXFF_Msk                                 
#define USART_SR_TXFE_Pos                         (16U)
#define USART_SR_TXFE_Msk                         (0x1UL<<USART_SR_TXFE_Pos)                        /*!< 0x00010000 */
#define USART_SR_TXFE                             USART_SR_TXFE_Msk                                 
#define USART_SR_EOBF_Pos                         (18U)
#define USART_SR_EOBF_Msk                         (0x1UL<<USART_SR_EOBF_Pos)                        /*!< 0x00040000 */
#define USART_SR_EOBF                             USART_SR_EOBF_Msk                                 
#define USART_SR_RTOF_Pos                         (19U)
#define USART_SR_RTOF_Msk                         (0x1UL<<USART_SR_RTOF_Pos)                        /*!< 0x00080000 */
#define USART_SR_RTOF                             USART_SR_RTOF_Msk                                 
#define USART_SR_TXPE_Pos                         (20U)
#define USART_SR_TXPE_Msk                         (0x1UL<<USART_SR_TXPE_Pos)                        /*!< 0x00100000 */
#define USART_SR_TXPE                             USART_SR_TXPE_Msk                                 
#define USART_SR_RXBUSY_Pos                       (21U)
#define USART_SR_RXBUSY_Msk                       (0x1UL<<USART_SR_RXBUSY_Pos)                      /*!< 0x00200000 */
#define USART_SR_RXBUSY                           USART_SR_RXBUSY_Msk                               
#define USART_SR_TXBUSY_Pos                       (22U)
#define USART_SR_TXBUSY_Msk                       (0x1UL<<USART_SR_TXBUSY_Pos)                      /*!< 0x00400000 */
#define USART_SR_TXBUSY                           USART_SR_TXBUSY_Msk                               
#define USART_SR_WAIT_RPT_Pos                     (23U)
#define USART_SR_WAIT_RPT_Msk                     (0x1UL<<USART_SR_WAIT_RPT_Pos)                    /*!< 0x00800000 */
#define USART_SR_WAIT_RPT                         USART_SR_WAIT_RPT_Msk                             

/********************************* Bit definition for USART_DR register *********************************************/
#define USART_DR_DR_Pos                           (0U)
#define USART_DR_DR_Msk                           (0x1FFUL<<USART_DR_DR_Pos)                        /*!< 0x000001FF */
#define USART_DR_DR                               USART_DR_DR_Msk

/********************************* Bit definition for USART_BRR register ********************************************/
#define USART_BRR_DIV_FRA_Pos                     (0U)
#define USART_BRR_DIV_FRA_Msk                     (0xFUL<<USART_BRR_DIV_FRA_Pos)                    /*!< 0x0000000F */
#define USART_BRR_DIV_FRA                         USART_BRR_DIV_FRA_Msk
#define USART_BRR_DIV_FRA_0                       (0x1UL<<USART_BRR_DIV_FRA_Pos)                    /*!< 0x00000001 */
#define USART_BRR_DIV_FRA_1                       (0x2UL<<USART_BRR_DIV_FRA_Pos)                    /*!< 0x00000002 */
#define USART_BRR_DIV_FRA_2                       (0x4UL<<USART_BRR_DIV_FRA_Pos)                    /*!< 0x00000004 */
#define USART_BRR_DIV_FRA_3                       (0x8UL<<USART_BRR_DIV_FRA_Pos)                    /*!< 0x00000008 */
#define USART_BRR_DIV_MAN_Pos                     (4U)
#define USART_BRR_DIV_MAN_Msk                     (0xFFFUL<<USART_BRR_DIV_MAN_Pos)                  /*!< 0x0000FFF0 */
#define USART_BRR_DIV_MAN                         USART_BRR_DIV_MAN_Msk

/********************************* Bit definition for USART_CR1 register ********************************************/
#define USART_CR1_SBK_Pos                         (0U)
#define USART_CR1_SBK_Msk                         (0x1UL<<USART_CR1_SBK_Pos)                        /*!< 0x00000001 */
#define USART_CR1_SBK                             USART_CR1_SBK_Msk                                 
#define USART_CR1_RWU_Pos                         (1U)
#define USART_CR1_RWU_Msk                         (0x1UL<<USART_CR1_RWU_Pos)                        /*!< 0x00000002 */
#define USART_CR1_RWU                             USART_CR1_RWU_Msk                                 
#define USART_CR1_RE_Pos                          (2U)
#define USART_CR1_RE_Msk                          (0x1UL<<USART_CR1_RE_Pos)                         /*!< 0x00000004 */
#define USART_CR1_RE                              USART_CR1_RE_Msk                                  
#define USART_CR1_TE_Pos                          (3U)
#define USART_CR1_TE_Msk                          (0x1UL<<USART_CR1_TE_Pos)                         /*!< 0x00000008 */
#define USART_CR1_TE                              USART_CR1_TE_Msk                                  
#define USART_CR1_IDLEIE_Pos                      (4U)
#define USART_CR1_IDLEIE_Msk                      (0x1UL<<USART_CR1_IDLEIE_Pos)                     /*!< 0x00000010 */
#define USART_CR1_IDLEIE                          USART_CR1_IDLEIE_Msk                              
#define USART_CR1_RXNEIE_Pos                      (5U)
#define USART_CR1_RXNEIE_Msk                      (0x1UL<<USART_CR1_RXNEIE_Pos)                     /*!< 0x00000020 */
#define USART_CR1_RXNEIE                          USART_CR1_RXNEIE_Msk                              
#define USART_CR1_TCIE_Pos                        (6U)
#define USART_CR1_TCIE_Msk                        (0x1UL<<USART_CR1_TCIE_Pos)                       /*!< 0x00000040 */
#define USART_CR1_TCIE                            USART_CR1_TCIE_Msk                                
#define USART_CR1_TXEIE_Pos                       (7U)
#define USART_CR1_TXEIE_Msk                       (0x1UL<<USART_CR1_TXEIE_Pos)                      /*!< 0x00000080 */
#define USART_CR1_TXEIE                           USART_CR1_TXEIE_Msk                               
#define USART_CR1_PEIE_Pos                        (8U)
#define USART_CR1_PEIE_Msk                        (0x1UL<<USART_CR1_PEIE_Pos)                       /*!< 0x00000100 */
#define USART_CR1_PEIE                            USART_CR1_PEIE_Msk                                
#define USART_CR1_PS_Pos                          (9U)
#define USART_CR1_PS_Msk                          (0x1UL<<USART_CR1_PS_Pos)                         /*!< 0x00000200 */
#define USART_CR1_PS                              USART_CR1_PS_Msk                                  
#define USART_CR1_PCE_Pos                         (10U)
#define USART_CR1_PCE_Msk                         (0x1UL<<USART_CR1_PCE_Pos)                        /*!< 0x00000400 */
#define USART_CR1_PCE                             USART_CR1_PCE_Msk                                 
#define USART_CR1_WAKE_Pos                        (11U)
#define USART_CR1_WAKE_Msk                        (0x1UL<<USART_CR1_WAKE_Pos)                       /*!< 0x00000800 */
#define USART_CR1_WAKE                            USART_CR1_WAKE_Msk                                
#define USART_CR1_M0_Pos                          (12U)
#define USART_CR1_M0_Msk                          (0x1UL<<USART_CR1_M0_Pos)                         /*!< 0x00001000 */
#define USART_CR1_M0                              USART_CR1_M0_Msk                                  
#define USART_CR1_UE_Pos                          (13U)
#define USART_CR1_UE_Msk                          (0x1UL<<USART_CR1_UE_Pos)                         /*!< 0x00002000 */
#define USART_CR1_UE                              USART_CR1_UE_Msk                                  
#define USART_CR1_M1_Pos                          (14U)
#define USART_CR1_M1_Msk                          (0x1UL<<USART_CR1_M1_Pos)                         /*!< 0x00004000 */
#define USART_CR1_M1                              USART_CR1_M1_Msk                                  
#define USART_CR1_MSB_Pos                         (15U)
#define USART_CR1_MSB_Msk                         (0x1UL<<USART_CR1_MSB_Pos)                        /*!< 0x00008000 */
#define USART_CR1_MSB                             USART_CR1_MSB_Msk                                 
#define USART_CR1_ADDM7_Pos                       (17U)
#define USART_CR1_ADDM7_Msk                       (0x1UL<<USART_CR1_ADDM7_Pos)                      /*!< 0x00020000 */
#define USART_CR1_ADDM7                           USART_CR1_ADDM7_Msk                               
#define USART_CR1_SWAP_Pos                        (18U)
#define USART_CR1_SWAP_Msk                        (0x1UL<<USART_CR1_SWAP_Pos)                       /*!< 0x00040000 */
#define USART_CR1_SWAP                            USART_CR1_SWAP_Msk                                
#define USART_CR1_TXFTCFG_Pos                     (19U)
#define USART_CR1_TXFTCFG_Msk                     (0x7UL<<USART_CR1_TXFTCFG_Pos)                    /*!< 0x00380000 */
#define USART_CR1_TXFTCFG                         USART_CR1_TXFTCFG_Msk
#define USART_CR1_TXFTCFG_0                       (0x1UL<<USART_CR1_TXFTCFG_Pos)                    /*!< 0x00080000 */
#define USART_CR1_TXFTCFG_1                       (0x2UL<<USART_CR1_TXFTCFG_Pos)                    /*!< 0x00100000 */
#define USART_CR1_TXFTCFG_2                       (0x4UL<<USART_CR1_TXFTCFG_Pos)                    /*!< 0x00200000 */
#define USART_CR1_RXFTCFG_Pos                     (22U)
#define USART_CR1_RXFTCFG_Msk                     (0x7UL<<USART_CR1_RXFTCFG_Pos)                    /*!< 0x01C00000 */
#define USART_CR1_RXFTCFG                         USART_CR1_RXFTCFG_Msk
#define USART_CR1_RXFTCFG_0                       (0x1UL<<USART_CR1_RXFTCFG_Pos)                    /*!< 0x00400000 */
#define USART_CR1_RXFTCFG_1                       (0x2UL<<USART_CR1_RXFTCFG_Pos)                    /*!< 0x00800000 */
#define USART_CR1_RXFTCFG_2                       (0x4UL<<USART_CR1_RXFTCFG_Pos)                    /*!< 0x01000000 */
#define USART_CR1_RX_INV_Pos                      (25U)
#define USART_CR1_RX_INV_Msk                      (0x1UL<<USART_CR1_RX_INV_Pos)                     /*!< 0x02000000 */
#define USART_CR1_RX_INV                          USART_CR1_RX_INV_Msk                              
#define USART_CR1_TX_INV_Pos                      (26U)
#define USART_CR1_TX_INV_Msk                      (0x1UL<<USART_CR1_TX_INV_Pos)                     /*!< 0x04000000 */
#define USART_CR1_TX_INV                          USART_CR1_TX_INV_Msk                              
#define USART_CR1_DATAINV_Pos                     (27U)
#define USART_CR1_DATAINV_Msk                     (0x1UL<<USART_CR1_DATAINV_Pos)                   /*!< 0x08000000 */
#define USART_CR1_DATAINV                         USART_CR1_DATAINV_Msk                            
#define USART_CR1_ONEBIT_Pos                      (28U)
#define USART_CR1_ONEBIT_Msk                      (0x1UL<<USART_CR1_ONEBIT_Pos)                     /*!< 0x10000000 */
#define USART_CR1_ONEBIT                          USART_CR1_ONEBIT_Msk                              
#define USART_CR1_RXFRQ_Pos                       (29U)
#define USART_CR1_RXFRQ_Msk                       (0x1UL<<USART_CR1_RXFRQ_Pos)                      /*!< 0x20000000 */
#define USART_CR1_RXFRQ                           USART_CR1_RXFRQ_Msk                               
#define USART_CR1_TXFRQ_Pos                       (30U)
#define USART_CR1_TXFRQ_Msk                       (0x1UL<<USART_CR1_TXFRQ_Pos)                      /*!< 0x40000000 */
#define USART_CR1_TXFRQ                           USART_CR1_TXFRQ_Msk                               
#define USART_CR1_FIFOEN_Pos                      (31U)
#define USART_CR1_FIFOEN_Msk                      (0x1UL<<USART_CR1_FIFOEN_Pos)                     /*!< 0x80000000 */
#define USART_CR1_FIFOEN                          USART_CR1_FIFOEN_Msk                              

/********************************* Bit definition for USART_CR2 register ********************************************/
#define USART_CR2_LBDL_Pos                        (5U)
#define USART_CR2_LBDL_Msk                        (0x1UL<<USART_CR2_LBDL_Pos)                       /*!< 0x00000020 */
#define USART_CR2_LBDL                            USART_CR2_LBDL_Msk                                
#define USART_CR2_LBDIE_Pos                       (6U)
#define USART_CR2_LBDIE_Msk                       (0x1UL<<USART_CR2_LBDIE_Pos)                      /*!< 0x00000040 */
#define USART_CR2_LBDIE                           USART_CR2_LBDIE_Msk                               
#define USART_CR2_LBCL_Pos                        (8U)
#define USART_CR2_LBCL_Msk                        (0x1UL<<USART_CR2_LBCL_Pos)                       /*!< 0x00000100 */
#define USART_CR2_LBCL                            USART_CR2_LBCL_Msk                                
#define USART_CR2_CPHA_Pos                        (9U)
#define USART_CR2_CPHA_Msk                        (0x1UL<<USART_CR2_CPHA_Pos)                       /*!< 0x00000200 */
#define USART_CR2_CPHA                            USART_CR2_CPHA_Msk                                
#define USART_CR2_CPOL_Pos                        (10U)
#define USART_CR2_CPOL_Msk                        (0x1UL<<USART_CR2_CPOL_Pos)                       /*!< 0x00000400 */
#define USART_CR2_CPOL                            USART_CR2_CPOL_Msk                                
#define USART_CR2_CLKEN_Pos                       (11U)
#define USART_CR2_CLKEN_Msk                       (0x1UL<<USART_CR2_CLKEN_Pos)                      /*!< 0x00000800 */
#define USART_CR2_CLKEN                           USART_CR2_CLKEN_Msk                               
#define USART_CR2_STOP_Pos                        (12U)
#define USART_CR2_STOP_Msk                        (0x3UL<<USART_CR2_STOP_Pos)                       /*!< 0x00003000 */
#define USART_CR2_STOP                            USART_CR2_STOP_Msk
#define USART_CR2_STOP_0                          (0x1UL<<USART_CR2_STOP_Pos)                       /*!< 0x00001000 */
#define USART_CR2_STOP_1                          (0x2UL<<USART_CR2_STOP_Pos)                       /*!< 0x00002000 */
#define USART_CR2_LINEN_Pos                       (14U)
#define USART_CR2_LINEN_Msk                       (0x1UL<<USART_CR2_LINEN_Pos)                      /*!< 0x00004000 */
#define USART_CR2_LINEN                           USART_CR2_LINEN_Msk                               
#define USART_CR2_ADD_Pos                         (15U)
#define USART_CR2_ADD_Msk                         (0xFFUL<<USART_CR2_ADD_Pos)                       /*!< 0x007F8000 */
#define USART_CR2_ADD                             USART_CR2_ADD_Msk
#define USART_CR2_DEM_Pos                         (23U)
#define USART_CR2_DEM_Msk                         (0x1UL<<USART_CR2_DEM_Pos)                        /*!< 0x00800000 */
#define USART_CR2_DEM                             USART_CR2_DEM_Msk                                 
#define USART_CR2_DEP_Pos                         (24U)
#define USART_CR2_DEP_Msk                         (0x1UL<<USART_CR2_DEP_Pos)                        /*!< 0x01000000 */
#define USART_CR2_DEP                             USART_CR2_DEP_Msk                                 
#define USART_CR2_RTOEN_Pos                       (25U)
#define USART_CR2_RTOEN_Msk                       (0x1UL<<USART_CR2_RTOEN_Pos)                      /*!< 0x02000000 */
#define USART_CR2_RTOEN                           USART_CR2_RTOEN_Msk                               
#define USART_CR2_ERSW_Pos                        (26U)
#define USART_CR2_ERSW_Msk                        (0x3UL<<USART_CR2_ERSW_Pos)                       /*!< 0x0C000000 */
#define USART_CR2_ERSW                            USART_CR2_ERSW_Msk
#define USART_CR2_ERSW_0                          (0x1UL<<USART_CR2_ERSW_Pos)                       /*!< 0x04000000 */
#define USART_CR2_ERSW_1                          (0x2UL<<USART_CR2_ERSW_Pos)                       /*!< 0x08000000 */
#define USART_CR2_REP_T_Pos                       (28U)
#define USART_CR2_REP_T_Msk                       (0x1UL<<USART_CR2_REP_T_Pos)                      /*!< 0x10000000 */
#define USART_CR2_REP_T                           USART_CR2_REP_T_Msk                               
#define USART_CR2_TREPEN_Pos                      (29U)
#define USART_CR2_TREPEN_Msk                      (0x1UL<<USART_CR2_TREPEN_Pos)                     /*!< 0x20000000 */
#define USART_CR2_TREPEN                          USART_CR2_TREPEN_Msk                              
#define USART_CR2_RREPEN_Pos                      (30U)
#define USART_CR2_RREPEN_Msk                      (0x1UL<<USART_CR2_RREPEN_Pos)                     /*!< 0x40000000 */
#define USART_CR2_RREPEN                          USART_CR2_RREPEN_Msk                              

/********************************* Bit definition for USART_CR3 register ********************************************/
#define USART_CR3_EIE_Pos                         (0U)
#define USART_CR3_EIE_Msk                         (0x1UL<<USART_CR3_EIE_Pos)                        /*!< 0x00000001 */
#define USART_CR3_EIE                             USART_CR3_EIE_Msk                                 
#define USART_CR3_IREN_Pos                        (1U)
#define USART_CR3_IREN_Msk                        (0x1UL<<USART_CR3_IREN_Pos)                       /*!< 0x00000002 */
#define USART_CR3_IREN                            USART_CR3_IREN_Msk                                
#define USART_CR3_IRLP_Pos                        (2U)
#define USART_CR3_IRLP_Msk                        (0x1UL<<USART_CR3_IRLP_Pos)                       /*!< 0x00000004 */
#define USART_CR3_IRLP                            USART_CR3_IRLP_Msk                                
#define USART_CR3_HDSEL_Pos                       (3U)
#define USART_CR3_HDSEL_Msk                       (0x1UL<<USART_CR3_HDSEL_Pos)                      /*!< 0x00000008 */
#define USART_CR3_HDSEL                           USART_CR3_HDSEL_Msk                               
#define USART_CR3_NACK_Pos                        (4U)
#define USART_CR3_NACK_Msk                        (0x1UL<<USART_CR3_NACK_Pos)                       /*!< 0x00000010 */
#define USART_CR3_NACK                            USART_CR3_NACK_Msk                                
#define USART_CR3_SCEN_Pos                        (5U)
#define USART_CR3_SCEN_Msk                        (0x1UL<<USART_CR3_SCEN_Pos)                       /*!< 0x00000020 */
#define USART_CR3_SCEN                            USART_CR3_SCEN_Msk                                
#define USART_CR3_DMAR_Pos                        (6U)
#define USART_CR3_DMAR_Msk                        (0x1UL<<USART_CR3_DMAR_Pos)                       /*!< 0x00000040 */
#define USART_CR3_DMAR                            USART_CR3_DMAR_Msk                                
#define USART_CR3_DMAT_Pos                        (7U)
#define USART_CR3_DMAT_Msk                        (0x1UL<<USART_CR3_DMAT_Pos)                       /*!< 0x00000080 */
#define USART_CR3_DMAT                            USART_CR3_DMAT_Msk                                
#define USART_CR3_RTSE_Pos                        (8U)
#define USART_CR3_RTSE_Msk                        (0x1UL<<USART_CR3_RTSE_Pos)                       /*!< 0x00000100 */
#define USART_CR3_RTSE                            USART_CR3_RTSE_Msk                                
#define USART_CR3_CTSE_Pos                        (9U)
#define USART_CR3_CTSE_Msk                        (0x1UL<<USART_CR3_CTSE_Pos)                       /*!< 0x00000200 */
#define USART_CR3_CTSE                            USART_CR3_CTSE_Msk                                
#define USART_CR3_CTSIE_Pos                       (10U)
#define USART_CR3_CTSIE_Msk                       (0x1UL<<USART_CR3_CTSIE_Pos)                      /*!< 0x00000400 */
#define USART_CR3_CTSIE                           USART_CR3_CTSIE_Msk                               
#define USART_CR3_OVER8_Pos                       (11U)
#define USART_CR3_OVER8_Msk                       (0x1UL<<USART_CR3_OVER8_Pos)                      /*!< 0x00000800 */
#define USART_CR3_OVER8                           USART_CR3_OVER8_Msk                               
#define USART_CR3_ABREN_Pos                       (12U)
#define USART_CR3_ABREN_Msk                       (0x1UL<<USART_CR3_ABREN_Pos)                      /*!< 0x00001000 */
#define USART_CR3_ABREN                           USART_CR3_ABREN_Msk                               
#define USART_CR3_ABRMOD_Pos                      (13U)
#define USART_CR3_ABRMOD_Msk                      (0x3UL<<USART_CR3_ABRMOD_Pos)                     /*!< 0x00006000 */
#define USART_CR3_ABRMOD                          USART_CR3_ABRMOD_Msk
#define USART_CR3_ABRMOD_0                        (0x1UL<<USART_CR3_ABRMOD_Pos)                     /*!< 0x00002000 */
#define USART_CR3_ABRMOD_1                        (0x2UL<<USART_CR3_ABRMOD_Pos)                     /*!< 0x00004000 */
#define USART_CR3_RXFFIE_Pos                      (15U)
#define USART_CR3_RXFFIE_Msk                      (0x1UL<<USART_CR3_RXFFIE_Pos)                     /*!< 0x00008000 */
#define USART_CR3_RXFFIE                          USART_CR3_RXFFIE_Msk                              
#define USART_CR3_TXFEIE_Pos                      (16U)
#define USART_CR3_TXFEIE_Msk                      (0x1UL<<USART_CR3_TXFEIE_Pos)                     /*!< 0x00010000 */
#define USART_CR3_TXFEIE                          USART_CR3_TXFEIE_Msk                              
#define USART_CR3_RXFTIE_Pos                      (17U)
#define USART_CR3_RXFTIE_Msk                      (0x1UL<<USART_CR3_RXFTIE_Pos)                     /*!< 0x00020000 */
#define USART_CR3_RXFTIE                          USART_CR3_RXFTIE_Msk                              
#define USART_CR3_TXFTIE_Pos                      (18U)
#define USART_CR3_TXFTIE_Msk                      (0x1UL<<USART_CR3_TXFTIE_Pos)                     /*!< 0x00040000 */
#define USART_CR3_TXFTIE                          USART_CR3_TXFTIE_Msk                              
#define USART_CR3_DEDT_Pos                        (19U)
#define USART_CR3_DEDT_Msk                        (0x1FUL<<USART_CR3_DEDT_Pos)                      /*!< 0x00F80000 */
#define USART_CR3_DEDT                            USART_CR3_DEDT_Msk
#define USART_CR3_DEDT_0                          (0x1UL<<USART_CR3_DEDT_Pos)                       /*!< 0x00080000 */
#define USART_CR3_DEDT_1                          (0x2UL<<USART_CR3_DEDT_Pos)                       /*!< 0x00100000 */
#define USART_CR3_DEDT_2                          (0x4UL<<USART_CR3_DEDT_Pos)                       /*!< 0x00200000 */
#define USART_CR3_DEDT_3                          (0x8UL<<USART_CR3_DEDT_Pos)                       /*!< 0x00400000 */
#define USART_CR3_DEDT_4                          (0x10UL<<USART_CR3_DEDT_Pos)                      /*!< 0x00800000 */
#define USART_CR3_DEAT_Pos                        (24U)
#define USART_CR3_DEAT_Msk                        (0x1FUL<<USART_CR3_DEAT_Pos)                      /*!< 0x1F000000 */
#define USART_CR3_DEAT                            USART_CR3_DEAT_Msk
#define USART_CR3_DEAT_0                          (0x1UL<<USART_CR3_DEAT_Pos)                       /*!< 0x01000000 */
#define USART_CR3_DEAT_1                          (0x2UL<<USART_CR3_DEAT_Pos)                       /*!< 0x02000000 */
#define USART_CR3_DEAT_2                          (0x4UL<<USART_CR3_DEAT_Pos)                       /*!< 0x04000000 */
#define USART_CR3_DEAT_3                          (0x8UL<<USART_CR3_DEAT_Pos)                       /*!< 0x08000000 */
#define USART_CR3_DEAT_4                          (0x10UL<<USART_CR3_DEAT_Pos)                      /*!< 0x10000000 */
#define USART_CR3_RTOIE_Pos                       (29U)
#define USART_CR3_RTOIE_Msk                       (0x1UL<<USART_CR3_RTOIE_Pos)                      /*!< 0x20000000 */
#define USART_CR3_RTOIE                           USART_CR3_RTOIE_Msk                               
#define USART_CR3_EOBIE_Pos                       (30U)
#define USART_CR3_EOBIE_Msk                       (0x1UL<<USART_CR3_EOBIE_Pos)                      /*!< 0x40000000 */
#define USART_CR3_EOBIE                           USART_CR3_EOBIE_Msk                               

/********************************* Bit definition for USART_GTPR register *******************************************/
#define USART_GTPR_PSC_Pos                        (0U)
#define USART_GTPR_PSC_Msk                        (0xFFUL<<USART_GTPR_PSC_Pos)                      /*!< 0x000000FF */
#define USART_GTPR_PSC                            USART_GTPR_PSC_Msk
#define USART_GTPR_GT_Pos                         (8U)
#define USART_GTPR_GT_Msk                         (0xFFUL<<USART_GTPR_GT_Pos)                       /*!< 0x0000FF00 */
#define USART_GTPR_GT                             USART_GTPR_GT_Msk

/********************************* Bit definition for USART_RTOR register *******************************************/
#define USART_RTOR_RTO_Pos                        (0U)
#define USART_RTOR_RTO_Msk                        (0xFFFFFFUL<<USART_RTOR_RTO_Pos)                  /*!< 0x00FFFFFF */
#define USART_RTOR_RTO                            USART_RTOR_RTO_Msk
#define USART_RTOR_BLEN_Pos                       (24U)
#define USART_RTOR_BLEN_Msk                       (0xFFUL<<USART_RTOR_BLEN_Pos)                     /*!< 0xFF000000 */
#define USART_RTOR_BLEN                           USART_RTOR_BLEN_Msk

/********************************************************************************************************************/
/********************************* UART *****************************************************************************/
/********************************************************************************************************************/

/********************************* Bit definition for UART_DR register **********************************************/
#define UART_DR_DR_Pos                            (0U)
#define UART_DR_DR_Msk                            (0x1FFUL<<UART_DR_DR_Pos)                         /*!< 0x000001FF */
#define UART_DR_DR                                UART_DR_DR_Msk

/********************************* Bit definition for UART_BRR register *********************************************/
#define UART_BRR_BRR_Pos                          (0U)
#define UART_BRR_BRR_Msk                          (0xFFFFUL<<UART_BRR_BRR_Pos)                      /*!< 0x0000FFFF */
#define UART_BRR_BRR                              UART_BRR_BRR_Msk

/********************************* Bit definition for UART_SR register **********************************************/
#define UART_SR_RXNE_Pos                          (0U)
#define UART_SR_RXNE_Msk                          (0x1UL<<UART_SR_RXNE_Pos)                         /*!< 0x00000001 */
#define UART_SR_RXNE                              UART_SR_RXNE_Msk                                  
#define UART_SR_ORE_Pos                           (1U)
#define UART_SR_ORE_Msk                           (0x1UL<<UART_SR_ORE_Pos)                          /*!< 0x00000002 */
#define UART_SR_ORE                               UART_SR_ORE_Msk                                   
#define UART_SR_PE_Pos                            (2U)
#define UART_SR_PE_Msk                            (0x1UL<<UART_SR_PE_Pos)                           /*!< 0x00000004 */
#define UART_SR_PE                                UART_SR_PE_Msk                                    
#define UART_SR_FE_Pos                            (3U)
#define UART_SR_FE_Msk                            (0x1UL<<UART_SR_FE_Pos)                           /*!< 0x00000008 */
#define UART_SR_FE                                UART_SR_FE_Msk                                    
#define UART_SR_BRI_Pos                           (4U)
#define UART_SR_BRI_Msk                           (0x1UL<<UART_SR_BRI_Pos)                          /*!< 0x00000010 */
#define UART_SR_BRI                               UART_SR_BRI_Msk                                   
#define UART_SR_TDRE_Pos                          (5U)
#define UART_SR_TDRE_Msk                          (0x1UL<<UART_SR_TDRE_Pos)                         /*!< 0x00000020 */
#define UART_SR_TDRE                              UART_SR_TDRE_Msk                                  
#define UART_SR_TXE_Pos                           (6U)
#define UART_SR_TXE_Msk                           (0x1UL<<UART_SR_TXE_Pos)                          /*!< 0x00000040 */
#define UART_SR_TXE                               UART_SR_TXE_Msk                                   
#define UART_SR_ADDR_RCVD_Pos                     (8U)
#define UART_SR_ADDR_RCVD_Msk                     (0x1UL<<UART_SR_ADDR_RCVD_Pos)                    /*!< 0x00000100 */
#define UART_SR_ADDR_RCVD                         UART_SR_ADDR_RCVD_Msk                             
#define UART_SR_BUSY_Pos                          (9U)
#define UART_SR_BUSY_Msk                          (0x1UL<<UART_SR_BUSY_Pos)                         /*!< 0x00000200 */
#define UART_SR_BUSY                              UART_SR_BUSY_Msk                                  
#define UART_SR_BUSY_ERR_Pos                      (10U)
#define UART_SR_BUSY_ERR_Msk                      (0x1UL<<UART_SR_BUSY_ERR_Pos)                     /*!< 0x00000400 */
#define UART_SR_BUSY_ERR                          UART_SR_BUSY_ERR_Msk                              

/********************************* Bit definition for UART_CR1 register *********************************************/
#define UART_CR1_M_Pos                            (0U)
#define UART_CR1_M_Msk                            (0x3UL<<UART_CR1_M_Pos)                           /*!< 0x00000003 */
#define UART_CR1_M                                UART_CR1_M_Msk
#define UART_CR1_M_0                              (0x1UL<<UART_CR1_M_Pos)                           /*!< 0x00000001 */
#define UART_CR1_M_1                              (0x2UL<<UART_CR1_M_Pos)                           /*!< 0x00000002 */
#define UART_CR1_STOP_Pos                         (2U)
#define UART_CR1_STOP_Msk                         (0x1UL<<UART_CR1_STOP_Pos)                        /*!< 0x00000004 */
#define UART_CR1_STOP                             UART_CR1_STOP_Msk                                 
#define UART_CR1_PCE_Pos                          (3U)
#define UART_CR1_PCE_Msk                          (0x1UL<<UART_CR1_PCE_Pos)                         /*!< 0x00000008 */
#define UART_CR1_PCE                              UART_CR1_PCE_Msk                                  
#define UART_CR1_PS_Pos                           (4U)
#define UART_CR1_PS_Msk                           (0x1UL<<UART_CR1_PS_Pos)                          /*!< 0x00000010 */
#define UART_CR1_PS                               UART_CR1_PS_Msk                                   
#define UART_CR1_SP_Pos                           (5U)
#define UART_CR1_SP_Msk                           (0x1UL<<UART_CR1_SP_Pos)                          /*!< 0x00000020 */
#define UART_CR1_SP                               UART_CR1_SP_Msk                                   
#define UART_CR1_SBK_Pos                          (6U)
#define UART_CR1_SBK_Msk                          (0x1UL<<UART_CR1_SBK_Pos)                         /*!< 0x00000040 */
#define UART_CR1_SBK                              UART_CR1_SBK_Msk                                  
#define UART_CR1_SWAP_Pos                         (8U)
#define UART_CR1_SWAP_Msk                         (0x1UL<<UART_CR1_SWAP_Pos)                        /*!< 0x00000100 */
#define UART_CR1_SWAP                             UART_CR1_SWAP_Msk                                 
#define UART_CR1_MSBFIRST_Pos                     (9U)
#define UART_CR1_MSBFIRST_Msk                     (0x1UL<<UART_CR1_MSBFIRST_Pos)                    /*!< 0x00000200 */
#define UART_CR1_MSBFIRST                         UART_CR1_MSBFIRST_Msk                             

/********************************* Bit definition for UART_CR2 register *********************************************/
#define UART_CR2_RXNEIE_Pos                       (0U)
#define UART_CR2_RXNEIE_Msk                       (0x1UL<<UART_CR2_RXNEIE_Pos)                      /*!< 0x00000001 */
#define UART_CR2_RXNEIE                           UART_CR2_RXNEIE_Msk                               
#define UART_CR2_TDREIE_Pos                       (1U)
#define UART_CR2_TDREIE_Msk                       (0x1UL<<UART_CR2_TDREIE_Pos)                      /*!< 0x00000002 */
#define UART_CR2_TDREIE                           UART_CR2_TDREIE_Msk                               
#define UART_CR2_LSIE_Pos                         (2U)
#define UART_CR2_LSIE_Msk                         (0x1UL<<UART_CR2_LSIE_Pos)                        /*!< 0x00000004 */
#define UART_CR2_LSIE                             UART_CR2_LSIE_Msk                                 
#define UART_CR2_BUSYERRIE_Pos                    (3U)
#define UART_CR2_BUSYERRIE_Msk                    (0x1UL<<UART_CR2_BUSYERRIE_Pos)                   /*!< 0x00000008 */
#define UART_CR2_BUSYERRIE                        UART_CR2_BUSYERRIE_Msk                            
#define UART_CR2_TXEIE_Pos                        (4U)
#define UART_CR2_TXEIE_Msk                        (0x1UL<<UART_CR2_TXEIE_Pos)                       /*!< 0x00000010 */
#define UART_CR2_TXEIE                            UART_CR2_TXEIE_Msk                                

/********************************* Bit definition for UART_CR3 register *********************************************/
#define UART_CR3_M_E_Pos                          (0U)
#define UART_CR3_M_E_Msk                          (0x1UL<<UART_CR3_M_E_Pos)                         /*!< 0x00000001 */
#define UART_CR3_M_E                              UART_CR3_M_E_Msk                                  
#define UART_CR3_ADDR_MATCH_Pos                   (1U)
#define UART_CR3_ADDR_MATCH_Msk                   (0x1UL<<UART_CR3_ADDR_MATCH_Pos)                  /*!< 0x00000002 */
#define UART_CR3_ADDR_MATCH                       UART_CR3_ADDR_MATCH_Msk                           
#define UART_CR3_SEND_ADDR_Pos                    (2U)
#define UART_CR3_SEND_ADDR_Msk                    (0x1UL<<UART_CR3_SEND_ADDR_Pos)                   /*!< 0x00000004 */
#define UART_CR3_SEND_ADDR                        UART_CR3_SEND_ADDR_Msk                            
#define UART_CR3_TX_MODE_Pos                      (3U)
#define UART_CR3_TX_MODE_Msk                      (0x1UL<<UART_CR3_TX_MODE_Pos)                     /*!< 0x00000008 */
#define UART_CR3_TX_MODE                          UART_CR3_TX_MODE_Msk                              
#define UART_CR3_DMAR_Pos                         (4U)
#define UART_CR3_DMAR_Msk                         (0x1UL<<UART_CR3_DMAR_Pos)                        /*!< 0x00000010 */
#define UART_CR3_DMAR                             UART_CR3_DMAR_Msk                                 
#define UART_CR3_DMAT_Pos                         (5U)
#define UART_CR3_DMAT_Msk                         (0x1UL<<UART_CR3_DMAT_Pos)                        /*!< 0x00000020 */
#define UART_CR3_DMAT                             UART_CR3_DMAT_Msk                                 
#define UART_CR3_DMA_SOFT_ACK_Pos                 (6U)
#define UART_CR3_DMA_SOFT_ACK_Msk                 (0x1UL<<UART_CR3_DMA_SOFT_ACK_Pos)                /*!< 0x00000040 */
#define UART_CR3_DMA_SOFT_ACK                     UART_CR3_DMA_SOFT_ACK_Msk                         

/********************************* Bit definition for UART_RAR register *********************************************/
#define UART_RAR_RAR_Pos                          (0U)
#define UART_RAR_RAR_Msk                          (0xFFUL<<UART_RAR_RAR_Pos)                        /*!< 0x000000FF */
#define UART_RAR_RAR                              UART_RAR_RAR_Msk

/********************************* Bit definition for UART_TAR register *********************************************/
#define UART_TAR_TAR_Pos                          (0U)
#define UART_TAR_TAR_Msk                          (0xFFUL<<UART_TAR_TAR_Pos)                        /*!< 0x000000FF */
#define UART_TAR_TAR                              UART_TAR_TAR_Msk

/********************************* Bit definition for UART_BRRF register ********************************************/
#define UART_BRRF_BRRF_Pos                        (0U)
#define UART_BRRF_BRRF_Msk                        (0xFUL<<UART_BRRF_BRRF_Pos)                       /*!< 0x0000000F */
#define UART_BRRF_BRRF                            UART_BRRF_BRRF_Msk
#define UART_BRRF_BRRF_0                          (0x1UL<<UART_BRRF_BRRF_Pos)                       /*!< 0x00000001 */
#define UART_BRRF_BRRF_1                          (0x2UL<<UART_BRRF_BRRF_Pos)                       /*!< 0x00000002 */
#define UART_BRRF_BRRF_2                          (0x4UL<<UART_BRRF_BRRF_Pos)                       /*!< 0x00000004 */
#define UART_BRRF_BRRF_3                          (0x8UL<<UART_BRRF_BRRF_Pos)                       /*!< 0x00000008 */

/********************************************************************************************************************/
/********************************* LPUART ***************************************************************************/
/********************************************************************************************************************/

/********************************* Bit definition for LPUART_CR1 register *******************************************/
#define LPUART_CR1_UE_Pos                         (0U)
#define LPUART_CR1_UE_Msk                         (0x1UL<<LPUART_CR1_UE_Pos)                        /*!< 0x00000001 */
#define LPUART_CR1_UE                             LPUART_CR1_UE_Msk                                 /*!< LPUART enabled */
#define LPUART_CR1_UESM_Pos                       (1U)
#define LPUART_CR1_UESM_Msk                       (0x1UL<<LPUART_CR1_UESM_Pos)                      /*!< 0x00000002 */
#define LPUART_CR1_UESM                           LPUART_CR1_UESM_Msk                               /*!< LPUART enabled in Stop mode */
#define LPUART_CR1_RE_Pos                         (2U)
#define LPUART_CR1_RE_Msk                         (0x1UL<<LPUART_CR1_RE_Pos)                        /*!< 0x00000004 */
#define LPUART_CR1_RE                             LPUART_CR1_RE_Msk                                 /*!< Receive enable */
#define LPUART_CR1_TE_Pos                         (3U)
#define LPUART_CR1_TE_Msk                         (0x1UL<<LPUART_CR1_TE_Pos)                        /*!< 0x00000008 */
#define LPUART_CR1_TE                             LPUART_CR1_TE_Msk                                 /*!< Transfer enable */
#define LPUART_CR1_IDLEIE_Pos                     (4U)
#define LPUART_CR1_IDLEIE_Msk                     (0x1UL<<LPUART_CR1_IDLEIE_Pos)                    /*!< 0x00000010 */
#define LPUART_CR1_IDLEIE                         LPUART_CR1_IDLEIE_Msk                             /*!< IDLE interrupt enable */
#define LPUART_CR1_RXNEIE_Pos                     (5U)
#define LPUART_CR1_RXNEIE_Msk                     (0x1UL<<LPUART_CR1_RXNEIE_Pos)                    /*!< 0x00000020 */
#define LPUART_CR1_RXNEIE                         LPUART_CR1_RXNEIE_Msk                             /*!< RX non-null interrupt enable */
#define LPUART_CR1_TCIE_Pos                       (6U)
#define LPUART_CR1_TCIE_Msk                       (0x1UL<<LPUART_CR1_TCIE_Pos)                      /*!< 0x00000040 */
#define LPUART_CR1_TCIE                           LPUART_CR1_TCIE_Msk                               /*!< End of Transfer interrupt enabled */
#define LPUART_CR1_TXEIE_Pos                      (7U)
#define LPUART_CR1_TXEIE_Msk                      (0x1UL<<LPUART_CR1_TXEIE_Pos)                     /*!< 0x00000080 */
#define LPUART_CR1_TXEIE                          LPUART_CR1_TXEIE_Msk                              /*!< TX is not full interrupt enabled */
#define LPUART_CR1_PEIE_Pos                       (8U)
#define LPUART_CR1_PEIE_Msk                       (0x1UL<<LPUART_CR1_PEIE_Pos)                      /*!< 0x00000100 */
#define LPUART_CR1_PEIE                           LPUART_CR1_PEIE_Msk                               /*!< PE interrupt enable */
#define LPUART_CR1_PS_Pos                         (9U)
#define LPUART_CR1_PS_Msk                         (0x1UL<<LPUART_CR1_PS_Pos)                        /*!< 0x00000200 */
#define LPUART_CR1_PS                             LPUART_CR1_PS_Msk                                 /*!< Parity selection */
#define LPUART_CR1_PCE_Pos                        (10U)
#define LPUART_CR1_PCE_Msk                        (0x1UL<<LPUART_CR1_PCE_Pos)                       /*!< 0x00000400 */
#define LPUART_CR1_PCE                            LPUART_CR1_PCE_Msk                                /*!< Parity control */
#define LPUART_CR1_WAKE_Pos                       (11U)
#define LPUART_CR1_WAKE_Msk                       (0x1UL<<LPUART_CR1_WAKE_Pos)                      /*!< 0x00000800 */
#define LPUART_CR1_WAKE                           LPUART_CR1_WAKE_Msk                               /*!< Receive wake-up mode */
#define LPUART_CR1_M0_Pos                         (12U)
#define LPUART_CR1_M0_Msk                         (0x1UL<<LPUART_CR1_M0_Pos)                        /*!< 0x00001000 */
#define LPUART_CR1_M0                             LPUART_CR1_M0_Msk                                 /*!< Configure the word length in combination with M1 */
#define LPUART_CR1_MME_Pos                        (13U)
#define LPUART_CR1_MME_Msk                        (0x1UL<<LPUART_CR1_MME_Pos)                       /*!< 0x00002000 */
#define LPUART_CR1_MME                            LPUART_CR1_MME_Msk                                /*!< Silent mode enabled */
#define LPUART_CR1_CMIE_Pos                       (14U)
#define LPUART_CR1_CMIE_Msk                       (0x1UL<<LPUART_CR1_CMIE_Pos)                      /*!< 0x00004000 */
#define LPUART_CR1_CMIE                           LPUART_CR1_CMIE_Msk                               /*!< Character match interrupt enabled */
#define LPUART_CR1_DEDT_Pos                       (16U)
#define LPUART_CR1_DEDT_Msk                       (0x1FUL<<LPUART_CR1_DEDT_Pos)                     /*!< 0x001F0000 */
#define LPUART_CR1_DEDT                           LPUART_CR1_DEDT_Msk                               /*!< The time between the transmit frame stop bit and the invalid DE (driver enable) signal */
#define LPUART_CR1_DEDT_0                         (0x1UL<<LPUART_CR1_DEDT_Pos)                      /*!< 0x00010000 */
#define LPUART_CR1_DEDT_1                         (0x2UL<<LPUART_CR1_DEDT_Pos)                      /*!< 0x00020000 */
#define LPUART_CR1_DEDT_2                         (0x4UL<<LPUART_CR1_DEDT_Pos)                      /*!< 0x00040000 */
#define LPUART_CR1_DEDT_3                         (0x8UL<<LPUART_CR1_DEDT_Pos)                      /*!< 0x00080000 */
#define LPUART_CR1_DEDT_4                         (0x10UL<<LPUART_CR1_DEDT_Pos)                     /*!< 0x00100000 */
#define LPUART_CR1_DEAT_Pos                       (21U)
#define LPUART_CR1_DEAT_Msk                       (0x1FUL<<LPUART_CR1_DEAT_Pos)                     /*!< 0x03E00000 */
#define LPUART_CR1_DEAT                           LPUART_CR1_DEAT_Msk                               /*!< The time between the DE (driver enable) signal validity and the start bit */
#define LPUART_CR1_DEAT_0                         (0x1UL<<LPUART_CR1_DEAT_Pos)                      /*!< 0x00200000 */
#define LPUART_CR1_DEAT_1                         (0x2UL<<LPUART_CR1_DEAT_Pos)                      /*!< 0x00400000 */
#define LPUART_CR1_DEAT_2                         (0x4UL<<LPUART_CR1_DEAT_Pos)                      /*!< 0x00800000 */
#define LPUART_CR1_DEAT_3                         (0x8UL<<LPUART_CR1_DEAT_Pos)                      /*!< 0x01000000 */
#define LPUART_CR1_DEAT_4                         (0x10UL<<LPUART_CR1_DEAT_Pos)                     /*!< 0x02000000 */
#define LPUART_CR1_M1_Pos                         (28U)
#define LPUART_CR1_M1_Msk                         (0x1UL<<LPUART_CR1_M1_Pos)                        /*!< 0x10000000 */
#define LPUART_CR1_M1                             LPUART_CR1_M1_Msk                                 /*!< The value of {M1,M0} the configurate length */
#define LPUART_CR1_FIFOEN_Pos                     (29U)
#define LPUART_CR1_FIFOEN_Msk                     (0x1UL<<LPUART_CR1_FIFOEN_Pos)                    /*!< 0x20000000 */
#define LPUART_CR1_FIFOEN                         LPUART_CR1_FIFOEN_Msk                             /*!< FIFO mode enabled */
#define LPUART_CR1_TXFEIE_Pos                     (30U)
#define LPUART_CR1_TXFEIE_Msk                     (0x1UL<<LPUART_CR1_TXFEIE_Pos)                    /*!< 0x40000000 */
#define LPUART_CR1_TXFEIE                         LPUART_CR1_TXFEIE_Msk                             /*!< TXFIFO null interrupt enabled */
#define LPUART_CR1_RXFFIE_Pos                     (31U)
#define LPUART_CR1_RXFFIE_Msk                     (0x1UL<<LPUART_CR1_RXFFIE_Pos)                    /*!< 0x80000000 */
#define LPUART_CR1_RXFFIE                         LPUART_CR1_RXFFIE_Msk                             /*!< RXFIFO full interrupt enabled */

/********************************* Bit definition for LPUART_CR2 register *******************************************/
#define LPUART_CR2_ADDM7_Pos                      (4U)
#define LPUART_CR2_ADDM7_Msk                      (0x1UL<<LPUART_CR2_ADDM7_Pos)                     /*!< 0x00000010 */
#define LPUART_CR2_ADDM7                          LPUART_CR2_ADDM7_Msk                              /*!< 7bit/4bit address detection configuration */
#define LPUART_CR2_STOP_Pos                       (12U)
#define LPUART_CR2_STOP_Msk                       (0x3UL<<LPUART_CR2_STOP_Pos)                      /*!< 0x00003000 */
#define LPUART_CR2_STOP                           LPUART_CR2_STOP_Msk                               /*!< Stop bit configuration */
#define LPUART_CR2_STOP_0                         (0x1UL<<LPUART_CR2_STOP_Pos)                      /*!< 0x00001000 */
#define LPUART_CR2_STOP_1                         (0x2UL<<LPUART_CR2_STOP_Pos)                      /*!< 0x00002000 */
#define LPUART_CR2_SWAP_Pos                       (15U)
#define LPUART_CR2_SWAP_Msk                       (0x1UL<<LPUART_CR2_SWAP_Pos)                      /*!< 0x00008000 */
#define LPUART_CR2_SWAP                           LPUART_CR2_SWAP_Msk                               /*!< TX/RX pin interchangeable */
#define LPUART_CR2_RXINV_Pos                      (16U)
#define LPUART_CR2_RXINV_Msk                      (0x1UL<<LPUART_CR2_RXINV_Pos)                     /*!< 0x00010000 */
#define LPUART_CR2_RXINV                          LPUART_CR2_RXINV_Msk                              /*!< The RX pin is active level inverting */
#define LPUART_CR2_TXINV_Pos                      (17U)
#define LPUART_CR2_TXINV_Msk                      (0x1UL<<LPUART_CR2_TXINV_Pos)                     /*!< 0x00020000 */
#define LPUART_CR2_TXINV                          LPUART_CR2_TXINV_Msk                              /*!< TX pin active level inverted */
#define LPUART_CR2_DATAINV_Pos                    (18U)
#define LPUART_CR2_DATAINV_Msk                    (0x1UL<<LPUART_CR2_DATAINV_Pos)                   /*!< 0x00040000 */
#define LPUART_CR2_DATAINV                        LPUART_CR2_DATAINV_Msk                            /*!< Inverse binary data processing */
#define LPUART_CR2_MSBFIRST_Pos                   (19U)
#define LPUART_CR2_MSBFIRST_Msk                   (0x1UL<<LPUART_CR2_MSBFIRST_Pos)                  /*!< 0x00080000 */
#define LPUART_CR2_MSBFIRST                       LPUART_CR2_MSBFIRST_Msk                           /*!< MSB first */
#define LPUART_CR2_TXOE_ALWAYS_ON_Pos             (20U)
#define LPUART_CR2_TXOE_ALWAYS_ON_Msk             (0x1UL<<LPUART_CR2_TXOE_ALWAYS_ON_Pos)            /*!< 0x00100000 */
#define LPUART_CR2_TXOE_ALWAYS_ON                 LPUART_CR2_TXOE_ALWAYS_ON_Msk                     
#define LPUART_CR2_ADD_Pos                        (24U)
#define LPUART_CR2_ADD_Msk                        (0xFFUL<<LPUART_CR2_ADD_Pos)                      /*!< 0xFF000000 */
#define LPUART_CR2_ADD                            LPUART_CR2_ADD_Msk                                /*!< LPUART address */

/********************************* Bit definition for LPUART_CR3 register *******************************************/
#define LPUART_CR3_EIE_Pos                        (0U)
#define LPUART_CR3_EIE_Msk                        (0x1UL<<LPUART_CR3_EIE_Pos)                       /*!< 0x00000001 */
#define LPUART_CR3_EIE                            LPUART_CR3_EIE_Msk                                /*!< Error interrupts are enabled */
#define LPUART_CR3_HDSEL_Pos                      (3U)
#define LPUART_CR3_HDSEL_Msk                      (0x1UL<<LPUART_CR3_HDSEL_Pos)                     /*!< 0x00000008 */
#define LPUART_CR3_HDSEL                          LPUART_CR3_HDSEL_Msk                              /*!< Half-duplex selection */
#define LPUART_CR3_DMAR_Pos                       (6U)
#define LPUART_CR3_DMAR_Msk                       (0x1UL<<LPUART_CR3_DMAR_Pos)                      /*!< 0x00000040 */
#define LPUART_CR3_DMAR                           LPUART_CR3_DMAR_Msk                               /*!< Enable DMA on reception */
#define LPUART_CR3_DMAT_Pos                       (7U)
#define LPUART_CR3_DMAT_Msk                       (0x1UL<<LPUART_CR3_DMAT_Pos)                      /*!< 0x00000080 */
#define LPUART_CR3_DMAT                           LPUART_CR3_DMAT_Msk                               /*!< Enable DMA while transmitting */
#define LPUART_CR3_RTSE_Pos                       (8U)
#define LPUART_CR3_RTSE_Msk                       (0x1UL<<LPUART_CR3_RTSE_Pos)                      /*!< 0x00000100 */
#define LPUART_CR3_RTSE                           LPUART_CR3_RTSE_Msk                               /*!< RTS enabled */
#define LPUART_CR3_CTSE_Pos                       (9U)
#define LPUART_CR3_CTSE_Msk                       (0x1UL<<LPUART_CR3_CTSE_Pos)                      /*!< 0x00000200 */
#define LPUART_CR3_CTSE                           LPUART_CR3_CTSE_Msk                               /*!< CTS enabled */
#define LPUART_CR3_CTSIE_Pos                      (10U)
#define LPUART_CR3_CTSIE_Msk                      (0x1UL<<LPUART_CR3_CTSIE_Pos)                     /*!< 0x00000400 */
#define LPUART_CR3_CTSIE                          LPUART_CR3_CTSIE_Msk                              /*!< CTS interrupt enable */
#define LPUART_CR3_OVRDIS_Pos                     (12U)
#define LPUART_CR3_OVRDIS_Msk                     (0x1UL<<LPUART_CR3_OVRDIS_Pos)                    /*!< 0x00001000 */
#define LPUART_CR3_OVRDIS                         LPUART_CR3_OVRDIS_Msk                             /*!< Overrun is prohibited */
#define LPUART_CR3_DDRE_Pos                       (13U)
#define LPUART_CR3_DDRE_Msk                       (0x1UL<<LPUART_CR3_DDRE_Pos)                      /*!< 0x00002000 */
#define LPUART_CR3_DDRE                           LPUART_CR3_DDRE_Msk                               /*!< Whether DMA is disabled when receiving an error */
#define LPUART_CR3_DEM_Pos                        (14U)
#define LPUART_CR3_DEM_Msk                        (0x1UL<<LPUART_CR3_DEM_Pos)                       /*!< 0x00004000 */
#define LPUART_CR3_DEM                            LPUART_CR3_DEM_Msk                                /*!< DE mode enabled */
#define LPUART_CR3_DEP_Pos                        (15U)
#define LPUART_CR3_DEP_Msk                        (0x1UL<<LPUART_CR3_DEP_Pos)                       /*!< 0x00008000 */
#define LPUART_CR3_DEP                            LPUART_CR3_DEP_Msk                                /*!< DE polarity selection */
#define LPUART_CR3_WUS_Pos                        (20U)
#define LPUART_CR3_WUS_Msk                        (0x3UL<<LPUART_CR3_WUS_Pos)                       /*!< 0x00300000 */
#define LPUART_CR3_WUS                            LPUART_CR3_WUS_Msk                                /*!< Low-power wake-up options */
#define LPUART_CR3_WUS_0                          (0x1UL<<LPUART_CR3_WUS_Pos)                       /*!< 0x00100000 */
#define LPUART_CR3_WUS_1                          (0x2UL<<LPUART_CR3_WUS_Pos)                       /*!< 0x00200000 */
#define LPUART_CR3_WUFIE_Pos                      (22U)
#define LPUART_CR3_WUFIE_Msk                      (0x1UL<<LPUART_CR3_WUFIE_Pos)                     /*!< 0x00400000 */
#define LPUART_CR3_WUFIE                          LPUART_CR3_WUFIE_Msk                              /*!< Low-power wake-up interrupt enable */
#define LPUART_CR3_TXFTIE_Pos                     (23U)
#define LPUART_CR3_TXFTIE_Msk                     (0x1UL<<LPUART_CR3_TXFTIE_Pos)                    /*!< 0x00800000 */
#define LPUART_CR3_TXFTIE                         LPUART_CR3_TXFTIE_Msk                             /*!< TXFIFO threshold interrupt enabled */
#define LPUART_CR3_RXFTCFG_Pos                    (25U)
#define LPUART_CR3_RXFTCFG_Msk                    (0x7UL<<LPUART_CR3_RXFTCFG_Pos)                   /*!< 0x0E000000 */
#define LPUART_CR3_RXFTCFG                        LPUART_CR3_RXFTCFG_Msk                            /*!< RXFIFO full threshold configuration */
#define LPUART_CR3_RXFTCFG_0                      (0x1UL<<LPUART_CR3_RXFTCFG_Pos)                   /*!< 0x02000000 */
#define LPUART_CR3_RXFTCFG_1                      (0x2UL<<LPUART_CR3_RXFTCFG_Pos)                   /*!< 0x04000000 */
#define LPUART_CR3_RXFTCFG_2                      (0x4UL<<LPUART_CR3_RXFTCFG_Pos)                   /*!< 0x08000000 */
#define LPUART_CR3_RXFTIE_Pos                     (28U)
#define LPUART_CR3_RXFTIE_Msk                     (0x1UL<<LPUART_CR3_RXFTIE_Pos)                    /*!< 0x10000000 */
#define LPUART_CR3_RXFTIE                         LPUART_CR3_RXFTIE_Msk                             /*!< RXFIFO threshold interrupt enabled */
#define LPUART_CR3_TXFTCFG_Pos                    (29U)
#define LPUART_CR3_TXFTCFG_Msk                    (0x7UL<<LPUART_CR3_TXFTCFG_Pos)                   /*!< 0xE0000000 */
#define LPUART_CR3_TXFTCFG                        LPUART_CR3_TXFTCFG_Msk                            /*!< TXFIFO threshold configuration */
#define LPUART_CR3_TXFTCFG_0                      (0x1UL<<LPUART_CR3_TXFTCFG_Pos)                   /*!< 0x20000000 */
#define LPUART_CR3_TXFTCFG_1                      (0x2UL<<LPUART_CR3_TXFTCFG_Pos)                   /*!< 0x40000000 */
#define LPUART_CR3_TXFTCFG_2                      (0x4UL<<LPUART_CR3_TXFTCFG_Pos)                   /*!< 0x80000000 */

/********************************* Bit definition for LPUART_BRR register *******************************************/
#define LPUART_BRR_BBR_Pos                        (0U)
#define LPUART_BRR_BBR_Msk                        (0xFFFFFUL<<LPUART_BRR_BBR_Pos)                   /*!< 0x000FFFFF */
#define LPUART_BRR_BBR                            LPUART_BRR_BBR_Msk                                /*!< LPUART baud rate */

/********************************* Bit definition for LPUART_RQR register *******************************************/
#define LPUART_RQR_SBKRQ_Pos                      (1U)
#define LPUART_RQR_SBKRQ_Msk                      (0x1UL<<LPUART_RQR_SBKRQ_Pos)                     /*!< 0x00000002 */
#define LPUART_RQR_SBKRQ                          LPUART_RQR_SBKRQ_Msk                              /*!< Send an abort request */
#define LPUART_RQR_MMRQ_Pos                       (2U)
#define LPUART_RQR_MMRQ_Msk                       (0x1UL<<LPUART_RQR_MMRQ_Pos)                      /*!< 0x00000004 */
#define LPUART_RQR_MMRQ                           LPUART_RQR_MMRQ_Msk                               /*!< Silent mode request */
#define LPUART_RQR_RXFRQ_Pos                      (3U)
#define LPUART_RQR_RXFRQ_Msk                      (0x1UL<<LPUART_RQR_RXFRQ_Pos)                     /*!< 0x00000008 */
#define LPUART_RQR_RXFRQ                          LPUART_RQR_RXFRQ_Msk                              /*!< Receive a data refresh request */
#define LPUART_RQR_TXFRQ_Pos                      (4U)
#define LPUART_RQR_TXFRQ_Msk                      (0x1UL<<LPUART_RQR_TXFRQ_Pos)                     /*!< 0x00000010 */
#define LPUART_RQR_TXFRQ                          LPUART_RQR_TXFRQ_Msk                              /*!< Route a data refresh request */

/********************************* Bit definition for LPUART_ISR register *******************************************/
#define LPUART_ISR_PE_Pos                         (0U)
#define LPUART_ISR_PE_Msk                         (0x1UL<<LPUART_ISR_PE_Pos)                        /*!< 0x00000001 */
#define LPUART_ISR_PE                             LPUART_ISR_PE_Msk                                 /*!< Parity error */
#define LPUART_ISR_FE_Pos                         (1U)
#define LPUART_ISR_FE_Msk                         (0x1UL<<LPUART_ISR_FE_Pos)                        /*!< 0x00000002 */
#define LPUART_ISR_FE                             LPUART_ISR_FE_Msk                                 /*!< Frame error flag */
#define LPUART_ISR_NE_Pos                         (2U)
#define LPUART_ISR_NE_Msk                         (0x1UL<<LPUART_ISR_NE_Pos)                        /*!< 0x00000004 */
#define LPUART_ISR_NE                             LPUART_ISR_NE_Msk                                 /*!< START bit noise flag */
#define LPUART_ISR_ORE_Pos                        (3U)
#define LPUART_ISR_ORE_Msk                        (0x1UL<<LPUART_ISR_ORE_Pos)                       /*!< 0x00000008 */
#define LPUART_ISR_ORE                            LPUART_ISR_ORE_Msk                                /*!< Overrun error flag */
#define LPUART_ISR_IDLE_Pos                       (4U)
#define LPUART_ISR_IDLE_Msk                       (0x1UL<<LPUART_ISR_IDLE_Pos)                      /*!< 0x00000010 */
#define LPUART_ISR_IDLE                           LPUART_ISR_IDLE_Msk                               /*!< idle flag */
#define LPUART_ISR_RXNE_Pos                       (5U)
#define LPUART_ISR_RXNE_Msk                       (0x1UL<<LPUART_ISR_RXNE_Pos)                      /*!< 0x00000020 */
#define LPUART_ISR_RXNE                           LPUART_ISR_RXNE_Msk                               /*!< RX register not empty */
#define LPUART_ISR_TC_Pos                         (6U)
#define LPUART_ISR_TC_Msk                         (0x1UL<<LPUART_ISR_TC_Pos)                        /*!< 0x00000040 */
#define LPUART_ISR_TC                             LPUART_ISR_TC_Msk                                 /*!< Transmission completion flag */
#define LPUART_ISR_TXE_Pos                        (7U)
#define LPUART_ISR_TXE_Msk                        (0x1UL<<LPUART_ISR_TXE_Pos)                       /*!< 0x00000080 */
#define LPUART_ISR_TXE                            LPUART_ISR_TXE_Msk                                /*!< TX register not full */
#define LPUART_ISR_CTSIF_Pos                      (9U)
#define LPUART_ISR_CTSIF_Msk                      (0x1UL<<LPUART_ISR_CTSIF_Pos)                     /*!< 0x00000200 */
#define LPUART_ISR_CTSIF                          LPUART_ISR_CTSIF_Msk                              /*!< CTS interrupt flag */
#define LPUART_ISR_CTS_Pos                        (10U)
#define LPUART_ISR_CTS_Msk                        (0x1UL<<LPUART_ISR_CTS_Pos)                       /*!< 0x00000400 */
#define LPUART_ISR_CTS                            LPUART_ISR_CTS_Msk                                /*!< CTS flag */
#define LPUART_ISR_BUSY_Pos                       (16U)
#define LPUART_ISR_BUSY_Msk                       (0x1UL<<LPUART_ISR_BUSY_Pos)                      /*!< 0x00010000 */
#define LPUART_ISR_BUSY                           LPUART_ISR_BUSY_Msk                               /*!< Busy flag */
#define LPUART_ISR_CMF_Pos                        (17U)
#define LPUART_ISR_CMF_Msk                        (0x1UL<<LPUART_ISR_CMF_Pos)                       /*!< 0x00020000 */
#define LPUART_ISR_CMF                            LPUART_ISR_CMF_Msk                                /*!< Address match flag */
#define LPUART_ISR_SBKF_Pos                       (18U)
#define LPUART_ISR_SBKF_Msk                       (0x1UL<<LPUART_ISR_SBKF_Pos)                      /*!< 0x00040000 */
#define LPUART_ISR_SBKF                           LPUART_ISR_SBKF_Msk                               /*!< Send abort flag */
#define LPUART_ISR_RWU_Pos                        (19U)
#define LPUART_ISR_RWU_Msk                        (0x1UL<<LPUART_ISR_RWU_Pos)                       /*!< 0x00080000 */
#define LPUART_ISR_RWU                            LPUART_ISR_RWU_Msk                                /*!< Receive Mute mode wake-up flag */
#define LPUART_ISR_WUF_Pos                        (20U)
#define LPUART_ISR_WUF_Msk                        (0x1UL<<LPUART_ISR_WUF_Pos)                       /*!< 0x00100000 */
#define LPUART_ISR_WUF                            LPUART_ISR_WUF_Msk                                /*!< Wake flag from low-power mode */
#define LPUART_ISR_TEACK_Pos                      (21U)
#define LPUART_ISR_TEACK_Msk                      (0x1UL<<LPUART_ISR_TEACK_Pos)                     /*!< 0x00200000 */
#define LPUART_ISR_TEACK                          LPUART_ISR_TEACK_Msk                              /*!< Transport enable acknowledgement flag */
#define LPUART_ISR_REACK_Pos                      (22U)
#define LPUART_ISR_REACK_Msk                      (0x1UL<<LPUART_ISR_REACK_Pos)                     /*!< 0x00400000 */
#define LPUART_ISR_REACK                          LPUART_ISR_REACK_Msk                              /*!< Receive the enable acknowledgment flag */
#define LPUART_ISR_TXFE_Pos                       (23U)
#define LPUART_ISR_TXFE_Msk                       (0x1UL<<LPUART_ISR_TXFE_Pos)                      /*!< 0x00800000 */
#define LPUART_ISR_TXFE                           LPUART_ISR_TXFE_Msk                               /*!< TXFIFO empty */
#define LPUART_ISR_RXFF_Pos                       (24U)
#define LPUART_ISR_RXFF_Msk                       (0x1UL<<LPUART_ISR_RXFF_Pos)                      /*!< 0x01000000 */
#define LPUART_ISR_RXFF                           LPUART_ISR_RXFF_Msk                               /*!< RXFIFO full logo */
#define LPUART_ISR_RXFT_Pos                       (26U)
#define LPUART_ISR_RXFT_Msk                       (0x1UL<<LPUART_ISR_RXFT_Pos)                      /*!< 0x04000000 */
#define LPUART_ISR_RXFT                           LPUART_ISR_RXFT_Msk                               /*!< RCFIFO threshold flag */
#define LPUART_ISR_TXFT_Pos                       (27U)
#define LPUART_ISR_TXFT_Msk                       (0x1UL<<LPUART_ISR_TXFT_Pos)                      /*!< 0x08000000 */
#define LPUART_ISR_TXFT                           LPUART_ISR_TXFT_Msk                               /*!< TXFIFO threshold flag */

/********************************* Bit definition for LPUART_ICR register *******************************************/
#define LPUART_ICR_PECF_Pos                       (0U)
#define LPUART_ICR_PECF_Msk                       (0x1UL<<LPUART_ICR_PECF_Pos)                      /*!< 0x00000001 */
#define LPUART_ICR_PECF                           LPUART_ICR_PECF_Msk                               /*!< Check value error flag reset */
#define LPUART_ICR_FECF_Pos                       (1U)
#define LPUART_ICR_FECF_Msk                       (0x1UL<<LPUART_ICR_FECF_Pos)                      /*!< 0x00000002 */
#define LPUART_ICR_FECF                           LPUART_ICR_FECF_Msk                               /*!< Frame error flag reset */
#define LPUART_ICR_NECF_Pos                       (2U)
#define LPUART_ICR_NECF_Msk                       (0x1UL<<LPUART_ICR_NECF_Pos)                      /*!< 0x00000004 */
#define LPUART_ICR_NECF                           LPUART_ICR_NECF_Msk                               /*!< Clear the START bit noise flag */
#define LPUART_ICR_ORECF_Pos                      (3U)
#define LPUART_ICR_ORECF_Msk                      (0x1UL<<LPUART_ICR_ORECF_Pos)                     /*!< 0x00000008 */
#define LPUART_ICR_ORECF                          LPUART_ICR_ORECF_Msk                              /*!< Overrun error flag reset */
#define LPUART_ICR_IDLECF_Pos                     (4U)
#define LPUART_ICR_IDLECF_Msk                     (0x1UL<<LPUART_ICR_IDLECF_Pos)                    /*!< 0x00000010 */
#define LPUART_ICR_IDLECF                         LPUART_ICR_IDLECF_Msk                             /*!< Clear idle flag  */
#define LPUART_ICR_TCCF_Pos                       (6U)
#define LPUART_ICR_TCCF_Msk                       (0x1UL<<LPUART_ICR_TCCF_Pos)                      /*!< 0x00000040 */
#define LPUART_ICR_TCCF                           LPUART_ICR_TCCF_Msk                               /*!< Transfer completion flag reset */
#define LPUART_ICR_CTSCF_Pos                      (9U)
#define LPUART_ICR_CTSCF_Msk                      (0x1UL<<LPUART_ICR_CTSCF_Pos)                     /*!< 0x00000200 */
#define LPUART_ICR_CTSCF                          LPUART_ICR_CTSCF_Msk                              /*!< CTS flag reset */
#define LPUART_ICR_CMCF_Pos                       (17U)
#define LPUART_ICR_CMCF_Msk                       (0x1UL<<LPUART_ICR_CMCF_Pos)                      /*!< 0x00020000 */
#define LPUART_ICR_CMCF                           LPUART_ICR_CMCF_Msk                               /*!< Address matching flag reset */
#define LPUART_ICR_WUCF_Pos                       (20U)
#define LPUART_ICR_WUCF_Msk                       (0x1UL<<LPUART_ICR_WUCF_Pos)                      /*!< 0x00100000 */
#define LPUART_ICR_WUCF                           LPUART_ICR_WUCF_Msk                               /*!< Low power wake-up flag reset */

/********************************* Bit definition for LPUART_RDR register *******************************************/
#define LPUART_RDR_RDR_Pos                        (0U)
#define LPUART_RDR_RDR_Msk                        (0x1FFUL<<LPUART_RDR_RDR_Pos)                     /*!< 0x000001FF */
#define LPUART_RDR_RDR                            LPUART_RDR_RDR_Msk                                /*!< Receive Data Register */

/********************************* Bit definition for LPUART_TDR register *******************************************/
#define LPUART_TDR_TDR_Pos                        (0U)
#define LPUART_TDR_TDR_Msk                        (0x1FFUL<<LPUART_TDR_TDR_Pos)                     /*!< 0x000001FF */
#define LPUART_TDR_TDR                            LPUART_TDR_TDR_Msk                                /*!< Transmit Data Register */

/********************************* Bit definition for LPUART_PRESC register *****************************************/
#define LPUART_PRESC_PRESCALER_Pos                (0U)
#define LPUART_PRESC_PRESCALER_Msk                (0xFUL<<LPUART_PRESC_PRESCALER_Pos)               /*!< 0x0000000F */
#define LPUART_PRESC_PRESCALER                    LPUART_PRESC_PRESCALER_Msk                        /*!< Input clock prescaler register */
#define LPUART_PRESC_PRESCALER_0                  (0x1UL<<LPUART_PRESC_PRESCALER_Pos)               /*!< 0x00000001 */
#define LPUART_PRESC_PRESCALER_1                  (0x2UL<<LPUART_PRESC_PRESCALER_Pos)               /*!< 0x00000002 */
#define LPUART_PRESC_PRESCALER_2                  (0x4UL<<LPUART_PRESC_PRESCALER_Pos)               /*!< 0x00000004 */
#define LPUART_PRESC_PRESCALER_3                  (0x8UL<<LPUART_PRESC_PRESCALER_Pos)               /*!< 0x00000008 */

/********************************************************************************************************************/
/********************************* DBGMCU ***************************************************************************/
/********************************************************************************************************************/

/********************************* Bit definition for DBGMCU_IDCODE register ****************************************/
#define DBGMCU_IDCODE_REV_ID_Pos                  (0U)
#define DBGMCU_IDCODE_REV_ID_Msk                  (0xFFFFFFFFUL<<DBGMCU_IDCODE_REV_ID_Pos)          /*!< 0xFFFFFFFF */
#define DBGMCU_IDCODE_REV_ID                      DBGMCU_IDCODE_REV_ID_Msk

/********************************* Bit definition for DBGMCU_CR1 register *******************************************/
#define DBGMCU_CR1_DBG_SLEEP_Pos                  (0U)
#define DBGMCU_CR1_DBG_SLEEP_Msk                  (0x1UL<<DBGMCU_CR1_DBG_SLEEP_Pos)                 /*!< 0x00000001 */
#define DBGMCU_CR1_DBG_SLEEP                      DBGMCU_CR1_DBG_SLEEP_Msk                          
#define DBGMCU_CR1_DBG_STOP_Pos                   (1U)
#define DBGMCU_CR1_DBG_STOP_Msk                   (0x1UL<<DBGMCU_CR1_DBG_STOP_Pos)                  /*!< 0x00000002 */
#define DBGMCU_CR1_DBG_STOP                       DBGMCU_CR1_DBG_STOP_Msk                           
#define DBGMCU_CR1_DBG_STDBY_Pos                  (2U)
#define DBGMCU_CR1_DBG_STDBY_Msk                  (0x1UL<<DBGMCU_CR1_DBG_STDBY_Pos)                 /*!< 0x00000004 */
#define DBGMCU_CR1_DBG_STDBY                      DBGMCU_CR1_DBG_STDBY_Msk                          
#define DBGMCU_CR1_DBG_IWDG_STOP_Pos              (8U)
#define DBGMCU_CR1_DBG_IWDG_STOP_Msk              (0x1UL<<DBGMCU_CR1_DBG_IWDG_STOP_Pos)             /*!< 0x00000100 */
#define DBGMCU_CR1_DBG_IWDG_STOP                  DBGMCU_CR1_DBG_IWDG_STOP_Msk                      
#define DBGMCU_CR1_DBG_WWDG_STOP_Pos              (9U)
#define DBGMCU_CR1_DBG_WWDG_STOP_Msk              (0x1UL<<DBGMCU_CR1_DBG_WWDG_STOP_Pos)             /*!< 0x00000200 */
#define DBGMCU_CR1_DBG_WWDG_STOP                  DBGMCU_CR1_DBG_WWDG_STOP_Msk                      
#define DBGMCU_CR1_DBG_TIM1_STOP_Pos              (10U)
#define DBGMCU_CR1_DBG_TIM1_STOP_Msk              (0x1UL<<DBGMCU_CR1_DBG_TIM1_STOP_Pos)             /*!< 0x00000400 */
#define DBGMCU_CR1_DBG_TIM1_STOP                  DBGMCU_CR1_DBG_TIM1_STOP_Msk                      
#define DBGMCU_CR1_DBG_TIM2_STOP_Pos              (11U)
#define DBGMCU_CR1_DBG_TIM2_STOP_Msk              (0x1UL<<DBGMCU_CR1_DBG_TIM2_STOP_Pos)             /*!< 0x00000800 */
#define DBGMCU_CR1_DBG_TIM2_STOP                  DBGMCU_CR1_DBG_TIM2_STOP_Msk                      
#define DBGMCU_CR1_DBG_TIM3_STOP_Pos              (12U)
#define DBGMCU_CR1_DBG_TIM3_STOP_Msk              (0x1UL<<DBGMCU_CR1_DBG_TIM3_STOP_Pos)             /*!< 0x00001000 */
#define DBGMCU_CR1_DBG_TIM3_STOP                  DBGMCU_CR1_DBG_TIM3_STOP_Msk                      
#define DBGMCU_CR1_DBG_FDCAN_STOP_Pos               (14U)
#define DBGMCU_CR1_DBG_FDCAN_STOP_Msk               (0x1UL<<DBGMCU_CR1_DBG_FDCAN_STOP_Pos)              /*!< 0x00004000 */
#define DBGMCU_CR1_DBG_FDCAN_STOP                   DBGMCU_CR1_DBG_FDCAN_STOP_Msk                      
#define DBGMCU_CR1_DBG_I2C1_SMBUS_TIMEOUT_Pos     (15U)
#define DBGMCU_CR1_DBG_I2C1_SMBUS_TIMEOUT_Msk     (0x1UL<<DBGMCU_CR1_DBG_I2C1_SMBUS_TIMEOUT_Pos)    /*!< 0x00008000 */
#define DBGMCU_CR1_DBG_I2C1_SMBUS_TIMEOUT         DBGMCU_CR1_DBG_I2C1_SMBUS_TIMEOUT_Msk             
#define DBGMCU_CR1_DBG_I2C2_SMBUS_TIMEOUT_Pos     (16U)
#define DBGMCU_CR1_DBG_I2C2_SMBUS_TIMEOUT_Msk     (0x1UL<<DBGMCU_CR1_DBG_I2C2_SMBUS_TIMEOUT_Pos)    /*!< 0x00010000 */
#define DBGMCU_CR1_DBG_I2C2_SMBUS_TIMEOUT         DBGMCU_CR1_DBG_I2C2_SMBUS_TIMEOUT_Msk             
#define DBGMCU_CR1_DBG_TIM8_STOP_Pos              (17U)
#define DBGMCU_CR1_DBG_TIM8_STOP_Msk              (0x1UL<<DBGMCU_CR1_DBG_TIM8_STOP_Pos)             /*!< 0x00020000 */
#define DBGMCU_CR1_DBG_TIM8_STOP                  DBGMCU_CR1_DBG_TIM8_STOP_Msk                      
#define DBGMCU_CR1_DBG_TIM6_STOP_Pos              (19U)
#define DBGMCU_CR1_DBG_TIM6_STOP_Msk              (0x1UL<<DBGMCU_CR1_DBG_TIM6_STOP_Pos)             /*!< 0x00080000 */
#define DBGMCU_CR1_DBG_TIM6_STOP                  DBGMCU_CR1_DBG_TIM6_STOP_Msk                      
#define DBGMCU_CR1_DBG_TIM7_STOP_Pos              (20U)
#define DBGMCU_CR1_DBG_TIM7_STOP_Msk              (0x1UL<<DBGMCU_CR1_DBG_TIM7_STOP_Pos)             /*!< 0x00100000 */
#define DBGMCU_CR1_DBG_TIM7_STOP                  DBGMCU_CR1_DBG_TIM7_STOP_Msk                      

/********************************* Bit definition for DBGMCU_CR2 register *******************************************/
#define DBGMCU_CR2_DBG_LPTIM_STOP_Pos             (8U)
#define DBGMCU_CR2_DBG_LPTIM_STOP_Msk             (0x1UL<<DBGMCU_CR2_DBG_LPTIM_STOP_Pos)            /*!< 0x00000100 */
#define DBGMCU_CR2_DBG_LPTIM_STOP                 DBGMCU_CR2_DBG_LPTIM_STOP_Msk                      
#define DBGMCU_CR2_DBG_EPWM_CLK_OFF_Pos           (16U)
#define DBGMCU_CR2_DBG_EPWM_CLK_OFF_Msk           (0x1UL<<DBGMCU_CR2_DBG_EPWM_CLK_OFF_Pos)          /*!< 0x00010000 */
#define DBGMCU_CR2_DBG_EPWM_CLK_OFF               DBGMCU_CR2_DBG_EPWM_CLK_OFF_Msk                  
#define DBGMCU_CR2_DBG_EPWM_EN_Pos                (17U)
#define DBGMCU_CR2_DBG_EPWM_EN_Msk                (0x1UL<<DBGMCU_CR2_DBG_EPWM_EN_Pos)               /*!< 0x00020000 */
#define DBGMCU_CR2_DBG_EPWM_EN                    DBGMCU_CR2_DBG_EPWM_EN_Msk                       

/********************************************************************************************************************/
/********************************* VREFBUF **************************************************************************/
/********************************************************************************************************************/

/********************************* Bit definition for VREFBUF_CR register *******************************************/
#define VREFBUF_CR_VREFBUFEN_Pos                  (0U)
#define VREFBUF_CR_VREFBUFEN_Msk                  (0x1UL<<VREFBUF_CR_VREFBUFEN_Pos)                 /*!< 0x00000001 */
#define VREFBUF_CR_VREFBUFEN                      VREFBUF_CR_VREFBUFEN_Msk                          
#define VREFBUF_CR_VREFBUFSEL_Pos                 (1U)
#define VREFBUF_CR_VREFBUFSEL_Msk                 (0x7UL<<VREFBUF_CR_VREFBUFSEL_Pos)                /*!< 0x0000000E */
#define VREFBUF_CR_VREFBUFSEL                     VREFBUF_CR_VREFBUFSEL_Msk
#define VREFBUF_CR_VREFBUFSEL_0                   (0x1UL<<VREFBUF_CR_VREFBUFSEL_Pos)                /*!< 0x00000002 */
#define VREFBUF_CR_VREFBUFSEL_1                   (0x2UL<<VREFBUF_CR_VREFBUFSEL_Pos)                /*!< 0x00000004 */
#define VREFBUF_CR_VREFBUFSEL_2                   (0x4UL<<VREFBUF_CR_VREFBUFSEL_Pos)                /*!< 0x00000008 */

/********************************************************************************************************************/
/********************************* PWR ******************************************************************************/
/********************************************************************************************************************/

/********************************* Bit definition for PWR_CR1 register **********************************************/
#define PWR_CR1_LPMS_ACTIVE_Pos                   (0U)
#define PWR_CR1_LPMS_ACTIVE_Msk                   (0x1UL<<PWR_CR1_LPMS_ACTIVE_Pos)                  /*!< 0x00000001 */
#define PWR_CR1_LPMS_ACTIVE                       PWR_CR1_LPMS_ACTIVE_Msk                           
#define PWR_CR1_LPMS_SLP_Pos                      (1U)
#define PWR_CR1_LPMS_SLP_Msk                      (0x1UL<<PWR_CR1_LPMS_SLP_Pos)                     /*!< 0x00000002 */
#define PWR_CR1_LPMS_SLP                          PWR_CR1_LPMS_SLP_Msk                              
#define PWR_CR1_LPMS_SLP_STOP                     (0x00000000U)
#define PWR_CR1_LPMS_SLP_STANDBY                  PWR_CR1_LPMS_SLP
#define PWR_CR1_VR_MODE_SLP_Pos                   (4U)
#define PWR_CR1_VR_MODE_SLP_Msk                   (0x1UL<<PWR_CR1_VR_MODE_SLP_Pos)                  /*!< 0x00000030 */
#define PWR_CR1_VR_MODE_SLP                       PWR_CR1_VR_MODE_SLP_Msk
#define PWR_CR1_VR_MODE_SLP_STOP0                 (0x00000000U)
#define PWR_CR1_VR_MODE_SLP_STOP1                 PWR_CR1_VR_MODE_SLP
#define PWR_CR1_DBP_Pos                           (8U)
#define PWR_CR1_DBP_Msk                           (0x1UL<<PWR_CR1_DBP_Pos)                          /*!< 0x00000100 */
#define PWR_CR1_DBP                               PWR_CR1_DBP_Msk                                   
#define PWR_CR1_FLS_WUPT_Pos                      (12U)
#define PWR_CR1_FLS_WUPT_Msk                      (0x3UL<<PWR_CR1_FLS_WUPT_Pos)                     /*!< 0x00003000 */
#define PWR_CR1_FLS_WUPT                          PWR_CR1_FLS_WUPT_Msk
#define PWR_CR1_FLS_WUPT_0                        (0x1UL<<PWR_CR1_FLS_WUPT_Pos)                     /*!< 0x00001000 */
#define PWR_CR1_FLS_WUPT_1                        (0x2UL<<PWR_CR1_FLS_WUPT_Pos)                     /*!< 0x00002000 */
#define PWR_CR1_MR_VSEL_Pos                       (16U)
#define PWR_CR1_MR_VSEL_Msk                       (0x3UL<<PWR_CR1_MR_VSEL_Pos)                      /*!< 0x00030000 */
#define PWR_CR1_MR_VSEL                           PWR_CR1_MR_VSEL_Msk
#define PWR_CR1_MR_VSEL_0                         (0x1UL<<PWR_CR1_MR_VSEL_Pos)                      /*!< 0x00010000 */
#define PWR_CR1_MR_VSEL_1                         (0x2UL<<PWR_CR1_MR_VSEL_Pos)                      /*!< 0x00020000 */
#define PWR_CR1_HSION_CTRL_Pos                    (25U)
#define PWR_CR1_HSION_CTRL_Msk                    (0x1UL<<PWR_CR1_HSION_CTRL_Pos)                   /*!< 0x02000000 */
#define PWR_CR1_HSION_CTRL                        PWR_CR1_HSION_CTRL_Msk                            
#define PWR_CR1_STDBY_MRRDY_WAIT_Pos              (26U)
#define PWR_CR1_STDBY_MRRDY_WAIT_Msk              (0x3UL<<PWR_CR1_STDBY_MRRDY_WAIT_Pos)             /*!< 0x0C000000 */
#define PWR_CR1_STDBY_MRRDY_WAIT                  PWR_CR1_STDBY_MRRDY_WAIT_Msk
#define PWR_CR1_STDBY_MRRDY_WAIT_0                (0x1UL<<PWR_CR1_STDBY_MRRDY_WAIT_Pos)             /*!< 0x04000000 */
#define PWR_CR1_STDBY_MRRDY_WAIT_1                (0x2UL<<PWR_CR1_STDBY_MRRDY_WAIT_Pos)             /*!< 0x08000000 */

/********************************* Bit definition for PWR_CR2 register **********************************************/
#define PWR_CR2_PVDE_Pos                          (0U)
#define PWR_CR2_PVDE_Msk                          (0x1UL<<PWR_CR2_PVDE_Pos)                         /*!< 0x00000001 */
#define PWR_CR2_PVDE                              PWR_CR2_PVDE_Msk                                  
#define PWR_CR2_PVDT_Pos                          (1U)
#define PWR_CR2_PVDT_Msk                          (0x7UL<<PWR_CR2_PVDT_Pos)                         /*!< 0x0000000E */
#define PWR_CR2_PVDT                              PWR_CR2_PVDT_Msk
#define PWR_CR2_PVDT_0                            (0x1UL<<PWR_CR2_PVDT_Pos)                         /*!< 0x00000002 */
#define PWR_CR2_PVDT_1                            (0x2UL<<PWR_CR2_PVDT_Pos)                         /*!< 0x00000004 */
#define PWR_CR2_PVDT_2                            (0x4UL<<PWR_CR2_PVDT_Pos)                         /*!< 0x00000008 */

/*!< PVD level configuration */
/* #define PWR_CR2_PVDT_LEV0                          0x00000000U  */                                      /*!< PVD level 2.7V */
#define PWR_CR2_PVDT_LEV1                          0x00000002U                                       /*!< PVD level 2.9V */
#define PWR_CR2_PVDT_LEV2                          0x00000004U                                       /*!< PVD level 3.1V */
#define PWR_CR2_PVDT_LEV3                          0x00000006U                                       /*!< PVD level 3.3V */
#define PWR_CR2_PVDT_LEV4                          0x00000008U                                       /*!< PVD level 3.8V */
#define PWR_CR2_PVDT_LEV5                          0x0000000AU                                       /*!< PVD level 4.0V */
#define PWR_CR2_PVDT_LEV6                          0x0000000CU                                       /*!< PVD level 4.2V */
#define PWR_CR2_PVDT_LEV7                          0x0000000EU                                       /*!< PVD level 4.5V */

/* Legacy defines */
/* #define PWR_CR2_PVDT_2V7                           PWR_CR2_PVDT_LEV0 */
#define PWR_CR2_PVDT_2V9                           PWR_CR2_PVDT_LEV1
#define PWR_CR2_PVDT_3V1                           PWR_CR2_PVDT_LEV2
#define PWR_CR2_PVDT_3V3                           PWR_CR2_PVDT_LEV3
#define PWR_CR2_PVDT_3V8                           PWR_CR2_PVDT_LEV4
#define PWR_CR2_PVDT_4V0                           PWR_CR2_PVDT_LEV5
#define PWR_CR2_PVDT_4V2                           PWR_CR2_PVDT_LEV6
#define PWR_CR2_PVDT_4V5                           PWR_CR2_PVDT_LEV7

#define PWR_CR2_PVD_OUT_SEL_Pos                   (7U)
#define PWR_CR2_PVD_OUT_SEL_Msk                   (0x1UL<<PWR_CR2_PVD_OUT_SEL_Pos)                  /*!< 0x00000080 */
#define PWR_CR2_PVD_OUT_SEL                       PWR_CR2_PVD_OUT_SEL_Msk                           
#define PWR_CR2_FLTEN_Pos                         (8U)
#define PWR_CR2_FLTEN_Msk                         (0x1UL<<PWR_CR2_FLTEN_Pos)                        /*!< 0x00000100 */
#define PWR_CR2_FLTEN                             PWR_CR2_FLTEN_Msk                                 
#define PWR_CR2_FLT_CTRL_Pos                      (9U)
#define PWR_CR2_FLT_CTRL_Msk                      (0x7UL<<PWR_CR2_FLT_CTRL_Pos)                     /*!< 0x00000E00 */
#define PWR_CR2_FLT_CTRL                          PWR_CR2_FLT_CTRL_Msk
#define PWR_CR2_FLT_CTRL_0                        (0x1UL<<PWR_CR2_FLT_CTRL_Pos)                     /*!< 0x00000200 */
#define PWR_CR2_FLT_CTRL_1                        (0x2UL<<PWR_CR2_FLT_CTRL_Pos)                     /*!< 0x00000400 */
#define PWR_CR2_FLT_CTRL_2                        (0x4UL<<PWR_CR2_FLT_CTRL_Pos)                     /*!< 0x00000800 */

/********************************* Bit definition for PWR_CR3 register **********************************************/
#define PWR_CR3_EWUP1_Pos                         (0U)
#define PWR_CR3_EWUP1_Msk                         (0x1UL<<PWR_CR3_EWUP1_Pos)                        /*!< 0x00000001 */
#define PWR_CR3_EWUP1                             PWR_CR3_EWUP1_Msk                                 
#define PWR_CR3_EWUP2_Pos                         (1U)
#define PWR_CR3_EWUP2_Msk                         (0x1UL<<PWR_CR3_EWUP2_Pos)                        /*!< 0x00000002 */
#define PWR_CR3_EWUP2                             PWR_CR3_EWUP2_Msk                                 
#define PWR_CR3_EWUP3_Pos                         (2U)
#define PWR_CR3_EWUP3_Msk                         (0x1UL<<PWR_CR3_EWUP3_Pos)                        /*!< 0x00000004 */
#define PWR_CR3_EWUP3                             PWR_CR3_EWUP3_Msk                                 
#define PWR_CR3_EWUP4_Pos                         (3U)
#define PWR_CR3_EWUP4_Msk                         (0x1UL<<PWR_CR3_EWUP4_Pos)                        /*!< 0x00000008 */
#define PWR_CR3_EWUP4                             PWR_CR3_EWUP4_Msk                                 
#define PWR_CR3_EWUP5_Pos                         (4U)
#define PWR_CR3_EWUP5_Msk                         (0x1UL<<PWR_CR3_EWUP5_Pos)                        /*!< 0x00000010 */
#define PWR_CR3_EWUP5                             PWR_CR3_EWUP5_Msk                                 
#define PWR_CR3_EWUP_Pos                          (0U)
#define PWR_CR3_EWUP_Msk                          (0x1FUL<<PWR_CR3_EWUP_Pos)                        /*!< 0x00000001 */
#define PWR_CR3_EWUP                              PWR_CR3_EWUP_Msk                                 
// #define PWR_CR3_RRS_Pos                           (16U)
// #define PWR_CR3_RRS_Msk                           (0x1UL<<PWR_CR3_RRS_Pos)                          /*!< 0x00010000 */
// #define PWR_CR3_RRS                               PWR_CR3_RRS_Msk                                   

/********************************* Bit definition for PWR_CR4 register **********************************************/
#define PWR_CR4_WUP1_Pos                           (0U)
#define PWR_CR4_WUP1_Msk                           (0x3UL<<PWR_CR4_WUP1_Pos)                          /*!< 0x00000003 */
#define PWR_CR4_WUP1                               PWR_CR4_WUP1_Msk                                        
#define PWR_CR4_WUP1_0                             (0x1UL<<PWR_CR4_WUP1_Pos)                          /*!< 0x00000001 */
#define PWR_CR4_WUP1_1                             (0x2UL<<PWR_CR4_WUP1_Pos)                          /*!< 0x00000002 */
#define PWR_CR4_WUP2_Pos                           (2U)                                                   
#define PWR_CR4_WUP2_Msk                           (0x3UL<<PWR_CR4_WUP2_Pos)                          /*!< 0x0000000C */
#define PWR_CR4_WUP2                               PWR_CR4_WUP2_Msk                                        
#define PWR_CR4_WUP2_0                             (0x1UL<<PWR_CR4_WUP2_Pos)                          /*!< 0x00000004 */
#define PWR_CR4_WUP2_1                             (0x2UL<<PWR_CR4_WUP2_Pos)                          /*!< 0x00000008 */
#define PWR_CR4_WUP3_Pos                           (4U)                                                   
#define PWR_CR4_WUP3_Msk                           (0x3UL<<PWR_CR4_WUP3_Pos)                          /*!< 0x00000030 */
#define PWR_CR4_WUP3                               PWR_CR4_WUP3_Msk                                        
#define PWR_CR4_WUP3_0                             (0x1UL<<PWR_CR4_WUP3_Pos)                          /*!< 0x00000010 */
#define PWR_CR4_WUP3_1                             (0x2UL<<PWR_CR4_WUP3_Pos)                          /*!< 0x00000020 */
#define PWR_CR4_WUP4_Pos                           (6U)                                                   
#define PWR_CR4_WUP4_Msk                           (0x3UL<<PWR_CR4_WUP4_Pos)                          /*!< 0x000000C0 */
#define PWR_CR4_WUP4                               PWR_CR4_WUP4_Msk                                        
#define PWR_CR4_WUP4_0                             (0x1UL<<PWR_CR4_WUP4_Pos)                          /*!< 0x00000040 */
#define PWR_CR4_WUP4_1                             (0x2UL<<PWR_CR4_WUP4_Pos)                          /*!< 0x00000080 */
#define PWR_CR4_WUP5_Pos                           (8U)                                                   
#define PWR_CR4_WUP5_Msk                           (0x3UL<<PWR_CR4_WUP5_Pos)                          /*!< 0x00000300 */
#define PWR_CR4_WUP5                               PWR_CR4_WUP5_Msk                                        
#define PWR_CR4_WUP5_0                             (0x1UL<<PWR_CR4_WUP5_Pos)                          /*!< 0x00000100 */
#define PWR_CR4_WUP5_1                             (0x2UL<<PWR_CR4_WUP5_Pos)                          /*!< 0x00000200 */

/********************************* Bit definition for PWR_SR register ***********************************************/
#define PWR_SR_WUF1_Pos                           (0U)
#define PWR_SR_WUF1_Msk                           (0x1UL<<PWR_SR_WUF1_Pos)                          /*!< 0x00000001 */
#define PWR_SR_WUF1                               PWR_SR_WUF1_Msk                                   
#define PWR_SR_WUF2_Pos                           (1U)
#define PWR_SR_WUF2_Msk                           (0x1UL<<PWR_SR_WUF2_Pos)                          /*!< 0x00000002 */
#define PWR_SR_WUF2                               PWR_SR_WUF2_Msk                                   
#define PWR_SR_WUF3_Pos                           (2U)
#define PWR_SR_WUF3_Msk                           (0x1UL<<PWR_SR_WUF3_Pos)                          /*!< 0x00000004 */
#define PWR_SR_WUF3                               PWR_SR_WUF3_Msk                                   
#define PWR_SR_WUF4_Pos                           (3U)
#define PWR_SR_WUF4_Msk                           (0x1UL<<PWR_SR_WUF4_Pos)                          /*!< 0x00000008 */
#define PWR_SR_WUF4                               PWR_SR_WUF4_Msk                                   
#define PWR_SR_WUF5_Pos                           (4U)
#define PWR_SR_WUF5_Msk                           (0x1UL<<PWR_SR_WUF5_Pos)                          /*!< 0x00000010 */
#define PWR_SR_WUF5                               PWR_SR_WUF5_Msk                                   
#define PWR_SR_WUF_Pos                            (0U)
#define PWR_SR_WUF_Msk                            (0x1FUL<<PWR_SR_WUF_Pos)                          /*!< 0x0000001F */
#define PWR_SR_WUF                                PWR_SR_WUF_Msk                                   
#define PWR_SR_SBF_Pos                            (16U)
#define PWR_SR_SBF_Msk                            (0x1UL<<PWR_SR_SBF_Pos)                           /*!< 0x00000100 */
#define PWR_SR_SBF                                PWR_SR_SBF_Msk                                    
#define PWR_SR_PVDO_Pos                           (22U)
#define PWR_SR_PVDO_Msk                           (0x1UL<<PWR_SR_PVDO_Pos)                          /*!< 0x00400000 */
#define PWR_SR_PVDO                               PWR_SR_PVDO_Msk                                   
#define PWR_SR_MR_RDY_Pos                         (23U)
#define PWR_SR_MR_RDY_Msk                         (0x1UL<<PWR_SR_MR_RDY_Pos)                        /*!< 0x00800000 */
#define PWR_SR_MR_RDY                             PWR_SR_MR_RDY_Msk                                 

/********************************* Bit definition for PWR_SCR register **********************************************/
#define PWR_SCR_CWUF1_Pos                         (0U)
#define PWR_SCR_CWUF1_Msk                         (0x1UL<<PWR_SCR_CWUF1_Pos)                        /*!< 0x00000001 */
#define PWR_SCR_CWUF1                             PWR_SCR_CWUF1_Msk                                 
#define PWR_SCR_CWUF2_Pos                         (1U)
#define PWR_SCR_CWUF2_Msk                         (0x1UL<<PWR_SCR_CWUF2_Pos)                        /*!< 0x00000002 */
#define PWR_SCR_CWUF2                             PWR_SCR_CWUF2_Msk                                 
#define PWR_SCR_CWUF3_Pos                         (2U)
#define PWR_SCR_CWUF3_Msk                         (0x1UL<<PWR_SCR_CWUF3_Pos)                        /*!< 0x00000004 */
#define PWR_SCR_CWUF3                             PWR_SCR_CWUF3_Msk                                 
#define PWR_SCR_CWUF4_Pos                         (3U)
#define PWR_SCR_CWUF4_Msk                         (0x1UL<<PWR_SCR_CWUF4_Pos)                        /*!< 0x00000008 */
#define PWR_SCR_CWUF4                             PWR_SCR_CWUF4_Msk                                 
#define PWR_SCR_CWUF5_Pos                         (4U)
#define PWR_SCR_CWUF5_Msk                         (0x1UL<<PWR_SCR_CWUF5_Pos)                        /*!< 0x00000010 */
#define PWR_SCR_CWUF5                             PWR_SCR_CWUF5_Msk                                 
#define PWR_SCR_CWUF_Pos                          (0U)
#define PWR_SCR_CWUF_Msk                          (0x1FUL<<PWR_SCR_CWUF_Pos)                        /*!< 0x0000001F */
#define PWR_SCR_CWUF                              PWR_SCR_CWUF_Msk                                 
#define PWR_SCR_CSBF_Pos                          (16U)
#define PWR_SCR_CSBF_Msk                          (0x1UL<<PWR_SCR_CSBF_Pos)                         /*!< 0x00010000 */
#define PWR_SCR_CSBF                              PWR_SCR_CSBF_Msk                                  

/****************************** ADC Instances *********************************/
#define IS_ADC_ALL_INSTANCE(INSTANCE) (((INSTANCE) == ADC1) || \
                                       ((INSTANCE) == ADC2))

#define IS_ADC_COMMON_INSTANCE(INSTANCE) ((INSTANCE) == ADC_COMMON)

#define IS_ADC_MULTIMODE_MASTER_INSTANCE(INSTANCE) ((INSTANCE) == ADC1)

#define IS_ADC_DMA_CAPABILITY_INSTANCE(INSTANCE) (((INSTANCE) == ADC1) || \
                                                  ((INSTANCE) == ADC2))

/****************************** DAC Instances *********************************/
#define IS_DAC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == DAC)

/****************************** COMP Instances *******************************/
#define IS_COMP_ALL_INSTANCE(INSTANCE) (((INSTANCE) == COMP1) || \
                                        ((INSTANCE) == COMP2) || \
                                        ((INSTANCE) == COMP3) || \
                                        ((INSTANCE) == COMP4))

#define IS_COMP_COMMON_INSTANCE(INSTANCE) (((INSTANCE) == COMP12_COMMON) || \
                                           ((INSTANCE) == COMP34_COMMON))

/****************************** OPA Instances *******************************/
#define IS_OPA_ALL_INSTANCE(INSTANCE) (((INSTANCE) == OPA1) || \
                                       ((INSTANCE) == OPA2) || \
                                       ((INSTANCE) == OPA3) || \
                                       ((INSTANCE) == OPA4))

/****************************** CRC Instances *******************************/
#define IS_CRC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == CRC)

/****************************** DBGMCU Instances *******************************/
#define IS_DBGMCU_ALL_INSTANCE(INSTANCE) ((INSTANCE) == DBGMCU)

/****************************** DMA Instances *********************************/
#define IS_DMA_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DMA_Channel1) || \
                                       ((INSTANCE) == DMA_Channel2) || \
                                       ((INSTANCE) == DMA_Channel3) || \
                                       ((INSTANCE) == DMA_Channel4) || \
                                       ((INSTANCE) == DMA_Channel5))

/****************************** EXTI Instances ********************************/
#define IS_EXTI_ALL_INSTANCE(INSTANCE) ((INSTANCE) == EXTI)

/****************************** FLASH Instances ********************************/
#define IS_FLASH_ALL_INSTANCE(INSTANCE) ((INSTANCE) == FLASH)

/******************************* GPIO Instances *******************************/
#define IS_GPIO_ALL_INSTANCE(INSTANCE) (((INSTANCE) == GPIOA) || \
                                        ((INSTANCE) == GPIOB) || \
                                        ((INSTANCE) == GPIOC) || \
                                        ((INSTANCE) == GPIOD))

/**************************** GPIO Alternate Function Instances ***************/
#define IS_GPIO_AF_INSTANCE(INSTANCE) IS_GPIO_ALL_INSTANCE(INSTANCE)

/**************************** GPIO Lock Instances *****************************/
#define IS_GPIO_LOCK_INSTANCE(INSTANCE) IS_GPIO_ALL_INSTANCE(INSTANCE)

/******************************** I2C Instances *******************************/
#define IS_I2C_ALL_INSTANCE(INSTANCE) (((INSTANCE) == I2C1) || \
                                       ((INSTANCE) == I2C2))

/********************* I2C WAKEUP FROMSTOP Instances **************************/
#define IS_I2C_WAKEUP_FROMSTOP_INSTANCE(INSTANCE) (((INSTANCE) == I2C1) || \
                                                   ((INSTANCE) == I2C2))

/******************************* SMBUS Instances ******************************/
#define IS_SMBUS_ALL_INSTANCE         IS_I2C_ALL_INSTANCE

/****************************** PWR Instances ********************************/
#define IS_PWR_ALL_INSTANCE(INSTANCE) ((INSTANCE) == PWR)

/****************************** RTC Instances ********************************/
#define IS_RTC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == RTC)

/******************************** I2S Instances *******************************/
#define IS_I2S_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SPI1) || \
                                       ((INSTANCE) == SPI2))

/****************************** IWDG Instances ********************************/
#define IS_IWDG_ALL_INSTANCE(INSTANCE)  ((INSTANCE) == IWDG)

/****************************** LPTIM Instances ********************************/
#define IS_LPTIM_INSTANCE(INSTANCE)  ((INSTANCE) == LPTIM)

/****************************** LPUART Instances ********************************/
#define IS_LPUART_ALL_INSTANCE(INSTANCE)  ((INSTANCE) == LPUART1)

/****************************** LPUART Instances : Driver Enable ******** **/
#define IS_LPUART_DRIVER_ENABLE_INSTANCE(INSTANCE)  ((INSTANCE) == LPUART1)

/****************************** LPUART Instances : Wake-up from Stop mode *****/
#define IS_LPUART_WAKEUP_FROMSTOP_INSTANCE(INSTANCE)  ((INSTANCE) == LPUART1)

/******************************** SPI Instances *******************************/
#define IS_SPI_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SPI1) || \
                                       ((INSTANCE) == SPI2))

/****************************** START TIM Instances ***************************/
/****************************** TIM Instances *********************************/
#define IS_TIM_INSTANCE(INSTANCE)\
  (((INSTANCE) == TIM1)    || \
   ((INSTANCE) == TIM2)    || \
   ((INSTANCE) == TIM3)    || \
   ((INSTANCE) == TIM6)    || \
   ((INSTANCE) == TIM7)    || \
   ((INSTANCE) == TIM8) )

/****************** TIM Instances : supporting 32 bits counter ****************/

#define IS_TIM_32B_COUNTER_INSTANCE(INSTANCE) ((INSTANCE) == TIM2)

/****************** TIM Instances : supporting the break function *************/
#define IS_TIM_BREAK_INSTANCE(INSTANCE)    (((INSTANCE) == TIM1)   || \
                                            ((INSTANCE) == TIM2)   || \
                                            ((INSTANCE) == TIM3)   || \
                                            ((INSTANCE) == TIM8))

/************** TIM Instances : supporting Break source selection *************/
#define IS_TIM_BREAKSOURCE_INSTANCE(INSTANCE) (((INSTANCE) == TIM1)   || \
                                               ((INSTANCE) == TIM2)   || \
                                               ((INSTANCE) == TIM3)   || \
                                               ((INSTANCE) == TIM8))

/****************** TIM Instances : supporting 2 break inputs *****************/
#define IS_TIM_BKIN2_INSTANCE(INSTANCE)       (((INSTANCE) == TIM1)   || \
                                               ((INSTANCE) == TIM2)   || \
                                               ((INSTANCE) == TIM3)   || \
                                               ((INSTANCE) == TIM8))

/************* TIM Instances : at least 1 capture/compare channel *************/
#define IS_TIM_CC1_INSTANCE(INSTANCE)   (((INSTANCE) == TIM1)   || \
                                         ((INSTANCE) == TIM2)   || \
                                         ((INSTANCE) == TIM3)   || \
                                         ((INSTANCE) == TIM8))

/************ TIM Instances : at least 2 capture/compare channels *************/
#define IS_TIM_CC2_INSTANCE(INSTANCE)   (((INSTANCE) == TIM1)   || \
                                         ((INSTANCE) == TIM2)   || \
                                         ((INSTANCE) == TIM3)   || \
                                         ((INSTANCE) == TIM8))

/************ TIM Instances : at least 3 capture/compare channels *************/
#define IS_TIM_CC3_INSTANCE(INSTANCE)   (((INSTANCE) == TIM1)   || \
                                         ((INSTANCE) == TIM2)   || \
                                         ((INSTANCE) == TIM3)   || \
                                         ((INSTANCE) == TIM8))

/************ TIM Instances : at least 4 capture/compare channels *************/
#define IS_TIM_CC4_INSTANCE(INSTANCE)   (((INSTANCE) == TIM1)   || \
                                         ((INSTANCE) == TIM2)   || \
                                         ((INSTANCE) == TIM3)   || \
                                         ((INSTANCE) == TIM8))

/****************** TIM Instances : at least 5 capture/compare channels *******/
#define IS_TIM_CC5_INSTANCE(INSTANCE)   (((INSTANCE) == TIM1)   || \
                                         ((INSTANCE) == TIM8))

/****************** TIM Instances : at least 6 capture/compare channels *******/
#define IS_TIM_CC6_INSTANCE(INSTANCE)   (((INSTANCE) == TIM1)   || \
                                         ((INSTANCE) == TIM8))

/************ TIM Instances : DMA requests generation (TIMx_DIER.COMDE) *******/
#define IS_TIM_CCDMA_INSTANCE(INSTANCE)    (((INSTANCE) == TIM1)   || \
                                            ((INSTANCE) == TIM2)   || \
                                            ((INSTANCE) == TIM3)   || \
                                            ((INSTANCE) == TIM8))
                                            
/****************** TIM Instances : DMA requests generation (TIMx_DIER.UDE) ***/
#define IS_TIM_DMA_INSTANCE(INSTANCE)      (((INSTANCE) == TIM1)   || \
                                            ((INSTANCE) == TIM2)   || \
                                            ((INSTANCE) == TIM3)   || \
                                            ((INSTANCE) == TIM6)   || \
                                            ((INSTANCE) == TIM7)   || \
                                            ((INSTANCE) == TIM8))

/************ TIM Instances : DMA requests generation (TIMx_DIER.CCxDE) *******/
#define IS_TIM_DMA_CC_INSTANCE(INSTANCE)   (((INSTANCE) == TIM1)   || \
                                            ((INSTANCE) == TIM2)   || \
                                            ((INSTANCE) == TIM3)   || \
                                            ((INSTANCE) == TIM8))

/******************** TIM Instances : DMA burst feature ***********************/
#define IS_TIM_DMABURST_INSTANCE(INSTANCE) (((INSTANCE) == TIM1)   || \
                                            ((INSTANCE) == TIM2)   || \
                                            ((INSTANCE) == TIM3)   || \
                                            ((INSTANCE) == TIM8))

/******************* TIM Instances : output(s) available **********************/
#define IS_TIM_CCX_INSTANCE(INSTANCE, CHANNEL) \
    ((((INSTANCE) == TIM1) &&                  \
     (((CHANNEL) == TIM_CHANNEL_1) ||          \
      ((CHANNEL) == TIM_CHANNEL_2) ||          \
      ((CHANNEL) == TIM_CHANNEL_3) ||          \
      ((CHANNEL) == TIM_CHANNEL_4) ||          \
      ((CHANNEL) == TIM_CHANNEL_5) ||          \
      ((CHANNEL) == TIM_CHANNEL_6)))           \
     ||                                        \
     (((INSTANCE) == TIM2) &&                  \
     (((CHANNEL) == TIM_CHANNEL_1) ||          \
      ((CHANNEL) == TIM_CHANNEL_2) ||          \
      ((CHANNEL) == TIM_CHANNEL_3) ||          \
      ((CHANNEL) == TIM_CHANNEL_4)))           \
     ||                                        \
     (((INSTANCE) == TIM3) &&                  \
     (((CHANNEL) == TIM_CHANNEL_1) ||          \
      ((CHANNEL) == TIM_CHANNEL_2) ||          \
      ((CHANNEL) == TIM_CHANNEL_3) ||          \
      ((CHANNEL) == TIM_CHANNEL_4)))           \
     ||                                        \
     (((INSTANCE) == TIM8) &&                  \
     (((CHANNEL) == TIM_CHANNEL_1) ||          \
      ((CHANNEL) == TIM_CHANNEL_2) ||          \
      ((CHANNEL) == TIM_CHANNEL_3) ||          \
      ((CHANNEL) == TIM_CHANNEL_4) ||          \
      ((CHANNEL) == TIM_CHANNEL_5) ||          \
      ((CHANNEL) == TIM_CHANNEL_6))))

/****************** TIM Instances : supporting complementary output(s) ********/
#define IS_TIM_CCXN_INSTANCE(INSTANCE, CHANNEL) \
   ((((INSTANCE) == TIM1) &&                    \
     (((CHANNEL) == TIM_CHANNEL_1) ||           \
      ((CHANNEL) == TIM_CHANNEL_2) ||           \
      ((CHANNEL) == TIM_CHANNEL_3) ||           \
      ((CHANNEL) == TIM_CHANNEL_4)))            \
    ||                                          \
    (((INSTANCE) == TIM8) &&                    \
     (((CHANNEL) == TIM_CHANNEL_1) ||           \
      ((CHANNEL) == TIM_CHANNEL_2) ||           \
      ((CHANNEL) == TIM_CHANNEL_3) ||           \
      ((CHANNEL) == TIM_CHANNEL_4))))

/****************** TIM Instances : supporting clock division *****************/
#define IS_TIM_CLOCK_DIVISION_INSTANCE(INSTANCE)   (((INSTANCE) == TIM1)   || \
                                                    ((INSTANCE) == TIM2)   || \
                                                    ((INSTANCE) == TIM3)   || \
                                                    ((INSTANCE) == TIM8))

/****** TIM Instances : supporting external clock mode 1 for ETRF input *******/
#define IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(INSTANCE) (((INSTANCE) == TIM1)   || \
                                                        ((INSTANCE) == TIM2)   || \
                                                        ((INSTANCE) == TIM3)   || \
                                                        ((INSTANCE) == TIM8))

/****** TIM Instances : supporting external clock mode 2 for ETRF input *******/
#define IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(INSTANCE) (((INSTANCE) == TIM1)   || \
                                                        ((INSTANCE) == TIM2)   || \
                                                        ((INSTANCE) == TIM3)   || \
                                                        ((INSTANCE) == TIM8))

/****************** TIM Instances : supporting external clock mode 1 for TIX inputs*/
#define IS_TIM_CLOCKSOURCE_TIX_INSTANCE(INSTANCE)      (((INSTANCE) == TIM1)   || \
                                                        ((INSTANCE) == TIM2)   || \
                                                        ((INSTANCE) == TIM3)   || \
                                                        ((INSTANCE) == TIM8))

/****************** TIM Instances : supporting internal trigger inputs(ITRX) *******/
#define IS_TIM_CLOCKSOURCE_ITRX_INSTANCE(INSTANCE)     (((INSTANCE) == TIM1)   || \
                                                        ((INSTANCE) == TIM2)   || \
                                                        ((INSTANCE) == TIM3)   || \
                                                        ((INSTANCE) == TIM8))

/****************** TIM Instances : supporting commutation event generation ***/
#define IS_TIM_COMMUTATION_EVENT_INSTANCE(INSTANCE)    (((INSTANCE) == TIM1)   || \
                                                        ((INSTANCE) == TIM2)   || \
                                                        ((INSTANCE) == TIM3)   || \
                                                        ((INSTANCE) == TIM8))

/****************** TIM Instances : supporting counting mode selection ********/
#define IS_TIM_COUNTER_MODE_SELECT_INSTANCE(INSTANCE)  (((INSTANCE) == TIM1)   || \
                                                        ((INSTANCE) == TIM2)   || \
                                                        ((INSTANCE) == TIM3)   || \
                                                        ((INSTANCE) == TIM8))

/****************** TIM Instances : supporting encoder interface **************/
#define IS_TIM_ENCODER_INTERFACE_INSTANCE(INSTANCE)    (((INSTANCE) == TIM1)   || \
                                                        ((INSTANCE) == TIM2)   || \
                                                        ((INSTANCE) == TIM3)   || \
                                                        ((INSTANCE) == TIM8))

/****************** TIM Instances : supporting multiple trigger ADC interface **/
#define IS_TIM_MULTIPLE_TRIGGER_ADC_INTERFACE_INSTANCE(INSTANCE)    (((INSTANCE) == TIM1)   || \
                                                                     ((INSTANCE) == TIM2)   || \
                                                                     ((INSTANCE) == TIM3)   || \
                                                                     ((INSTANCE) == TIM8))

/****************** TIM Instances : supporting Hall sensor interface **********/
#define IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(INSTANCE)  (((INSTANCE) == TIM1)   || \
                                                          ((INSTANCE) == TIM2)   || \
                                                          ((INSTANCE) == TIM3)   || \
                                                          ((INSTANCE) == TIM8))

/**************** TIM Instances : external trigger input available ************/
#define IS_TIM_ETR_INSTANCE(INSTANCE)                  (((INSTANCE) == TIM1)   || \
                                                        ((INSTANCE) == TIM2)   || \
                                                        ((INSTANCE) == TIM3)   || \
                                                        ((INSTANCE) == TIM8))

/************* TIM Instances : supporting ETR source selection ***************/
#define IS_TIM_ETRSEL_INSTANCE(INSTANCE)               (((INSTANCE) == TIM1)   || \
                                                        ((INSTANCE) == TIM2)   || \
                                                        ((INSTANCE) == TIM3)   || \
                                                        ((INSTANCE) == TIM8))

/****** TIM Instances : Master mode available (TIMx_CR2.MMS available )********/
#define IS_TIM_MASTER_INSTANCE(INSTANCE)   (((INSTANCE) == TIM1)  || \
                                            ((INSTANCE) == TIM2)  || \
                                            ((INSTANCE) == TIM3)  || \
                                            ((INSTANCE) == TIM6)  || \
                                            ((INSTANCE) == TIM7)  || \
                                            ((INSTANCE) == TIM8))

/*********** TIM Instances : Slave mode available (TIMx_SMCR available )*******/
#define IS_TIM_SLAVE_INSTANCE(INSTANCE)                (((INSTANCE) == TIM1)   || \
                                                        ((INSTANCE) == TIM2)   || \
                                                        ((INSTANCE) == TIM3)   || \
                                                        ((INSTANCE) == TIM8))

/****************** TIM Instances : supporting OCxREF clear *******************/
#define IS_TIM_OCXREF_CLEAR_INSTANCE(INSTANCE)         (((INSTANCE) == TIM1)   || \
                                                        ((INSTANCE) == TIM2)   || \
                                                        ((INSTANCE) == TIM3)   || \
                                                        ((INSTANCE) == TIM8))

/****************** TIM Instances : supporting bitfield OCCS in SMCR register *******************/
#define IS_TIM_OCCS_INSTANCE(INSTANCE)                 (((INSTANCE) == TIM1)   || \
                                                        ((INSTANCE) == TIM2)   || \
                                                        ((INSTANCE) == TIM3)   || \
                                                        ((INSTANCE) == TIM8))

/****************** TIM Instances : remapping capability **********************/
#define IS_TIM_REMAP_INSTANCE(INSTANCE)                (((INSTANCE) == TIM1)   || \
                                                        ((INSTANCE) == TIM2)   || \
                                                        ((INSTANCE) == TIM3)   || \
                                                        ((INSTANCE) == TIM8))

/****************** TIM Instances : supporting repetition counter *************/
#define IS_TIM_REPETITION_COUNTER_INSTANCE(INSTANCE)  (((INSTANCE) == TIM1)    || \
                                                       ((INSTANCE) == TIM8))

/****************** TIM Instances : supporting ADC triggering through TRGO2 ***/
#define IS_TIM_TRGO2_INSTANCE(INSTANCE)    (((INSTANCE) == TIM1)    || \
                                            ((INSTANCE) == TIM8))

/******************* TIM Instances : Timer input XOR function *****************/
#define IS_TIM_XOR_INSTANCE(INSTANCE)                  (((INSTANCE) == TIM1)   || \
                                                        ((INSTANCE) == TIM2)   || \
                                                        ((INSTANCE) == TIM3)   || \
                                                        ((INSTANCE) == TIM8))

/******************* TIM Instances : Timer input selection ********************/
#define IS_TIM_TISEL_INSTANCE(INSTANCE)                (((INSTANCE) == TIM1)   || \
                                                        ((INSTANCE) == TIM2)   || \
                                                        ((INSTANCE) == TIM3)   || \
                                                        ((INSTANCE) == TIM8))

/****************** TIM Instances : Advanced timer instances *******************/
#define IS_TIM_ADVANCED_INSTANCE(INSTANCE)       (((INSTANCE) == TIM1)    || \
                                                 ((INSTANCE) == TIM8))


/****************** TIM Instances : supporting HSE/32 request instances *******************/
#define IS_TIM_HSE32_INSTANCE(INSTANCE)         (1)
/****************************** END TIM Instances *****************************/


/******************** USART Instances : Synchronous mode **********************/
#define IS_USART_INSTANCE(INSTANCE) ((INSTANCE) == USART1)

/*********************** USART Instances : FIFO mode **************************/
#define IS_USART_FIFO_INSTANCE(INSTANCE) ((INSTANCE) == USART1)

/******************** USART Instances : Asynchronous mode *********************/
#define IS_SCI_INSTANCE(INSTANCE) ((INSTANCE) == USART1)

/******************** USART Instances : HWFLOW mode ***************************/
#define IS_SCI_HWFLOW_INSTANCE(INSTANCE) ((INSTANCE) == USART1)

/******************** USART Instances : Asynchronous mode *********************/
#define IS_SCI_FIFO_INSTANCE(INSTANCE) ((INSTANCE) == USART1)

/****************** USART Instances : Driver Enable detection *****************/
#define IS_SCI_DRIVER_ENABLE_INSTANCE(INSTANCE) ((INSTANCE) == USART1)

/****************** USART Instances : Auto Baud Rate detection ****************/
#define IS_SCI_AUTOBAUDRATE_DETECTION_INSTANCE(INSTANCE) ((INSTANCE) == USART1)

/******************** USART Instances :  Half-Duplex mode *********************/
#define IS_SCI_HALFDUPLEX_INSTANCE(INSTANCE) ((INSTANCE) == USART1)
                                              
/******************** USART Instances : Asynchronous mode *********************/
#define IS_SCI_LIN_INSTANCE(INSTANCE)        ((INSTANCE) == USART1)

/***************** UART Instances : Multi-Processor mode **********************/
#define IS_SCI_MULTIPROCESSOR_INSTANCE(INSTANCE)  ((INSTANCE) == USART1)

/******************** UART Instances : Asynchronous mode **********************/
#define IS_UART_INSTANCE(INSTANCE) (((INSTANCE) == UART1) || \
                                    ((INSTANCE) == UART2))

/******************* UART Instances : DMA mode available **********************/
#define IS_UART_DMA_INSTANCE(INSTANCE) (((INSTANCE) == UART1) || \
                                        ((INSTANCE) == UART2))

/************************ USART Instances : LIN mode **************************/
#define IS_USART_LIN_INSTANCE(INSTANCE) ((INSTANCE) == USART1)

/********************* UART Instances : Smard card mode ***********************/
#define IS_SMARTCARD_INSTANCE(INSTANCE) ((INSTANCE) == USART1)

/****************** UART Instances : Auto Baud Rate detection *****************/
#define IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(INSTANCE) ((INSTANCE) == USART1)

/*********************** UART Instances : IRDA mode ***************************/
#define IS_IRDA_INSTANCE(INSTANCE) ((INSTANCE) == USART1)

/****************** LPUART Instances : Hardware Flow control ********************/
#define IS_LPUART_HWFLOW_INSTANCE(INSTANCE) ((INSTANCE) == LPUART1)

/****************** LPUART Instances : Hardware Flow control ********************/
#define IS_LPUART_HALFDUPLEX_INSTANCE(INSTANCE) ((INSTANCE) == LPUART1)

/******************** LPUART Instance *****************************************/
#define IS_LPUART_INSTANCE(INSTANCE)    ((INSTANCE) == LPUART1)

/****************************** RTC Instances *********************************/
#define IS_RTC_ALL_INSTANCE(INSTANCE)  ((INSTANCE) == RTC)

/**************************** WWDG Instances *****************************/
#define IS_WWDG_ALL_INSTANCE(INSTANCE)  ((INSTANCE) == WWDG)

/****************************** PWM Instances *******************************/
#define IS_EPWM_INSTANCE(INSTANCE) (((INSTANCE) == EPWM1) || ((INSTANCE) == EPWM2) || ((INSTANCE) == EPWM3) || \
                                     ((INSTANCE) == EPWM4) || ((INSTANCE) == EPWM5) || ((INSTANCE) == EPWM6))

/**
  * @}
  */

#ifdef __cplusplus
}
#endif

#endif /* __PY32F420xC_H */

